Abstract: The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment.

Abstract: Embodiments of the present invention provide methods for enhancing void-free metallic filling of narrow openings by electrochemical deposition (ECD). The methods provide enhanced replenishment of plating inhibitor at the field, while depleting the inhibitor inside narrow openings. The resulting inhibitor gradients facilitate void-free ECD filling of narrow openings with large aspect ratios. The inventive methods utilize vigorous electrolyte agitation at the field and top corners of the openings, while maintaining a relatively stagnant electrolyte inside the openings. Vigorous agitation is produced, for example, by high pressure jets flow and/or by mechanical means, such as brush (or pad, or wiper blade) wiping, or by a combination of jets and wiping brushes.

Abstract: The invention is related to a method of plating of a metal layer on a substrate. The method is particularly preferred for the formation of metallization structures for integrated circuits.

Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a twostep process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.

Abstract: A method of forming a metal layer on a substrate is disclosed. The metal layer is formed using a combined electrochemical plating/electrochemical mechanical polishing (ECP/EMP) process. In the ECP/EMP process, the metal layer is deposited on the substrate by contacting the substrate with a porous pad and then alternately applying a first electrical potential and a second electrical potential to an electrolyte plating solution. The first electrical potential functions to deposit metal on the substrate while the second electrical potential functions to remove metal from topographic portions thereof.

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, using an indirect external influence, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion, thus causing greater plating of the cavity portion relative to the top portion.

Abstract: A method of forming an oxide free copper interconnect, comprising the following steps. A substrate is provided and a patterned dielectric layer is formed over the substrate. The patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A copper seed layer is formed over the sidewalls of the opening. The copper seed layer is subjected to an electrochemical technique to eliminate any copper oxide formed over the copper seed layer. A bulk copper layer is electrochemically plated over the copper-oxide-free copper seed layer, filling the opening and forming the oxide-free copper interconnect.

Abstract: In a method for forming a light waveguide, a light waveguide forming substrate is disposed so that a photosemiconductor thin film or a conductive thin film on the substrate is in contact with an aqueous electrolyte solution containing a film forming material having a property that solubility or dispersibility to a water solution decreases according to the pH change, and a voltage is applied between the photosemiconductor thin film or the conductive thin film and a counter electrode by light irradiation.

Abstract: Method of synthesis of confined colloidal crystals using electrodeposition. The present invention provides a method of growing confined colloidal crystal structures using electrodeposition of monodispersed charged colloid spheres onto a substrate patterned with an array of electroconductive surface relief features on a surface of a substrate. In this approach, control over large-scale ordering is achieved via a planar pattern whose scale is on the order of tens of microns, a regime readily accessed through coarse lithography, laser micromachining, and holography.

Abstract: The invention provides for a back-end metallisation process in which a recess is filled with copper and which includes the step of forming a plating base on the surfaces of the recess for the subsequent galvanic deposition of the said copper, and wherein subsequent to the formation of the plating base, but prior to the galvanic deposition of the copper, a modifying agent is introduced to the recess and which serves to absorb in the surface regions not covered by the plating base and to thereby modify the surface to promote copper growth thereon so as to effectively repair the initial plating base before the copper plating fill commences.

Abstract: A method of electrochemically filling features on a wafer surface to form a substantially planar copper layer is provided. The features to be filled includes a first feature that is an unfilled feature with the smallest width and a second feature having the next larger width after the smallest feature. The first and the second features are less than 10 micrometers in width. The method comprises applying a first cathodic current to form a first copper layer on the wafer surface. The first copper layer has a planar portion over a first feature and a non-planar portion over a second feature. After a surface of the first copper layer is treated by applying a first pulsed current, a second cathodic current is applied to form a second copper layer on the first copper layer. The second copper layer has a planar portion over both the first and second features.

Abstract: Electrolytic copper plating methods are provided, wherein copper is electrolytically deposited on a substrate, and the electrolytic copper plating solution supplied to the electrolytic copper plating is subjected to dummy electrolysis using an insoluble anode. The method described above can maintain and restore the electrolytic copper plating solution so as to maintain satisfactory appearance of plated copper, fineness of deposited copper film, and via-filling.

Abstract: The present invention provides an edge cleaning system and method in which a directed stream of a mild etching solution is supplied to an edge area of a rotating workpiece, including the front surface edge and bevel, while a potential difference between the workpiece and the directed stream is maintained. In one aspect, the present invention provides an edge cleaning system that is disposed in the same processing chamber that is used for deposition or removal processing of the workpiece. In another aspect, the mild etching solution used for edge removal is also used to clean the front surface of the wafer, either simultaneously with or sequentially with the edge removal process.

Abstract: A plate and a substrate are placed to face each other and a treatment liquid is jetted from a treatment liquid jetting portion of the plate, thereby treating the substrate. At this time, bubbles in the treatment liquid are discharged from an opening formed in the plate, thereby enabling reduction in treatment nonuniformity caused by the bubbles. The formation of a slope toward the opening on the plate makes it possible to further promote the removal of the bubbles from the treatment liquid.

Abstract: The interior of cavities and through-holes in electrically conductive substrates having high-aspect ratios of 8:1 or greater can be electroplated with a uniform layer of metal on their interior surfaces by using a pulse reverse voltage waveform having a pulse train of long cathodic pulses followed by short anodic pulses even in the absence of conventional additives such as levelers and brighteners.

Abstract: Disclosed are methods for depositing a copper seed layer on a substrate having a conductive layer. Such methods are particularly suitable for depositing a copper seed layer on a substrate having small apertures, and preferably very small apertures.

Abstract: An active part of a sensor is formed, for example, by micro-machined silicon wafers bearing electronic elements, electrical conductors, connection pads, and pins. The pads are electrically connected to the pin ends by conductive elements. Then the wafer and the pin ends are plunged into an electrolytic bath to make an electrolytic deposit of conductive metal on the pin ends, the pads, and the conductive elements that connect them. Finally, this metal is oxidized or nitrized to form an insulating coat on the pin ends, the pads, and the conductive elements that connect them. Such a sensor may find particular application as a sensor designed to work in harsh environments.

Abstract: Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.

Abstract: Apparatus and methods are disclosed for electroplating conductive films on semiconductor wafers, wherein field adjustment apparatus is located in a reservoir between a cathode and an anode to influence the electric field used in the plating process. Field adjustment apparatus is presented having one or more apertures, which may be selectively plugged to adjust the electrical fields during plating.

Abstract: A method for forming electroplating cathode contacts around the periphery of a semiconductor wafer including forming an insulating layer over a conductive layer extending at least around the periphery of a semiconductor wafer substrate; etching a plurality of openings around a peripheral portion of the semiconductor wafer substrate through the insulating layer to extend through a thickness of the insulating layer in closed communication with the conductive layer said conductive area in electrical communication with a central portion of the semiconductor wafer substrate; filling the plurality of openings with metal to form electrically conductive pathways; planarizing the electrically conductive pathway surfaces; and, forming a metal layer over the electrically conductive pathway surfaces to form a plurality of contact pads for contacting a cathode for carrying out an electroplating process.

Abstract: This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Abstract: A method of fabricating a semiconductor device, having a reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and annealing the electroplated Cu—Zn alloy thin film (30); and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform reduced-oxygen Cu—Zn alloy thin film (30), having a controlled Zn content, for reducing electromigration on the Cu—Zn/Cu structure by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A method and apparatus for electrochemically depositing a metal into a high aspect ratio structure on a substrate are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a first conductive material disposed thereon in a processing chamber containing an electrochemical bath, depositing a second conductive material on the first conductive material as the conductive material is contacted with the electrochemical bath by applying a plating bias to the substrate while immersing the substrate into the electrochemical bath, and depositing a third conductive material in situ on the second conductive material by an electrochemical deposition technique to fill the feature. The bias may include a charge density between about 20 mA*sec/cm2 and about 160 mA*sec/cm2. The electrochemical deposition technique may include a pulse modulation technique.

Abstract: An electrochemical transistor device is provided, comprising a source contact, a drain contact, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and said at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and said gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to said gate electrode(s).

Abstract: The present invention relates to a method and an apparatus for depositing a metal layer on a semiconductor structure. A semiconductor structure comprising at least one recess and at least one elevation is provided. The semiconductor structure is electroplated for depositing a layer of metal and for filling at least one recess with metal. The semiconductor structure is electropolished for preferentially removing the metal from at least one elevation, and chemical mechanical polishing is performed to remove a surplus of the metal from at least one elevation and for planarizing a surface of the semiconductor structure. The present invention advantageously allows the reduction of the demands on the chemical mechanical polishing process.

Abstract: A facility for selecting and refining electrical parameters for processing a microelectronic workpiece in a processing chamber is described. The facility initially configures the electrical parameters in accordance with either a mathematical model of the processing chamber or experimental data derived from operating the actual processing chamber. After a workpiece is processed with the initial parameter configuration, the results are measured and a sensitivity matrix based upon the mathematical model of the processing chamber is used to select new parameters that correct for any deficiencies measured in the processing of the first workpiece. These parameters are then used in processing a second workpiece, which may be similarly measured, and the results used to further refine the parameters.

Abstract: Disclosed are methods for repairing seed layers prior to subsequent metallization during the manufacture of electronic devices. Also disclosed are electronic devices containing substantially continuous seed layers.

Abstract: Resin cloths, powders, specular bodies and other objects resistant to conventional plating can be plated with metals by a simple method.

Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

Abstract: A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer.

Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: Systems and methods to operate upon a nonplanar top surface of a conductive surface layer of a workpiece, so as to, for example, preserve the structural integrity of a dielectric film layer disposed below the conductive surface layer, are presented. According to an exemplary method, a layer of conducting material such as a conducting paste is applied over the nonplanar top surface of the conductive surface layer to obtain a planar top surface. At least a portion of the conducting material layer and at least a portion of the conductive surface layer are removed in a planar manner to at least partially planarize the nonplanar top surface. The conducting material layer may be annealed so that the conducting material layer diffuses with the conductive surface layer prior to removal of at least the portions of conducting material layer and the conductive surface layer.

Abstract: The present invention provides a semiconductor manufacturing apparatus capable of shortening TAT by completing a plurality of processes including plating, annealing, and CMP-in-twice or the like in copper wiring process in a single manufacturing apparatus, and is also capable of suppressing costs for consumable materials by replacing the CMP step with other step. The apparatus of the present invention comprises an electrolytic plating chamber (11) for performing electrolytic plating of a substrate (91), an electrolytic polishing chamber (21) for performing electrolytic polishing of the substrate, and a conveying chamber (81) having installed therein a conveying instrument (83) responsible for loading/unloading of the substrate to or from the electrolytic plating chamber, and to or from he electrolytic polishing chamber, and is connected respectively to the electrolytic plating chamber and the electrolytic polishing chamber.

Abstract: A copper electroplating bath and a method to plate substrates with the bath are provided. The bath and method are particularly effective to plate electronic components such as semiconductive wafer VLSI and ULSI interconnects with void-free fill copper plating for circuitry forming vias and trenches and other small features less than 0.2 microns with high aspect ratios. The copper bath contains a bath soluble organic divalent sulfur compound, and a bath soluble polyether compound such as a block copolymer of polyoxyethylene and polyoxypropylene, a polyoxyethylene or polyoxypropylene derivative of a polyhydric alcohol and a mixed polyoxyethylene and polyoxypropylene derivative of a polyhydric alcohol. A preferred polyether compound is a mixed polyoxyethylene and polyoxypropylene derivative of glycerine. A preferred copper bath also contains a pyridine compound derivative.

Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrodes which have a contact face which bears against the workpiece and conducts current therebetween. The contact face is provided with a contact face outer contacting surface which is made from a contact face material similar similar to the workpiece plating material which is to be plated onto the semiconductor workpiece. The contact face can be formed by pre-conditioned an electrode contact using a plating metal which is similar to the plating materials which is to be plated onto the semiconductor workpiece.

Abstract: The present invention pertains to methods and apparatus for electroplating a substantially uniform layer of a metal onto a work piece having a seed layer thereon. The total current of a plating cell is distributed among a plurality of anodes in the plating cell in order to tailor the current distribution in the plating electrolyte to compensate for resistance and voltage variation across a work piece due to the seed layer. Focusing elements are used to create “virtual anodes” in proximity to the plating surface of the work piece to further control the current distribution in the electrolyte during plating.

Abstract: The present invention provides inter alia electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention are characterized in significant part by a grain refiner/stabilizer additive comprising one or more non-aromatic compounds having &pgr; electrons that can be delocalized, e.g., an &agr;,&bgr; unsaturated system or other conjugated system that contains a proximate electron-withdrawing group. Compositions of the invention provide enhanced grain refinement and increased stability in metal plating solutions, particularly in tin and tin alloy plating formulations.

Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.

Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

Abstract: A method and apparatus for transmitting electrical signals and fluids to and/or from a microelectronic workpiece. An apparatus in accordance with one embodiment of the invention includes a shaft rotatable about a shaft axis and having a first end with a first electrical contact portion toward the first end, a second end opposite the first end, and an internal channel along the shaft axis between the first and second ends. The shaft can further have at least one first hole toward the first end with the first hole extending radially from the channel to an external surface of the shaft. The shaft can still further have at least one second hole toward the second end with the second hole extending from the channel to the external surface. A housing rotatably receives the shaft and has an aperture coupleable to a fluid source and/or fluid sink.

Abstract: A via filling method that provides superior filling properties and superior planarization of the deposited metal layer is provided. This is achieved by a method having a F/R ratio, the ratio of the electric current densities between the forward electrolysis and the reverse electrolysis, is in the range of 1/1 to 1/10 in a PPR electric current method applied with a cycle wherein the forward electrolysis interval is from 1 to 50 msec and the reverse electrolysis interval is from 0.2 to 5 msec.

Abstract: The invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects. A plating system is disclosed for plating conductive patterns formed at a first surface of a substrate. The system is such that exposure surfaces not to be plated is inhibited. A first electrode of the system is immersed in the plating solution while the second electrode is in contact with another than the first surface of the substrate. The conductive patterns to be plated are temporarily electrically connected with the second electrode.

Abstract: A method of plating for filling via holes, in which each via hole is formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate. A copper film is formed on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes. A strike plating of copper is provided on the copper film, and the substrate is immersed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper strike. The plating promoter is removed from the copper strike plating located on the top surface insulation layer while leaving the plating promoter on the side walls and bottoms of the respective via holes. The substrate is subsequently electroplated with copper to fill the via holes.

Abstract: An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.

Abstract: A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

Abstract: Electroplating methods and systems employing ultrasonic energy to enhance electroplating processes. The electroplating methods involve sweeping a plating surface with ultrasonic energy having an area of maximum ultrasonic energy density while simultaneously performing electroplating. The systems include movement apparatus providing relative movement between an ultrasonic energy source and a cathode while the ultrasonic energy source and the cathode are located within a plating tank.

Abstract: A method and apparatus for electrochemically depositing a metal onto a substrate. The apparatus generally includes a head assembly having a cathode and a wafer holder disposed above the cathode. The apparatus further includes a process kit disposed below the head assembly, the process kit including an electrolyte container configured to receive and maintain a fluid electrolyte therein, and an anode disposed in the electrolyte container. The apparatus further includes a power supply in electrical communication with the cathode and the anode, the power supply being configured to provide a varying amplitude electrical signal to the anode and cathode.