Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.

Abstract: A method of forming an electrically conductive structure on a substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed over the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration. A second current is applied to the substrate at a second bias and a second density for a second duration. The first current and the second current are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.

Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.

Abstract: A semiconductor workpiece holder for use in processing a semiconductor workpiece includes a workpiece support operatively mounted to support a workpiece in position for processing. A finger assembly is operatively mounted upon the workpiece support and includes a finger tip. The finger assembly is movable between an engaged position in which the finger tip is engaged against the workpiece, and a disengaged position in which the finger tip is moved away from the workpiece. Preferably, at least one electrode forms part of the finger assembly and includes an electrode contact for contacting a surface of said workpiece. At least one protective sheath covers at least some of the electrode contact. According to one aspect of the invention, a sheathed electrode having a sheathed electrode tip is positioned against a semiconductor workpiece surface in a manner engaging the workpiece surface with said sheathed electrode tip.

Abstract: A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required.

Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.

Abstract: Electroplating processes (e.g. conformable contact mask plating and electrochemical fabrication processes) that include in situ activation of a surface onto which a deposit will be made are described. At least one material to be deposited has an effective deposition voltage that is higher than an open circuit voltage, and wherein a deposition control parameter is capable of being set to such a value that a voltage can be controlled to a value between the effective deposition voltage and the open circuit voltage such that no significant deposition occurs but such that surface activation of at least a portion of the substrate can occur. After making electrical contact between an anode, that comprises the at least one material, and the substrate via a plating solution, applying a voltage or current to activate the surface without any significant deposition occurring, and thereafter without breaking the electrical contact, causing deposition to occur.

Abstract: The invention concerns a method for making an multilevel interconnection circuitry comprising conductor tracks and micro-vias. The method for producing at least one of the levels comprises the following steps: a) on a substrate including at its surface metallizable and/or potentially metallizable parts (102), forming a first insulating photosensitive resin layer (103) comprising a compound capable of inducing subsequent metallization; b) exposing and revealing the first layer (103) so as to selectively uncover the metallizable and/or potentially metallizable parts (102) of the substrate; c) forming, by metallization, metal conductor tracks (111) and micro-vias (110) at the surface of the first insulating photosensitive resin layer (113) and of the parts uncovered during step b), by providing a second photosensitive resin layer (105) forming a selective protection, the second photosensitive resin layer (105) being eliminated.

Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.

Abstract: The present invention provides a plating method and apparatus, which is capable of introducing plating solution into the fine channels and holes formed in a substrate without needing to add a surface active agent to the plating solution, and capable of forming a high-quality plating film having no defects or omissions. The plating method for performing electrolytic or electroless plating of an object using a plating solution comprises: conducting a plating operation after or while deaerating dissolved gas in the plating solution; and/or conducting a preprocessing operation using a preprocessing solution after or while deaerating dissolved gas in the preprocessing solution and subsequently conducting the plating operation.

Abstract: A method and apparatus for electrochemically plating on a production surface of a substrate are provided. The apparatus generally includes a plating cell having a plating solution reservoir configured to contain a volume of an electrochemical plating solution, and a substrate support member positioned above the plating solution reservoir, the substrate support member being configured to electrically engage a non-production side of a substrate secured thereto.

Abstract: The overflow of a brazing material (19) from a die pad (11) is prevented by forming a second plating film (14B) on the surface of the die pad (11). The second plating film (14B) is provided around the surface of the die pad 11 so as to enclose an area where a semiconductor element (13) is mounted. In a step of mounting the semiconductor element (13) on the die pad (11) with the brazing material (19), the brazing material (19) overflows from the first plating film (14A) when the semiconductor element (13) is mounted on the upper part of the molten brazing material. However, the second plating film (14B) functions as a blocking area by which the overflow of the brazing material is prevented. Therefore, a short circuit can be prevented from arising between the die pad (11) and the bonding pad (12) because of the brazing material that has spread.

Abstract: The present invention is directed to methods and compositions for depositing a noble metal alloy onto a microelectronic workpiece. In one particular aspect of the invention, a platinum metal alloy is electrochemically deposited on a surface of the workpiece from an acidic plating composition. The plated compositions when combined with high-k dielectric material are useful in capacitor structures.

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract: There is provided a copper-plating liquid free from an alkali metal and a cyanide which, when used in plating of a substrate having an outer seed layer and fine recesses of a high aspect ratio, can reinforce the thin portion of the seed layer and can embed copper completely into the depth of the fine recesses. The plating liquid contains divalent copper ions and a completing agent, and an optional pH adjusting agent.

Abstract: A method for forming a thin film and a method for fabricating a liquid crystal display device using the same are provided. The method provides a process that is simplified. Uniform thin film characteristics can be obtained. The method for forming a thin film includes the steps of forming a diffusion barrier film on a substrate, forming a metal seed layer on the diffusion barrier film, removing a metal oxide film formed on a surface of the metal seed layer using an electric plating method, and depositing metal on the metal seed layer in which the metal oxide film is removed.

Abstract: The present invention provides inter alias electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention are characterized in significant part by a grain refiner/stabilizer additive comprising one or more non-aromatic compounds having &pgr; electrons that can be delocalized, e.g., an &agr;,&bgr; unsaturated system or other conjugated system that contains a proximate electron-withdrawing group. Compositions of the invention provide enhanced grain refinement and increased stability in metal plating solutions, particularly in tin and tin alloy plating formulations.

Abstract: The method for making plastic packages of the present invention includes: forming an electroless Cu plating film on a resin substrate after removing a Cu foil; disposing a first plating resist pattern thereupon, passing electricity through the electroless Cu plating film, and disposing an electrolytic Cu plating film where the pattern is absent; disposing a second plating resist pattern to form a circuit pattern, and disposing a Ni and Au plating film; removing the plating resist pattern and etching away the Ni and Au plating film and the electroless Cu plating film not covered by the electrolytic Cu plating film; and disposing a solder resist film with openings to expose an external terminal connection pad and a semiconductor element connection pad. This method provides superior bonding properties with a solder resist, reduces undercutting during etching, allows use of high-density circuits, provides high reliability, and improves yield.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: A method for redistributing bond pad locations on an IC die incorporates steps of (a) depositing a dielectric layer over the IC die and opening vias through the dielectric layer to the bond pads; (b) depositing a thin seed layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the seed layer to provide redistribution lines from individual ones of the bond pads to new locations for the bond pads; and (c) increasing the thickness of the redistribution lines by electroplating a conductive material onto the seed layer material. In some cases multiple relocations are made in the distribution.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Abstract: A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Abstract: A micro-electronic bond degradation sensor includes a sensor substrate having sensor circuitry and a sensor stud and a power stud extending therefrom. The sensor circuitry includes a voltage-to-current amplifier having an input coupled to sensor stud and an output coupled to the power stud. The voltage-to-current amplifier is operable to convert a voltage signal occurring along the sensor stud to a current signal output along the power stud.

Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.

Abstract: An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by, baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.

Abstract: Embodiments of the invention provide a method for plating copper into features formed on a semiconductor substrate. The method includes positioning the substrate in a plating cell, wherein the plating cell includes a catholyte volume containing a catholyte solution, an anolyte volume containing an anolyte solution, an ionic membrane positioned to separate the anolyte volume from the catholyte volume, and an anode positioned in the anolyte volume. The method further includes applying a plating bias between the anode and the substrate, plating copper ions onto the substrate from the catholyte solution, and replenishing the copper ions plated onto the substrate from the catholyte solution with copper ions transported from the anolyte solution via the ionic membrane, wherein the catholyte solution has a copper concentration of greater than about 51 g/L.

Abstract: Disclosed are electrolytes for copper electroplating that provide enhanced fill of small features with less overplate. Also disclosed are methods of plating substrates, such as electronic devices, using such electrolytes.

Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermined area by mechanically polishing the other areas while the conductive material is being applied.

Abstract: In an electroplating apparatus for semiconductor wafers, the currents to each of a plurality of contact portions contacting the wafer edge are individually adjustable and/or a parameter indicative of the current flow in each contact portion may be determined. Moreover, for precise control of the currents, means are provided for monitoring the currents.

Abstract: A process and apparatus are provided for electroplating a film onto a substrate having a top side including a plating surface includes the following steps. Provide a plating tank with an electroplating bath. Provide an anode in the bath. Place a substrate having a plating surface to be electroplated into the electroplating bath connecting surfaces to be plated to a first cathode. Support a second cathode including a portion thereof with openings therethrough extending across the plating surface of the substrate and positioned between the substrate and the anode. Connect power to provide a negative voltage to the first cathode and provide a negative voltage to the second cathode, and provide a positive voltage to the anode.

Abstract: A method for depositing a metal conduction layer in a feature of a substrate is provided. The method includes forming the feature in the substrate, the feature having a width dimension of less than about a tenth of a micron. A barrier layer is deposited on the substrate, preferably using a self ionized plasma deposition process, where the barrier layer has a thickness of no more than about three hundred angstroms. A substantially continuous seed layer is deposited on the barrier layer, where the seed layer has a thickness of less than about three hundred angstroms. A conduction layer is deposited on the seed layer from an alkaline electroplating bath, where the electroplating bath contains an electroplating solution selected from the group consisting a pyrophosphate solution, an alkaline cyanide solution and an alkaline metal ion complexing solution. The process is adaptable to electroplating features on a substrate wherein the features have a width dimension of less than about one tenth of a micron.

Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrode assemblies which have a contact part which connects to a distal end of an electrode shaft and bears against the workpiece and conducts current therebetween. The contact part is preferably made from a corrosion resistant material, such as platinum. The electrode assembly also preferably includes a dielectric layer which covers the distal end of the electrode shaft and seals against the contact part to prevent plating liquid from corroding the joint between these parts.

Abstract: According to the invention, silicon nanoparticles are applied to a substrate using an electrochemical plating processes, analogous to metal plating. An electrolysis tank of an aqueous or non-aqueous solution, such as alcohol, ether, or other solvents in which the particles are dissolved operates at a current flow between the electrodes. In applying silicon nanoparticles to a silicon, metal, or non-conducting substrate, a selective area plating may be accomplished by defining areas of different conductivity on the substrate. Silicon nanoparticle composite platings and stacked alternating material platings are also possible. The addition of metal ions into the silicon nanoparticle solution produces a composite material plating. Either composite silicon nanoparticle platings or pure silicon nanoparticle platings may be stacked with each other or with convention metal platings.

Abstract: A process for via filling is provided, wherein after flash plating, a PPR current is applied for a cycle of 1 to 50 msec positive electrolysis time and 0.2 to 5 msec reverse electrolysis time until an F/R ratio representing the ratio of positive electrolysis current density to reverse electrolysis current density is at least 1/0.2 and less than 1/1.

Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a two-step process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.

Abstract: A mist trap mechanism and method for a plating apparatus, which can provide an improved mist removing effect by a simple structure, are provided. A gas discharge passage is formed to connect the space in a plating chamber and space outside of the plating chamber and provided with a liquid spouting portion and a solid wall. The discharge gas collides with the liquid spouted from the liquid spouting portion, and the discharge gas collides with the solid wall which has its surface wetted with the liquid spouted from the liquid spouting portion. Such a two-staged collision of the discharge gas effectively takes the mist contained in the discharge gas into the liquid. A liquid recovery portion is disposed in connection with the gas discharge passage to collectively catch the mist in a state captured by the liquid.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.

Abstract: In accordance with one embodiment of the invention, a process for applying a metal to a workpiece is set forth. The workpiece initially includes a seed layer deposited on at least a portion of a surface thereof that is generally unsuitable for bulk electrochemical deposition. The process starts with this workpiece and repairs the seed layer by depositing a metal using a first electrochemical deposition process to provide a repaired seed layer that is suitable for subsequent bulk electrochemical deposition. After the seed layer has been repaired, a bulk metal deposition over the repaired seed layer is executed by electrochemically depositing a bulk amount of a metal onto the repaired seed layer using a second electrochemical deposition process. The processing parameters of the second electrochemical deposition process are different from processing parameters used in the first electrochemical deposition process. A corresponding apparatus is also set forth.

Abstract: Semiconductor materials having a porous texture are modified with a recognition element and produce a photoluminescent response on exposure to electromagnetic radiation. The recognition elements, which can be selected from biomolecular, organic and inorganic moieties, interact with a target analyte to produce a modulated photoluminescent response, as compared with that of semiconductor materials modified with a recognition element only.

Abstract: A method for forming a low resistivity copper conductor line includes forming a silver material layer on silicon material, and forming a copper material layer on the silver material layer using an electroplating process.

Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

Abstract: The present invention provides plating solutions, particularly metal plating solutions, designed to provide uniform coatings on substrates and to provide substantially defect free filling of small features, e.g., micron scale features and smaller, formed on substrates with none or low supporting electrolyte, i.e., which include no acid, low acid, no base, or no conducting salts, and/or high metal ion, e.g., copper, concentration. Additionally, the plating solutions may contain small amounts of additives which enhance the plated film quality and performance by serving as brighteners, levelers, surfactants, grain refiners, stress reducers, etc.

Abstract: The object of the present invention is to provide a plating method capable of planarization process of high quality in comparison with the conventional plating method and also provide a plating device and a plating system adopting the plating method of the invention. In the plating method and device, an object 10 to be processed and an electrode plate 20 are dipped in a solution including objective metal ions and a forward current is supplied between the object and the electrode plate to educe a metal on the surface of the object. After forming a plating film on the object excessively, a backward current is supplied between the object 10 and the electrode 20 to uniformly remove at least part of superfluous plating film.

Abstract: Disclosed is an improved electrolyte formulation for the electrodeposition of copper onto electronic devices substrates and a process using the formulation. The formulation is a solution which contains copper alkanesulfonate salts and free alkanesulfonic acids and which is intended for the metallization of micron or sub-micron dimensioned trenches or vias.