Abstract: An electrochemical reaction assembly and methods of inducing electrochemical reactions, such as for deposition of materials on semiconductor substrates. The assembly and method achieve a highly uniform thickness and composition of deposition material or uniform etching or polishing on the semiconductor substrates by retaining the semiconductor substrates on a moving cathode immersed in an appropriate reaction solution wherein a wire mesh anode rotates about the moving cathode during electrochemical reaction.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer.

Abstract: Methods and apparatuses for in-situ cleaning of semiconductor electroplating electrodes to remove plating metal without requiring !the manual removal of the electrodes from the semiconductor plating equipment. The electrode is placed into the plating liquid and, an electrical current having reverse polarity is passed between the electrode and plating liquid. Plating deposits which have accumulated on the electrode are electrochemically dissolved and removed from the electrode.

Abstract: A capacitor having an electrode formed by electroplating, and a manufacturing method thereof are disclosed. According to an embodiment of the invention, a conductive film is formed on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film formed around the conductive plug. Then, a non-conductive pattern exposing a part of the conductive film on the conductive plug is formed on the conductive film, and a lower electrode, which is formed of a platinum (Pt) group metal, is formed on the conductive film by electroplating. In addition, the lower electrode can have a rectangular, T-shaped, reverse trapezoid or barrel-shaped cross-section. Electroplating can similarly form an upper electrode of the capacitor.

Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.

Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract: By using electron beam lithography, chemically assisted ion beam etching, and electroplating, high aspect ratio magnetic columns, 60 nm-170 nm in diameter, which are embedded in an aluminum-gallium-oxide/gallium-arsenide (Al0.9Ga0.1)203/GaAs heterostructured substrate, are fabricated. Storage of data in electroplated Ni columns is realized in the form of tracks 0.5 &mgr;m and 0.25 &mgr;m in the down-track direction, and 1 &mgr;m in the cross-track direction, corresponding to areal densities of 1.3 and 2.6 Gbits/in2 respectively. The fabrication of patterned media samples, using dry etching and oxidation of AlGaAs, and electrodeposition of Ni into GaAs substrate is realized.

Abstract: A method for depositing a coating of a nanostructure material onto a substrate includes: (1) forming a solution or suspension of containing the nanostructure material; (2) selectively adding “chargers” to the solution; (3) immersing electrodes in the solution, the substrate upon which the nanostructure material is to be deposited acting as one of the electrodes; (4) applying a direct and/or alternating current electrical field between the two electrodes for a certain period of time thereby causing the nanostructure materials in the solution to migrate toward and attach themselves to the substrate electrode; and (5) subsequent optional processing of the coated substrate.

Abstract: A process for selectively forming a metal barrier layer on a surface of an interconnect of a wiring substrate comprising the steps of abrading the substrate and simultaneously feeding onto the substrate a plating solution having said metal dissolved therein. The abrading step comprises contacting the substrate against an abrasive surface and causing relative linear and/or rotary motion between the abrasive surface and the substrate while the substrate is in contact with the abrasive surface. Growth of the metal barrier layer on a portion of the wiring substrate other than the interconnect layer is suppressed and the metal barrier layer thus formed is thinner, exhibits improved uniformity and superior prevention against Cu diffusion.

Abstract: A method for forming electroplating cathode contacts around the periphery of a semiconductor wafer including forming an insulating layer over a conductive layer extending at least around the periphery of a semiconductor wafer substrate; etching a plurality of openings around a peripheral portion of the semiconductor wafer substrate through the insulating layer to extend through a thickness of the insulating layer in closed communication with the conductive layer said conductive area in electrical communication with a central portion of the semiconductor wafer substrate; filling the plurality of openings with metal to form electrically conductive pathways; planarizing the electrically conductive pathway surfaces; and, forming a metal layer over the electrically conductive pathway surfaces to form a plurality of contact pads for contacting a cathode for carrying out an electroplating process.

Abstract: A process for metallization of a workpiece, such as a semiconductor workpiece. In an embodiment, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.

Abstract: A method and apparatus for fluid sealing the underside of a workpiece, such as a semiconductor wafer and the like, during wet-processing such as electrodeposition and the like, employing an elastomeric encased ring of flexible fingers against which the periphery of the workpiece underside is forced to deflect the fingers downwardly and engage a peripheral sealing bead against the underside periphery of the workpiece; and where electrical contact with the workpiece is desired, resiliently engaging electrical contact tips protruding through peripheral openings in the elastomeric covering within the sealing ring, with the underside periphery of the workpiece.

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion and causing greater plating of the cavity portion relative to the top portion.

Abstract: A layer of a metal is electroplated onto an electrically conducting substrate having a generally smooth surface with a small recess therein, having a transverse dimension not greater than about 350 micrometers, typically from about 5 micrometers to about 350 micrometers, by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses typically have a duty cycle less than about 50% and the anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of the pulses ranges from about 10 Hertz to about 12000 Hertz. The on-time of the cathodic pulses may range from about 0.83 microseconds to about 50 milliseconds.

Abstract: A method and apparatus for plating a substrate is provided, wherein fine pits formed in the substrate, such as fine channels for wiring, are filled with a copper, copper alloy, or other material with low electrical resistance. The method is performed on a wafer W having fine pits (10) to fill the fine pits with a metal (13) and includes performing a first plating process (11) by immersing the wafer in a first plating solution having a composition superior in throwing power; and performing a second plating process (12) by immersing the substrate in a second plating solution having a composition superior in leveling ability.

Abstract: A plating method comprising using a plating solution containing an additive satisfying the following conditions: 0.005×h2/w<D/&kgr;<0.5×h2/w, and 0.01≦&THgr;≦0.

Abstract: Disclosed are methods for analyzing additive breakdown products in electroplating baths as well as methods of controlling the presence of such breakdown products in electroplating baths.

Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Abstract: A system is provided in which a smaller flow of deposition solution is diverted from a larger flow of deposition solution flowing on an electrochemical deposition tool platform. The smaller flow is diverted to a dosing unit which may be on a separate platform. The dosing unit in one embodiment comprises a pressurized flow line.

Abstract: A method of plating which improves the uniformity of a plated coating thickness without changing the flow velocity of a feed plating solution. An aperture at a center of a mesh anode electrode of a plating apparatus produces an electric field density distribution between the mesh anode electrode and a wafer that is lower in the central portion of the wafer than at the edge portion of the wafer.

Abstract: An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.

Abstract: Embodiments of the present invention provide methods for enhancing void-free metallic filling of narrow openings by electrochemical deposition (ECD). The methods provide enhanced replenishment of plating inhibitor at the field, while depleting the inhibitor inside narrow openings. The resulting inhibitor gradients facilitate void-free ECD filling of narrow openings with large aspect ratios. The inventive methods utilize vigorous electrolyte agitation at the field and top comers of the openings, while maintaining a relatively stagnant electrolyte inside the openings. Vigorous agitation is produced, for example, by high pressure jets flow and/or by mechanical means, such as brush (or pad, or wiper blade) wiping, or by a combination of jets and wiping brushes.

Abstract: The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment.

Abstract: The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other.

Abstract: Methods and apparatus are provided for the preparation of a substrate having an array of diverse materials, the materials being deposited at spatially addressable, predefined regions. In particular, potential masking systems are provided which generate spatially and temporally varying electric, magnetic and chemical potentials across a substrate. These varying potentials are used to deposit components of source materials onto a substrate in a combinatorial fashion, thus creating arrays of materials that differ slightly in chemical composition, concentration, stoichiometry, and/or thickness. The diverse materials may be organized in discrete arrays, or they may vary continuously over the surface of the substrate. The shape of the potential allows the determination of the composition of the resulting materials at all locations on the substrate.

Abstract: The invention provides for a back-end metallisation process in which a recess is filled with copper and which includes the step of forming a plating base on the surfaces of the recess for the subsequent galvanic deposition of the said copper, and wherein subsequent to the formation of the plating base, but prior to the galvanic deposition of the copper, a modifying agent is introduced to the recess and which serves to absorb in the surface regions not covered by the plating base and to thereby modify the surface to promote copper growth thereon so as to effectively repair the initial plating base before the copper plating fill commences.

Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.

Abstract: In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

Abstract: Disclosed is a process flows for treating seed layers including copper such that various problems such as oxidation and insufficient coverage can be repaired in an effective and efficient manner.

Abstract: A system is provided in which a smaller flow of deposition solution is diverted from a larger flow of deposition solution flowing on an electro-chemical deposition tool platform. The smaller flow is diverted to a dosing unit which may be on a separate platform. The dosing unit in one embodiment comprises a pressurized flow line.

Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers, such as copper, onto a semiconductor workpiece. The workpiece holder includes electrodes which extend and are partially submerged in a liquid plating bath. The electrodes have a contact face which bears against the workpiece and conducts current therebetween. The submersible portions of the electrodes are partially covered with a dielectric layer or surface and partially covered with a conductive layer or surface. The conductive surface is preferably spaced from the contact face and placed in direct contact with the plating bath to allow diversion of some of the plating current directly between the electrode and plating bath. Associated methods are also described.

Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching an integrated circuit chip to a rigid or flexible dielectric substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the integrated circuit chip. The via holes are aligned and placed on top of the pads so that the pads are totally or partially exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the integrated circuit chip and the traces of the dielectric circuitry.

Abstract: The present invention provides methods for the use of copper electroplating compositions. Electroplating compositions of the invention contain an increased brightener concentration that can provide effective copper plate on difficult-to-plate aperture walls, including high aspect ratio, small diameter microvias.

Abstract: A method is provided of forming a semiconductor seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition with an organic additive at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition plates at a very low rate initially followed by a low rate deposition to build up a thicker and more uniform seed layer at the bottom and bottom sidewall. In the meantime, this slow plating rate step only adds a small thickness to the top portion of the feature where non-electrochemical deposition seed coverage was initially thicker.

Abstract: The present invention provides a composition and method for void-free plating of a metal into high aspect ratio features. The plating process is carried out in a plating solution containing metal at a molar concentration of between about 0.4 M and about 0.9 M, an acid at a concentration of between about 4 mg/L and about 40 mg/L, a suppressor at a concentration of between about 2 mL/L and about 15 mL/L, an accelerator at a concentration of between about 1.5 mL/L and about 8 mL/L, and a leveler at a concentration of between about 4 mL/L and about 11 mL/L.

Abstract: One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

Abstract: An electrochemical processing apparatus for processing a microelectronic workpiece includes a metrology unit and a control, signal-connected to the metrology unit. An electrochemical deposition unit provides a space to receive said microelectronic workpiece to deposit a subsequent film layer onto a prior layer, wherein a condition signal from the metrology unit influences the process control of the electrochemical deposition unit. The signal can also be used to transfer the microelectronic workpiece to a layer stripping unit, or a layer enhancement unit, or to a non-compliance station. The apparatus is particularly useful in measuring seed layer thickness and adjusting the operating control of a computational fluid dynamic reactor, which electroplates a process layer onto the seed layer.

Abstract: A method of electroplating both sides of a dual-sided circuit board substrate having electrically connected, multi-trace circuit patterns formed on both sides of the substrate, without requiring formation and at least partial removal of electrically conductive tie bars, comprises steps of covering and electrically contacting a first one of the circuit patterns with a first layer of electrically conductive material, applying an electrical potential to the first layer of electrically conductive material to effect electroplating on the second one of the circuit patterns, removing the first layer of electrically conductive material, covering and electrically contacting the second one of the circuit patterns with a second layer of electrically conductive material, applying an electrical potential to the second layer of electrically conductive material to effect electroplating on the first one of the circuit patterns, and removing the second layer of electrically conductive material.

Abstract: A method for making semiconductor interconnect features in a dielectric layer is provided. The method includes depositing a copper seed layer over a barrier layer that is formed over the dielectric layer and into etched features of the dielectric layer. The copper seed layer is then treated to remove an oxidized layer from over the copper seed layer. The method then moves to electroplating a copper fill layer over the treated copper seed layer. The copper fill layer is configured to fill the etched features of the dielectric layer.

Abstract: Disclosed are electroplating baths for enhancing copper seed layers and for subsequent metallization on the seed layers. Methods of enhancing copper seed layers and depositing metal on such seed layers are also disclosed.

Abstract: The present invention generally provides a method and an apparatus for forming a doped metal film on a conductive substrate. In one aspect of the invention, the deposition process comprises first depositing a phosphorus doped seed layer on a conductive substrate, and then depositing a conductive metal layer on the phosphorus doped seed layer to form a conductive film. In another aspect, the invention provides a method of processing a substrate including depositing a dielectric layer on a substrate, etching a feature into the substrate, depositing a conductive layer in the feature, depositing a phosphorus doped seed layer on the conductive barrier layer, and depositing a conductive metal layer on the phosphorus doped seed layer. In another aspect of the invention, an apparatus is provided that includes a phosphorus doped anode used for depositing a phosphorus doped metal film, such as a seed layer, in an electrochemical deposition process.

Abstract: Bumps are formed by means of uniform plating in which air can be easily discharged.

Abstract: In a process for manufacturing an electrode (1) on a substrate (2) using a conventional structuring process, an electrically conducting surface structure is created which has at least one tip (3) or edge (4). In the area of the tip (3) or edge (4), an electrode layer (5) is galvanized onto the substrate (2) and/or applied by electrostatic powder coating. Then, a surface area of the substrate (2), which surrounds the electrode layer (5) located on the tip (3) or edge (4), is converted into an insulating layer (8) by a chemical reaction. The electrode layer (5) can also be applied in a manner where, in the area of the tip (3) or edge (4), a chemical is released, which upon irradiation by electromagnetic and/or particle radiation, precipitates an electrically conducting material. This chemical is then impinged in the area of the tip (3) or edge (4) with optical radiation.

Abstract: Disclosed are methods for depositing a conductive layer on a substrate having a barrier layer and/or a dielectric layer. Such methods are particularly suitable for depositing an electroplated copper layer on a substrate having small apertures, and preferably very small apertures.

Abstract: The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion and causing greater plating of the cavity portion relative to the top portion.

Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.

Abstract: A method for making semiconductor interconnect features in a dielectric layer is provided. The method includes depositing a copper seed layer over a barrier layer that is formed over the dielectric layer and into etched features of the dielectric layer. The copper seed layer is then treated to remove an oxidized layer from over the copper seed layer. The method then moves to electroplating a copper fill layer over the treated copper seed layer. The copper fill layer is configured to fill the etched features of the dielectric layer.