Product Is Circuit Board Or Printed Circuit Patents (Class 205/125)
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Patent number: 6939447Abstract: A method of electro-plating comprises providing an anode current for a target, applying an electron beam to the surface of a target and passing electrolyte between said target and anode, thereby to deposit material on said target. An electron beam gun directs an electron beam onto web while anode provides a current thereby depositing material on the web.Type: GrantFiled: February 14, 2003Date of Patent: September 6, 2005Assignee: TDAO LimitedInventor: John Michael Lowe
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Patent number: 6935018Abstract: A method for forming a copper-Invar-copper (CIC) laminate having an intermetallic layer of negligible thickness, and a structure associated with the CIC laminate. Starting with a block of Invar, the method includes a cleaning step followed by an electroplating step. The cleaning step electrochemically cleans the block of Invar with an acid solution while applying a negative voltage bias to the block of Invar. The electroplating step electroplates copper on the block of Invar, resulting in the block of Invar being sandwiched between two layers of copper, such that an intermetallic layer of zero or negligible thickness is disposed between the block of Invar and each layer of copper. Each layer of copper has a uniform thickness. If the starting block of Invar contains a through hole, then the electroplating step will plate a ring of copper on the through hole wall.Type: GrantFiled: October 25, 2002Date of Patent: August 30, 2005Assignee: International Business Machines CorporationInventors: Raymond T. Galasco, Bonnie S. McClure, Craig W. Richards
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Patent number: 6905589Abstract: A method of making a circuitized substrate in which a commoning layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a printed circuit board or the like. The structure, including such a chip and circuit board is ideally suited for use within an information handling system.Type: GrantFiled: February 24, 2003Date of Patent: June 14, 2005Assignee: Endicott Interconnect Technologies, Inc.Inventors: Frank D. Egitto, Voya P. Markovich, Thomas R. Miller
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Patent number: 6902659Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermine area by mechanically polishing the other areas while the conductive material is being applied.Type: GrantFiled: September 9, 2002Date of Patent: June 7, 2005Assignee: ASM Nutool, Inc.Inventor: Homayoun Talieh
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Patent number: 6902660Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole in the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.Type: GrantFiled: August 30, 2002Date of Patent: June 7, 2005Assignee: Korea Advanced Institute of Science and TechnologyInventors: Hyuek Jae Lee, Jin Yu
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Patent number: 6899829Abstract: A conductive polymer colloidal composition that selectively forms a coating on a non-conductive surface. The conductive polymer colloidal composition is composed of a polymer and a sulfonate dopant. The conductive polymer colloidal composition may also contain conductive colloidal particles such as conductive carbon or metal salt particles, oxidants, stabilizers, and preservatives. The conductive polymer colloidal composition may be employed to selectively coat the non-conductive parts of printed wiring boards such that a uniform metal layer can be deposited on the conductive polymer coat. In addition to a uniform metal layer being formed over the conductive polymer, adhesion between the metal layer and the printed wiring board is improved.Type: GrantFiled: November 30, 2001Date of Patent: May 31, 2005Assignee: Shipley Company, L.L.C.Inventors: James G. Shelnut, Wade Sonnenberg, Patrick J. Houle
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Patent number: 6896784Abstract: A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated.Type: GrantFiled: June 15, 2004Date of Patent: May 24, 2005Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Todd M. Fowler, Ajay P. Giri, Anton Nenadic, Blessen Samuel, Keith Kwong Hon Wong
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Patent number: 6890413Abstract: A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated.Type: GrantFiled: December 11, 2002Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Todd M. Fowler, Ajay P. Giri, Anton Nenadic, Blessen Samuel, Keith Kwong Hon Wong
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Patent number: 6866764Abstract: An inexpensive process for depositing an electrically conductive material on selected surfaces of a dielectric substrate may be advantageously employed in the manufacture of printed wiring boards having high quality, high density, fine-line circuitry, thereby allowing miniaturization of electronic components and/or increased interconnect capacity. The process may also be used for providing conductive pathways between opposite sides of a dielectric substrate and in decorative metallization applications.Type: GrantFiled: February 21, 2002Date of Patent: March 15, 2005Assignee: Michigan Molecular InstituteInventors: David A. Dalman, Petar R. Dvornic
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Patent number: 6863793Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a twostep process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.Type: GrantFiled: April 3, 2001Date of Patent: March 8, 2005Assignee: Faraday Technology Marketing Group, LLCInventors: E. Jennings Taylor, Jenny J. Sun, Maria E. Inman
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Patent number: 6841189Abstract: The invention provides for a back-end metallisation process in which a recess is filled with copper and which includes the step of forming a plating base on the surfaces of the recess for the subsequent galvanic deposition of the said copper, and wherein subsequent to the formation of the plating base, but prior to the galvanic deposition of the copper, a modifying agent is introduced to the recess and which serves to absorb in the surface regions not covered by the plating base and to thereby modify the surface to promote copper growth thereon so as to effectively repair the initial plating base before the copper plating fill commences.Type: GrantFiled: April 1, 2002Date of Patent: January 11, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Eric Alexander Meulenkamp, Maria Jeanne Schroevers
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Patent number: 6835294Abstract: Electrolytic copper plating methods are provided, wherein copper is electrolytically deposited on a substrate, and the electrolytic copper plating solution supplied to the electrolytic copper plating is subjected to dummy electrolysis using an insoluble anode. The method described above can maintain and restore the electrolytic copper plating solution so as to maintain satisfactory appearance of plated copper, fineness of deposited copper film, and via-filling.Type: GrantFiled: June 7, 2002Date of Patent: December 28, 2004Assignee: Shipley Company, L.L.C.Inventors: Hideki Tsuchida, Masaru Kusaka, Shinjiro Hayashi
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Patent number: 6827833Abstract: The interior of cavities and through-holes in electrically conductive substrates having high-aspect ratios of 8:1 or greater can be electroplated with a uniform layer of metal on their interior surfaces by using a pulse reverse voltage waveform having a pulse train of long cathodic pulses followed by short anodic pulses even in the absence of conventional additives such as levelers and brighteners.Type: GrantFiled: October 15, 2001Date of Patent: December 7, 2004Assignee: Faraday Technology Marketing Group, LLCInventors: E. Jennings Taylor, Jenny J. Sun
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Publication number: 20040238370Abstract: A method of manufacturing a printed circuit board is disclosed. A seed layer is removed while etching of a circuit pattern is prevented. In a printed circuit board manufacturing process according to a semi-additive method, a seed layer is formed by electroless copper plating. Using a resist pattern, a circuit pattern is formed by electrolytic copper plating. After the formation of the circuit pattern, the exposed regions of seed layer are subjected to etching. According to the invention, an etching liquid at a temperature of about 15° C. or less is used. As a temperature of the etching liquid is lowered, a potential difference between the seed layer and the circuit pattern increases. Due to the increase in potential difference, the seed layer becomes more susceptible to being etched, while the circuit pattern becomes less susceptible to being etched.Type: ApplicationFiled: May 7, 2004Publication date: December 2, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ryoichi Watanabe, Tatsuji Yamada, Shogo Mizumoto, Fumio Kumokawa
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Publication number: 20040231995Abstract: It is an object of the present invention to provide a copper electroplating method for a printed circuit board having via-holes, which can reproducibly secure good plated film quality and via-hole filling capacity even when the board includes a resist or the like. The electroplating bath for electroplating of a printed circuit board, containing at least one compound selected from the group consisting of pyridinium, bipyridinium, phenanthrolinium, quinolinium and phenazinium salts in the form of onium with an N-alkyl, N-aralkyl, N-aryl, N-alkylene or N-aralkylene moiety.Type: ApplicationFiled: May 21, 2004Publication date: November 25, 2004Inventor: Kenji Murao
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Patent number: 6821404Abstract: A process for recovering copper from an alkaline etch bath from an etching process in which printed boards plated with copper are etched with the alkaline etch bath and then rinsed with water, copper being removed by extraction with an organic solution, from which it is re-extracted in an acid solution. Said acid solution is passed to an operation for recovering copper, e.g. by electrolysis, but before said copper recovery a flow is diverted, in which the copper content is adjusted to a value below the value of the acid solution for copper recovery and which is used for the plating of printed boards.Type: GrantFiled: October 2, 2001Date of Patent: November 23, 2004Assignee: Mercer Holdings Corp.Inventors: Robert Pacholik, Gunnar Lidmer
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Publication number: 20040226828Abstract: Provided are a method for manufacturing a mounting substrate and a method for manufacturing a circuit device, both of which include the step of electroplating a number of electrodes. The method for manufacturing a mounting substrateincludes the steps of: forming a plurality of electrodes to a mounting substrate, the plurality of electrodes being electrically connected to each other by use of plating wires; energizing the electrodes via the plating wires to coat the electrodes with plated films 19 by electroplating; and electrically separating the individual electrodes from each other by cutting off the plating wires. Furthermore, the method for manufacturing a circuit device includes, in addition to the foregoing method for manufacturing a mounting substrate, the steps of: fixing a circuit element on the mounting substrate and electrically connecting the electrodes with the circuit element; and forming a sealing resin so as to cover the circuit element.Type: ApplicationFiled: March 31, 2004Publication date: November 18, 2004Inventor: Kiyoshi Mita
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Patent number: 6818115Abstract: The present invention includes an electrolytic plating system with an elecrolytic plating bath, means for positioning the printed circuit boards in the bath, and means to alternately generate a laminar flow of electrolyte on each side of the printed circuit boards. A preferred means to alternately generate a laminar flow of electolyte comprises a floating shield with a venturi-shaped partition and an aligned partition below the printed circuit boards, and operating a plurality of eductors below the floating shield. The means to alternately generate a laminar flow of electolyte can further comprise a transport mechanism that moves the floating shield and its partitions from side to side relative to the eductors or a mechanism to move the eductors. The plating can be also be improved by using a vibrator and a spring-mounting system that prevents vibration energy being absorbed by fixed portions of the plating system.Type: GrantFiled: October 18, 2002Date of Patent: November 16, 2004Assignee: Viasystems Group, Inc.Inventors: Hein van Kempen, Daniel J. Weber
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Patent number: 6811675Abstract: This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.Type: GrantFiled: June 20, 2001Date of Patent: November 2, 2004Assignee: Semitool, Inc.Inventor: Linlin Chen
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Patent number: 6808641Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.Type: GrantFiled: January 17, 2001Date of Patent: October 26, 2004Assignee: Murata Manufacturing Co., LtdInventors: Yoshiyuki Tonami, Yoshihiro Koshido
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Patent number: 6804881Abstract: A method for manufacture of a multilayer board and the board formed by the novel method. The method comprises selective plating of metallic reinforcing members, solder mount pads, signal lines and interconnections sequentially. The resultant board is desirably free of glass fiber reinforcement.Type: GrantFiled: May 12, 2000Date of Patent: October 19, 2004Assignee: Shipley Company, L.L.C.Inventors: Charles R. Shipley, Robert L. Goldberg, James G. Shelnut
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Patent number: 6805915Abstract: An electroless copper plating solution using glyoxylic acid as a reducing agent, which is small in the reacting quantity of Cannizzaro reaction, does not largely cause precipitation of the salt accumulated in the electroless copper plating solution by the plating reaction and Cannizzaro reaction, and can be used stably over a long period of time. The electroless copper plating solution comprises copper ion, a complexing agent for copper ion, a reducing agent for copper ion and a pH adjusting agent, wherein the reducing agent for copper ion is glyoxylic acid or a salt thereof, the pH adjusting agent is potassium hydroxide and the electroless copper plating solution contains at least one member selected from metasilicic acid, metasilicic acid salt, germanium dioxide, germanic acid salt, phosphoric acid, phosphoric acid salt, vanadic acid, vanadic acid salt, stannic acid and stannic acid salt in an amount of 0.0001 mol/L or more.Type: GrantFiled: February 19, 2002Date of Patent: October 19, 2004Assignee: Hitachi, Ltd.Inventors: Takeyuki Itabashi, Hiroshi Kanemoto, Haruo Akahoshi, Eiji Takai, Naoki Nishimura, Tadashi Iida, Yoshinori Ueda
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Patent number: 6797145Abstract: An electrochemical processing method is provided for forming a current carrying device for semiconductor chip packaging and similar applications. The method comprises selecting sections of a substrate to carry current wherein a selected section is at least partly covered with a voltage switchable dielectric material, rendering the voltage switchable dielectric material conductive, and electrochemically forming a current carrying material directly on the voltage switchable dielectric material. The voltage switchable dielectric material can have a characteristic voltage, such that when a voltage having a magnitude exceeding the characteristic voltage is applied to the voltage switchable dielectric material, the voltage switchable dielectric material switches from a dielectric material to a conductive material. When conductive, the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating.Type: GrantFiled: December 9, 2002Date of Patent: September 28, 2004Inventor: Lex Kosowsky
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Patent number: 6782610Abstract: The present invention relates to a method for fabricating a wiring substrate by forming an insulating film on a metal base having openings on the metal base at positions corresponding to metal bumps to be formed later; forming at least one layer of wiring on the base made of a metal through the insulating film, the layer of wiring having a wring film formed thereon by electroplating; and selectively etching the base. The insulating film can be a liquid photosensitive polyamide, the wiring layer can be copper and the wiring film can be a conductive layer selected from the group consisting of Ni-P and Ni. In the present invention, the wiring layer can be formed through the insulating film in contact with the metal base at the openings in the insulating film and in contact with the insulating film where there are no openings in the insulating film.Type: GrantFiled: December 20, 1999Date of Patent: August 31, 2004Assignee: North CorporationInventors: Tomoo Iijima, Masayuki Oosawa, Shigeo Hirade
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Patent number: 6783654Abstract: A plating bath which accommodates an insoluble anode and a printed-circuit board, and a copper dissolved bath which supplies copper ions are arranged. The insoluble anode is arranged as opposed to the printed-circuit board being a cathode, and a forward/reverse current is applied between both of the electrodes. Iron ions are added to a plating solution.Type: GrantFiled: March 14, 2001Date of Patent: August 31, 2004Assignee: Kabushiki Kaisha Toyoda Jidoshokki SeisakushoInventors: Toshiki Inoue, Kyoko Kumagai
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Patent number: 6783652Abstract: A resin plate having wiring pattern recesses and via through holes is made. All of the surfaces of the resin plate including inner walls of the wiring pattern recesses and via through holes are coated with a metal film. An electro-plating is applied using the metal film as a power-supply layer to fill a plated metal into the wiring pattern recesses and via through holes. The metal film formed on the resin plate except for the inner walls of the wiring pattern recesses and via through holes is removed, so that wiring pattern and via are exposed on a surface the same as that of the resin plate.Type: GrantFiled: November 26, 2001Date of Patent: August 31, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takahiro Iijima, Akio Rokugawa, Yasuyoshi Horikawa
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Publication number: 20040163964Abstract: A method of making a circuitized substrate in which a commoning layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a printed circuit board or the like. The structure, including such a chip and circuit board is ideally suited for use within an information handling system.Type: ApplicationFiled: February 24, 2003Publication date: August 26, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: Frank D. Egitto, Voya P. Markovich, Thomas R. Miller
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Patent number: 6773568Abstract: The present invention provides inter alia electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention are characterized in significant part by a grain refiner/stabilizer additive comprising one or more non-aromatic compounds having &pgr; electrons that can be delocalized, e.g., an &agr;,&bgr; unsaturated system or other conjugated system that contains a proximate electron-withdrawing group. Compositions of the invention provide enhanced grain refinement and increased stability in metal plating solutions, particularly in tin and tin alloy plating formulations.Type: GrantFiled: July 16, 2003Date of Patent: August 10, 2004Assignee: Shipley Company, L.L.C.Inventors: Andre Egli, Anja Vinckier, Jochen Heber, Wan Zhang
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Patent number: 6767445Abstract: The present invention is a process for manufacturing resistors integral with the printed circuit board by plating the resistors onto the insulative substrate. The invention uses a mask during the activation step so as to selectively activate only selected portions of the surface thus enabling smaller areas to be plated on the printed circuit board because no plating mask is used. The process of the instant invention produced printed circuit boards having greater uniformity and reliability as compared to the prior art.Type: GrantFiled: October 16, 2002Date of Patent: July 27, 2004Inventors: Peter Kukanskis, Frank Durso, David Sawoska
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Patent number: 6761814Abstract: A via filling method that provides superior filling properties and superior planarization of the deposited metal layer is provided. This is achieved by a method having a F/R ratio, the ratio of the electric current densities between the forward electrolysis and the reverse electrolysis, is in the range of 1/1 to 1/10 in a PPR electric current method applied with a cycle wherein the forward electrolysis interval is from 1 to 50 msec and the reverse electrolysis interval is from 0.2 to 5 msec.Type: GrantFiled: December 20, 2002Date of Patent: July 13, 2004Assignee: Shipley Company, L.L.C.Inventors: Masaru Kusaka, Hideki Tsuchida
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Patent number: 6758958Abstract: The invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects. A plating system is disclosed for plating conductive patterns formed at a first surface of a substrate. The system is such that exposure surfaces not to be plated is inhibited. A first electrode of the system is immersed in the plating solution while the second electrode is in contact with another than the first surface of the substrate. The conductive patterns to be plated are temporarily electrically connected with the second electrode.Type: GrantFiled: April 16, 2001Date of Patent: July 6, 2004Assignees: Interuniversitair Micro-Elektronica Centrum, Siemens AktiengesellschaftInventors: Filip Van Steenkiste, Kris Baert, Walter Gumbrecht, Philippe Arquint
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Patent number: 6755957Abstract: A method of plating for filling via holes, in which each via hole is formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate. A copper film is formed on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes. A strike plating of copper is provided on the copper film, and the substrate is immersed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper strike. The plating promoter is removed from the copper strike plating located on the top surface insulation layer while leaving the plating promoter on the side walls and bottoms of the respective via holes. The substrate is subsequently electroplated with copper to fill the via holes.Type: GrantFiled: January 30, 2001Date of Patent: June 29, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kenji Nakamura, Masao Nakazawa
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Patent number: 6755954Abstract: An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.Type: GrantFiled: April 4, 2002Date of Patent: June 29, 2004Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Timothy Patrick Cleary, Michael John Janicki, Edmund B. Minshall, Thomas A. Ponnuswamy
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Publication number: 20040118692Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Linlin Chen, Jiong-Ping Lu, Changfeng Xia
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Patent number: 6749737Abstract: A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.Type: GrantFiled: August 10, 2001Date of Patent: June 15, 2004Assignee: Unimicron Taiwan Corp.Inventors: Jao-Chin Cheng, Chang-Chin Hsieh, Chih-Peng Fan, Chih-Hao Yeh
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Patent number: 6746590Abstract: Electroplating methods and systems employing ultrasonic energy to enhance electroplating processes. The electroplating methods involve sweeping a plating surface with ultrasonic energy having an area of maximum ultrasonic energy density while simultaneously performing electroplating. The systems include movement apparatus providing relative movement between an ultrasonic energy source and a cathode while the ultrasonic energy source and the cathode are located within a plating tank.Type: GrantFiled: September 5, 2001Date of Patent: June 8, 2004Assignee: 3m Innovative Properties CompanyInventors: Haiyan Zhang, Harlan L. Krinke
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Patent number: 6740352Abstract: Bonding pad(s) formed on a printed circuit board with circuit patterns. The bonding pad(s) include a plurality of copper patterns formed on the PCB and electrically connected to the circuit patterns, a filler filled between the copper patterns such that an upper surface of the copper pattern is exposed, and a plating layer applied at an upper surface of the copper patterns. An interval between wire bonding pad(s) is reduced by preventing a nickel plating layer and a gold plating layer from protruding at a lower portion of a copper pattern when they are formed on the copper patterns.Type: GrantFiled: November 12, 2002Date of Patent: May 25, 2004Assignee: LG Electronics Inc.Inventors: Sung-Gue Lee, Yong-Il Kim
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Patent number: 6740222Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.Type: GrantFiled: June 7, 2001Date of Patent: May 25, 2004Assignee: Agere Systems Inc.Inventor: Charles Cohn
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Publication number: 20040092136Abstract: A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polimid, partially-cured polyimid, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention.Type: ApplicationFiled: October 14, 2003Publication date: May 13, 2004Applicant: Micron Technology, Inc.Inventors: Warren M. Farnworth, Kevin G. Duesman
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Publication number: 20040084321Abstract: A method of applying a conductive carbon coating to a non-conductive surface and a printed wiring board having through holes or other nonconductive surfaces treated with such carbon coatings are disclosed. A conditioning agent is applied to the non-conductive surface to form a conditioned surface. A liquid dispersion of electrically conductive carbon (for example, graphite) having a mean particle size no greater than about 50 microns, combined with an organic binding agent, is coated on the conditioned surface to form an electrically conductive carbon coating. The conductive carbon coating is then optionally fixed on the (formerly) nonconductive surface and dried. The resulting coating has a low electrical resistance and is tenacious enough to be plated and exposed to molten solder without creating voids or losing adhesion, yet is easily removable from copper surfaces of the substrate by microetching.Type: ApplicationFiled: December 5, 2003Publication date: May 6, 2004Inventors: Charles Edwin Thorn, Frank Polakovic, Charles A. Mosolf
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Publication number: 20040079645Abstract: A method for manufacturing a personal digital assistant (PDA) that contains an upper housing and a lower housing, includes forming a first portion and a second portion of the upper housing through plastic injection molding at one time, and forming at least one positioning stud on an inner side of the upper housing through plastic injection molding. The first portion can be electroplated, the second portion cannot be electroplated, and the positioning stud contains a surface that can be electroplated. The method further includes electroplating the upper housing so as to form an electrically conductive layer on the first portion and the surface of the positioning stud.Type: ApplicationFiled: April 15, 2003Publication date: April 29, 2004Inventors: Chang-Huang Chiu, Chun-Shih Lee
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Publication number: 20040078970Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.Type: ApplicationFiled: August 22, 2003Publication date: April 29, 2004Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
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Publication number: 20040078968Abstract: Method for producing a printed circuit board on a substrate comprising five steps: (a) printing a predeterrnmined circuit pattern onto the substrate using a conductive material, (b) applying additional connection traces onto the substrate, (c) depositing a metal onto the printed circuit pattern by electroplating or electroforming a metal onto the substrate, (d) applying an adhesion and insulation glue layer over portions of the metal that comprises the desired circuit pattern, and (e) removing any undesired connection traces from the substrate.Type: ApplicationFiled: October 22, 2002Publication date: April 29, 2004Inventor: Sul Kay Wong
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Patent number: 6723219Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.Type: GrantFiled: August 27, 2001Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventor: Dale W. Collins
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Publication number: 20040069649Abstract: A flexible printed board production method which ensures higher adhesion of copper, excellent workability, easier continuous production and lower costs. The flexible printed board production method comprises the steps of: treating a surface of a polyimide resin film with plasma or short wavelength ultraviolet radiation; activating the treated surface with the use of an alkali metal hydroxide; electrolessly plating the surface of the polyimide resin film with nickel; and electroplating the electrolessly plated surface of the polyimide resin film with copper, whereby a copper layer is formed on the surface of the polyimide resin film.Type: ApplicationFiled: August 12, 2003Publication date: April 15, 2004Inventors: Naoki Katayama, Yasuhiro Hayashi, Joonhaneng Kang
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Publication number: 20040067447Abstract: The invention concerns a method for making an multilevel interconnection circuitry comprising conductor tracks and micro-vias. The method for producing at least one of the levels comprises the following steps: a) on a substrate including at its surface metallizable and/or potentially metallizable parts (102), forming a first insulating photosensitive resin layer (103) comprising a compound capable of inducing subsequent metallization; b) exposing and revealing the first layer (103) so as to selectively uncover the metallizable and/or potentially metallizable parts (102) of the substrate; c) forming, by metallization, metal conductor tracks (111) and micro-vias (110) at the surface of the first insulating photosensitive resin layer (113) and of the parts uncovered during step b), by providing a second photosensitive resin layer (105) forming a selective protection, the second photosensitive resin layer (105) being eliminated.Type: ApplicationFiled: November 14, 2003Publication date: April 8, 2004Inventors: Robert Cassat, Vincent Lorentz
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Publication number: 20040050708Abstract: A plating method for a printed circuit board includes: a first step of providing a substrate having a plurality of connection pads and circuit patterns connected to the connection pads; a second step of using some of the circuit patterns provided on a surface of the substrate as a power connection portion and connecting the power connection portion to an external power source; a third step of covering a surface of the substrate excepting the connection pads with a plating resistance resist to shield it; a fourth step of supplying power to the connection pad through the power connection portion and forming a gold-plated layer on the connection pad; and a fifth step of making the power connection portion and the external power source to be electrically short. With this method, a printed circuit board without a power supply line for gold-plating can be obtained.Type: ApplicationFiled: August 20, 2003Publication date: March 18, 2004Applicant: LG ELECTRONICS INC.Inventors: Yu-Seock Yang, Sung-Gue Lee, Yong-Soon Jang, Hyung-Kun Kim
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Patent number: 6706418Abstract: The present invention provides inter alias electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention are characterized in significant part by a grain refiner/stabilizer additive comprising one or more non-aromatic compounds having &pgr; electrons that can be delocalized, e.g., an &agr;,&bgr; unsaturated system or other conjugated system that contains a proximate electron-withdrawing group. Compositions of the invention provide enhanced grain refinement and increased stability in metal plating solutions, particularly in tin and tin alloy plating formulations.Type: GrantFiled: June 29, 2001Date of Patent: March 16, 2004Assignee: Shipley Company L.L.C.Inventors: Andre Egli, Anja Vinckier, Jochen Heber, Wan Zhang
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Publication number: 20040035711Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole to the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.Type: ApplicationFiled: August 30, 2002Publication date: February 26, 2004Inventors: Hyuek Jae Lee, Jin Yu
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Publication number: 20040023057Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.Type: ApplicationFiled: July 11, 2003Publication date: February 5, 2004Applicant: TDK CORPORATIONInventor: Akifumi Kamijima