Forming Nonelectrolytic Coating Before Depositing Predominantly Single Metal Or Alloy Electrolytic Coating Patents (Class 205/183)
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Patent number: 7049007Abstract: A peelable composite foil includes a metallic carrier foil, a first barrier layer on one side of the metallic carrier and a second metallic layer on the first barrier layer. The second metallic layer includes a combination of a metal selected from the group including zinc, molybdenum, antimony and tungsten, and an electrodeposited, ultra-thin metal foil on the second metallic layer.Type: GrantFiled: July 10, 2002Date of Patent: May 23, 2006Assignee: Circuit Foil Luxembourg SarlInventors: Raymond Gales, Michel Streel, Rene Lanners
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Patent number: 7005192Abstract: A ceramic electronic component having a ceramic member into which no plating intrudes, and a method of producing the ceramic electronic component by which the ceramic electronic component can be easily produced are provided. The ceramic electronic component contains a ceramic member, and terminal electrodes formed on both of end-faces of the ceramic member. Each terminal electrode comprises an external electrode, and a plating coat formed thereon. To produce the ceramic electronic component, the ceramic member having the external electrodes are dipped into a water-repelling agent, dried, and plated. The water-repelling agent contains a functional group which is readily adsorbed to the external electrodes and a hydrophobic functional group.Type: GrantFiled: March 26, 2002Date of Patent: February 28, 2006Assignee: Murata Manufacturing Co., Ltd.Inventors: Yukio Sanada, Yoshinori Saito
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Patent number: 6997787Abstract: A cutting tool having a hard tip is pressed with a uniform pressure against a surface of a vehicle wheel as the wheel is rotated to smooth and seal the surface. The smoothed and sealed wheel surface is then chrome plated with a process that includes applying a nickel layer directly upon smoothed and sealed wheel surface and a chromium layer over the nickel layer.Type: GrantFiled: November 22, 2004Date of Patent: February 14, 2006Assignee: Hayes Lemmerz International, Inc.Inventors: Geoffrey L. Gatton, Lou Grenier, Peter Yee
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Patent number: 6972082Abstract: A method for the continuous selective electroplating of a metallic substrate material (10) and more particularly of a substrate material band having prestamped contact elements, comprises the following steps: a) the substrate material (10) is coated in an electrophoretic coating means (14) with an electrophoretic coating composition selective with at least one composition strip, b) the at least one composition strip is removed at those parts by means of a laser (40), which are to be electroplated, c) in an electroplating process a metal layer is applied to the areas (42) deprived of composition in at least one composition strip using selective electroplating and d) the at least one composition strip is then removed.Type: GrantFiled: June 20, 2002Date of Patent: December 6, 2005Assignee: IMO Ingo Müller e.K.Inventor: Michail Kotsias
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Patent number: 6872295Abstract: The present invention is related to a method for the preparation of a composition for electroplating a copper-containing layer on a substrate. This method makes use of an aqueous solution that has at least: a source of copper Cu(II) ions, an additive to adjust the pH to a predetermined value, and a complexing agent for complexing Cu(II) ions. The complexing agent has the chemical formula: COOR1—COHR2R3 in which R1 is an organic group covalently bound to the carboxylate group (COO), R2 is either hydrogen or an organic group, and R3 is either hydrogen or an organic group. The solution has no reducing agent. The method involves providing electrons from a source not in direct contact with the solution, through transport means that provides the contact between said source and said solution. The present invention is also related to a process for forming a copper-containing layer on a substrate in an electroplating bath prepared according to the foregoing method.Type: GrantFiled: December 12, 2001Date of Patent: March 29, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Roger Palmans, Yuri Lantasov
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Patent number: 6866764Abstract: An inexpensive process for depositing an electrically conductive material on selected surfaces of a dielectric substrate may be advantageously employed in the manufacture of printed wiring boards having high quality, high density, fine-line circuitry, thereby allowing miniaturization of electronic components and/or increased interconnect capacity. The process may also be used for providing conductive pathways between opposite sides of a dielectric substrate and in decorative metallization applications.Type: GrantFiled: February 21, 2002Date of Patent: March 15, 2005Assignee: Michigan Molecular InstituteInventors: David A. Dalman, Petar R. Dvornic
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Patent number: 6855376Abstract: Carbon nanotubes are directly grown on a substrate surface having three metal layers thereon by a thermal chemical vapor deposition at low-temperature, which can be used as an electron emission source for field emission displays. The three layers include a layer of an active metal catalyst sandwiched between a thick metal support layer formed on the substrate and a bonding metal layer. The active metal catalyst is iron, cobalt, nickel or an alloy thereof; the metal support and the bonding metal independently are Au, Ag, Cu, Pd, Pt or an alloy thereof; and they can be formed by sputtering, chemical vapor deposition, physical vapor deposition, screen printing or electroplating.Type: GrantFiled: September 10, 2002Date of Patent: February 15, 2005Assignee: Industrial Technology Research InstituteInventors: Chien-Liang Hwang, Jack Ting, Jih-Shun Chiang, Chuan Chuang
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Patent number: 6824666Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer.Type: GrantFiled: January 28, 2002Date of Patent: November 30, 2004Assignee: Applied Materials, Inc.Inventors: Srinivas Gandikota, Chris R. McGuirk, Deenesh Padhi, Muhammad Atif Malik, Sivakami Ramanathan, Girish A. Dixit, Robin Cheung
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Publication number: 20040231998Abstract: The process of this invention involves first adsorbing a catalyst on the surface of a specimen by immersion in a catalyst-containing solution, followed by electrolytic deposition in a second solution that need not contain catalyst. This two-step superconformal process produces a seam-free and void-free metal microelectronic conductor.Type: ApplicationFiled: May 23, 2003Publication date: November 25, 2004Inventors: Daniel Josell, Thomas P. Moffat, Daniel Wheeler
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Publication number: 20040213895Abstract: A method of manufacturing an embedded multilevel interconnection, comprising the steps of: forming a hole portion in an insulating layer; forming a barrier metal film mainly made of tantalum and nitrogen in such a manner that the barrier metal film covers at least an inner wall of the hole portion, an element composition ratio (N/Ta) of nitrogen to tantalum contained in the barrier metal film being 0.3 or higher but 1.5 or lower; removing an oxide film formed on a surface of the barrier metal film; and immersing the barrier metal film in a plating liquid comprising copper and thereby forming an electroless copper plating film on the barrier metal film.Type: ApplicationFiled: March 26, 2004Publication date: October 28, 2004Applicant: Semiconductor Technology Academic Research CenterInventors: Shoso Shingubara, Takayuki Takahagi, Zenglin Wang
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Patent number: 6808813Abstract: A ceramic electronic device is protected at the surface from retention of water, thus having improved operation reliability, and a method of manufacturing the device is provided. A protective layer is formed on the ceramic element and external electrodes by dehydrating condensation of organic silicon compound.Type: GrantFiled: January 11, 2002Date of Patent: October 26, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kimura, Emiko Igaki, Hiroshi Ito, Osamu Yamashita, Masakazu Tanahashi
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Publication number: 20040206629Abstract: A method for the continuous selective electroplating of a metallic substrate material (10) and more particularly of a substrate material band having prestamped contact elements, comprises the following steps:Type: ApplicationFiled: January 20, 2004Publication date: October 21, 2004Inventor: Michail Kotsias
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Publication number: 20040202776Abstract: A process for forming an interface (106) between a plated and a non-plated area (102, 104) on the surface of a plastic component (100) is disclosed. First, an anti-plating layer (110) is formed over the surface of the plastic component. Thereafter, a low-power laser beam (10) is used to remove a portion of the anti-plating layer and to form an interface between the plated area and the non-plated area. A seeding layer (120) is formed on the plated area so that the plated area is electrically conductive. Finally, a metallic layer (130) is electrically plated over the seeding layer. The metallic layer connects with the anti-plating layer via the interface. The cost of producing the anti-plating layer is low. Moreover, since the laser etching operation is able to produce a high-quality interface boundary between the plated and the non-plated area, yield of the process is improved.Type: ApplicationFiled: June 9, 2003Publication date: October 14, 2004Inventors: Che-Hung Huang, Steven Hsu
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Patent number: 6802985Abstract: There is provided a method for fabricating electrical wirings capable of being manufactured with low cost and easily applied to large-scale substrates. A photosensitive ground resin film is formed on an insulating substrate by coating process. The ground resin film is subjected to exposure and development processes, by which a ground resin film patterned into a wiring pattern is obtained. Then, on the patterned ground resin film, a low-resistance metal film made of Cu is formed by electroless plating.Type: GrantFiled: August 25, 2000Date of Patent: October 12, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshimasa Chikama, Yoshihiro Izumi
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Patent number: 6773572Abstract: A method of metal layer formation which can satisfactorily eliminate the problems caused by plating solution infiltration and is sufficiently effective in reducing the permittivity of an insulating layer; and a metal foil-based layered product obtainable by the method. The method is for forming a metal layer on a surface of a porous resin layer and includes: a step in which a porous resin layer having a dense layer as a surface part thereof is used as the porous resin layer and a thin metal film is formed on the surface of the dense layer by a dry process; and a step in which a metal film is formed on the surface of the thin metal film by plating.Type: GrantFiled: December 30, 2002Date of Patent: August 10, 2004Assignee: Nitto Denko CorporationInventors: Toshiyuki Kawashima, Nobuharu Tahara, Kenichi Ikeda
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Multi-cell masks and methods and apparatus for using such masks to form three-dimensional structures
Publication number: 20040129573Abstract: Multilayer structures are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. Selectivity of deposition is obtained via a multi-cell controllable mask. Alternatively, net selective deposition is obtained via a blanket deposition and a selective removal of material via a multi-cell mask. Individual cells of the mask may contain electrodes comprising depositable material or electrodes capable of receiving etched material from a substrate. Alternatively, individual cells may include passages that allow or inhibit ion flow between a substrate and an external electrode and that include electrodes or other control elements that can be used to selectively allow or inhibit ion flow and thus inhibit significant deposition or etching. Single cell masks having a cell size that is smaller or equal to the desired deposition resolution may also be used to form structures.Type: ApplicationFiled: October 1, 2003Publication date: July 8, 2004Applicant: University of Southern CaliforniaInventor: Adam L. Cohen -
Patent number: 6755958Abstract: A cooper or copper alloy electrical contact member is treated by electroplating a barrier layer on a contact surface of the member, the barrier layer having a thickness ranging from about 0.00001 inch to about 0.0001 inch, and the barrier layer is selected from the group consisting of cobalt, cobalt-nickel alloys, cobalt-tungsten alloys, cobalt-nickel-tungsten alloys, and rhodium. An outer finish layer is coated over the barrier layer, and the finish layer is selected from the group consisting of tin, gold, palladium, platinum, silver, and alloys thereof, so that the electrical contact resistance of the treated contact member does not exceed about 10 milliohms at 100 grams contact force over a period of at least 1000 hours, and at a temperature of at least 150 degrees C.Type: GrantFiled: December 11, 2001Date of Patent: June 29, 2004Assignee: Handy & HarmanInventor: Amit Datta
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Patent number: 6755957Abstract: A method of plating for filling via holes, in which each via hole is formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate. A copper film is formed on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes. A strike plating of copper is provided on the copper film, and the substrate is immersed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper strike. The plating promoter is removed from the copper strike plating located on the top surface insulation layer while leaving the plating promoter on the side walls and bottoms of the respective via holes. The substrate is subsequently electroplated with copper to fill the via holes.Type: GrantFiled: January 30, 2001Date of Patent: June 29, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kenji Nakamura, Masao Nakazawa
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Patent number: 6740222Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.Type: GrantFiled: June 7, 2001Date of Patent: May 25, 2004Assignee: Agere Systems Inc.Inventor: Charles Cohn
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Publication number: 20040084321Abstract: A method of applying a conductive carbon coating to a non-conductive surface and a printed wiring board having through holes or other nonconductive surfaces treated with such carbon coatings are disclosed. A conditioning agent is applied to the non-conductive surface to form a conditioned surface. A liquid dispersion of electrically conductive carbon (for example, graphite) having a mean particle size no greater than about 50 microns, combined with an organic binding agent, is coated on the conditioned surface to form an electrically conductive carbon coating. The conductive carbon coating is then optionally fixed on the (formerly) nonconductive surface and dried. The resulting coating has a low electrical resistance and is tenacious enough to be plated and exposed to molten solder without creating voids or losing adhesion, yet is easily removable from copper surfaces of the substrate by microetching.Type: ApplicationFiled: December 5, 2003Publication date: May 6, 2004Inventors: Charles Edwin Thorn, Frank Polakovic, Charles A. Mosolf
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Publication number: 20040076707Abstract: In a die for molding a honeycomb structure, in which a coating layer is formed on a die base so that slits with a particular width are provided, the slits are provided so as to have a width of 30 to 200 &mgr;m by forming the coating layer by a substrate layer with a thickness of 10 to 100 &mgr;m and a surface layer with a thickness of 1 to 30 &mgr;m. Further, the substrate layer is formed by a metal layer containing no oxide.Type: ApplicationFiled: July 3, 2003Publication date: April 22, 2004Inventors: Keiji Matsumoto, Haremi Ito, Shinji Murahata
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Publication number: 20040065555Abstract: Electroplating processes (e.g. conformable contact mask plating and electrochemical fabrication processes) that include in situ activation of a surface onto which a deposit will be made are described. At least one material to be deposited has an effective deposition voltage that is higher than an open circuit voltage, and wherein a deposition control parameter is capable of being set to such a value that a voltage can be controlled to a value between the effective deposition voltage and the open circuit voltage such that no significant deposition occurs but such that surface activation of at least a portion of the substrate can occur. After making electrical contact between an anode, that comprises the at least one material, and the substrate via a plating solution, applying a voltage or current to activate the surface without any significant deposition occurring, and thereafter without breaking the electrical contact, causing deposition to occur.Type: ApplicationFiled: May 7, 2003Publication date: April 8, 2004Applicant: University of Southern CaliforniaInventor: Gang Zhang
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Publication number: 20040058088Abstract: Disclosed is a processing method for forming a thick film having an improved adhesion to a surface-modified substrate and an apparatus thereof enabling to form a thick film having the improved adhesion to a polymeric surface by modifying the polymeric surface to have a hydrophilic property. The method includes the steps of preparing a substrate of a polymer material, surface-modifying the substrate, forming a seed layer on the substrate, and forming the thick film on the seed layer. The apparatus includes an unloading area supplying a substrate of a polymer material, a surface treating area modifying a surface of the substrate, a seed layer formation area forming a seed layer on the surface-modified substrate, a thick film formation area forming a thick film on the seed layer, and a loading area loading the substrate.Type: ApplicationFiled: September 2, 2003Publication date: March 25, 2004Inventors: Young-Whoan Beag, Sung Han, Jun-Sik Cho, Cheol-Su Lee, Sung-Soo Koh, Jin-Woo Seok
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Publication number: 20040045833Abstract: This specification discloses a thin-film gas diffusion electrode (GDE) and the method for making the same. The thin-film GDE is formed in a unitary way. A dual-nature porous thin film is used as the substrate. A surface processing is performed to make one surface of the thing film hydrophlic while the other surface hydrophobic. The hydrophlic area serves as the active layer for electrochemical reactions after chemical processing. The hydrophobic area is kept dry to form a smooth gas channel, functioning as a gas diffusion layer. In this method, the thin-film GDE is free from the use of binders and high-temperature high-pressure manufacturing processes.Type: ApplicationFiled: April 21, 2003Publication date: March 11, 2004Inventors: Wen-Chin Li, Shu-Chin Chou, Shinn-Horng Yeh, Kuan-Liang Chen, Kun-Lung Hsien, Min-Lun Chen
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Publication number: 20040040855Abstract: A method for redistributing bond pad locations on an IC die incorporates steps of (a) depositing a dielectric layer over the IC die and opening vias through the dielectric layer to the bond pads; (b) depositing a thin seed layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the seed layer to provide redistribution lines from individual ones of the bond pads to new locations for the bond pads; and (c) increasing the thickness of the redistribution lines by electroplating a conductive material onto the seed layer material. In some cases multiple relocations are made in the distribution.Type: ApplicationFiled: August 28, 2002Publication date: March 4, 2004Inventor: Victor Batinovich
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Publication number: 20040040857Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.Type: ApplicationFiled: May 31, 2003Publication date: March 4, 2004Applicant: Semitool, Inc.Inventors: Lin Lin Chen, Thomas Taylor
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Publication number: 20040035708Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.Type: ApplicationFiled: April 17, 2003Publication date: February 26, 2004Applicant: Semitool, Inc.Inventors: Linlin Chen, Thomas Taylor
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Publication number: 20040035709Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.Type: ApplicationFiled: April 29, 2003Publication date: February 26, 2004Inventor: Cyprian Uzoh
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Publication number: 20040035710Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.Type: ApplicationFiled: May 28, 2003Publication date: February 26, 2004Applicant: Semitool, Inc.Inventors: Linlin Chen, Thomas Taylor
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Method of producing transfer stickers with metal powder and transfer stickers produced by the method
Publication number: 20040035713Abstract: A method of producing transfer stickers with metal powder has the steps of: coating a substrate with a first isolating layer; coating the first isolating layer with a resin layer; coating the resin layer with a metal powder layer by an electroplating process; printing a first protecting resin layer pattern on the metal powder layer; etching the metal powder layer for shape and to cause the patterns to protrude; washing away the etching reagents; printing a second protecting resin layer on the first protecting resin layer to protect the patterns in shape; printing an adhesive layer on the second protecting resin layer; and then attaching a second isolating layer to the adhesive layer. The transfer sticker made in accordance with this method has exquisite patterns that can be transferred completely without other residual parts of the sticker.Type: ApplicationFiled: August 27, 2003Publication date: February 26, 2004Inventor: Teng-Kuei Chen -
Publication number: 20040026258Abstract: Disclosed is a method for forming a high reflective micropattern, comprising forming a micropattern using an organometallic compound in a photoreaction or with thermal energy; and growing crystal, using the pattern as the nucleus for growing crystal, by an electro or electroless plating process. The method forms a high reflective metal pattern rapidly and efficiently without using conventional chemical vapor deposition or physical deposition methods such as sputtering.Type: ApplicationFiled: June 26, 2003Publication date: February 12, 2004Inventors: Chang Ho No, Soon Taik Hwang, Young Hun Byun, Byong Ki Yun, Jin Young Kim
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Publication number: 20040013812Abstract: The invention relates to the production of composite cathodes, which comprise, for example, at least one lithium-containing spinel, composite anodes for lithium batteries, and the cathodes and anodes thereby produced. The active mass in the form of a thin film is incorporated into a material, or the active mass together with a matrix metal or a matrix alloy is deposited on a substrate. The invention also relates to a metallised, textile material made of insulating fibres which have been made conductive and which have been completely galvanically or electrolessly plated. The fibres lying on crossovers are not baked with other fibres, but can move freely. The surface of the material is thereby optimally used. Said material is preferably used as an anode or a cathode for batteries, especially a lithium battery, and fuel cells.Type: ApplicationFiled: August 4, 2003Publication date: January 22, 2004Inventors: Wolfgang Kollmann, Helga Kollmann
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Patent number: 6680092Abstract: The invention concerns a method for producing high resolution patterns on a support comprising the following steps: high resolution printing of a varnish on the support; treating the support by electrolysis; washing and drying the support.Type: GrantFiled: May 10, 2002Date of Patent: January 20, 2004Assignee: Cabinet Erman S.A.R.L.Inventor: Michel Levy
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Patent number: 6660154Abstract: Disclosed are methods for repairing or enhancing discontinuous metal seed layers prior to subsequent metallization during the manufacture of electronic devices. Such repair methods do not require the use of a second electroplating bath.Type: GrantFiled: October 17, 2001Date of Patent: December 9, 2003Assignee: Shipley Company, L.L.C.Inventors: David Merricks, Denis Morrissey, Martin W. Bayes, Mark Lefebvre, James G. Shelnut, Donald E. Storjohann
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Publication number: 20030224253Abstract: A process of fabricating a non-gap 3-D microstructure array mold core comprises a first step in which a buffer layer is coated on a substrate. A photomask layer is then coated of the buffer layer. A pattern is subsequently formed on the photomask by photo-lithography. The patterned photomask layer is subjected to a reflow by which a microstructure array is formed on the photomask layer. The microstructure array is coated with a metal conductive layer. The microgaps of the microstructure array are eliminated by an electrocasting layer which is coated on the microstructure array. The non-gap microstructure array mold core so fabricated is made into a metal molding tool by microinjection molding or microthermo-pressure molding.Type: ApplicationFiled: June 1, 2002Publication date: December 4, 2003Inventors: Kun-Lung Lin, Min-Chieh Chou, Cheng-Tang Pan
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Publication number: 20030196905Abstract: The invention relates to a metal membrane filter (1) and to a method and apparatus for the production thereof. The metal membrane filter (1) has rectilinear, cylindrical filter pores (2), which are arranged statistically distributed on the metal membrane filter surface (3) in a density of from a single filter pore (2) per cm2 up to 107 filter pores (2) per cm2. The average diameter of the filter pores (2) is uniform for all filter pores (2) and is from a few tens of nm up to several micrometres. The metal membrane filter (1) comprises a metal electro-deposited with rectilinear, cylindrical filter pores (2) or a correspondingly electro-deposited metal alloy.Type: ApplicationFiled: December 30, 2002Publication date: October 23, 2003Inventors: Dobri Dobrev, Johann Vetter, Reinhard Neumann, Norbert Angert
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Patent number: 6613603Abstract: A photovoltaic device is provided which comprises a back reflection layer, a zinc oxide layer and a semiconductor layer stacked in this order on a substrate, wherein the zinc oxide layer contains a carbohydrate. The content of the carbohydrate is preferably in the range of from 1 &mgr;g/cm3 to 100 mg/cm3. Thereby, the zinc oxide layer can be formed without abnormal growth to have a rough surface to achieve sufficient optical confinement effect, and the photovoltaic device is improved in the durability and the photoelectric conversion efficiency.Type: GrantFiled: July 21, 1998Date of Patent: September 2, 2003Assignee: Canon Kabushiki KaishaInventor: Masafumi Sano
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Publication number: 20030102225Abstract: The conductive fabric is fabricated by preparing a base fibrous fabric substrate having the form of a woven, non-woven, or mesh sheet, forming a first layer formed on the fibrous fabric substrate in accordance with an electroless plating process, the first layer being made of copper, and forming a second layer as an externally exposed layer, on the first layer continuously, the second layer being made of gold or platinum.Type: ApplicationFiled: January 2, 2003Publication date: June 5, 2003Inventor: Sun-Ki Kim
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Publication number: 20030089613Abstract: The present invention is to provide a method of selective electroplating comprises a substrate. The substrate may include printed circuir board or other plating metal article on printed circuit board surface specified region. Then, a wet film formed on the substrate by screen-printing, wherein the wet film is photo-sensitivty. Next, it is hardening the wet film, and then exposing the wet film. Next, it is developing the wet film to expose some region for forming metal on the substrate. A metal layer formed on the substrate. Finally, it is stripping the wet film.Type: ApplicationFiled: November 15, 2001Publication date: May 15, 2003Inventor: Chang Yu Ching
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Patent number: 6555209Abstract: A method of manufacturing a multilayer wiring board comprising a step of forming an upper wiring layer (27), a part thereof being electrically connected to a pillar-shaped metallic body (24a), after he pillar-shaped metal body (24a) is formed on a lower wiring layer (22) is characterized in that the step of forming the metallic body includes a sub-step of forming a plating layer (24) constituting the metallic body, a sub-step of forming a mask layer (25) on the surface where the metal body is formed, of the plating layer, and a sub-step of etching the plating layer. The manufacture can be carried out with simple equipment combination of conventional steps and the wiring layer can be made fine.Type: GrantFiled: August 31, 2001Date of Patent: April 29, 2003Assignee: Daiwa Co., Ltd.Inventors: Eiji Yoshimura, Toshiro Higuchi
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Patent number: 6546751Abstract: A method of providing a decorative metal pattern on an electrically non-conductive substrate, such as a glass or plastic substrate, which includes applying a mixture of heat fusible material, such as glass or plastic, with a metal having a particle size less than about 500 mesh constituting at least 50% of the mixture, to the substrate in the desired pattern, heating the so-applied mixture until the heat fusible material fuses and bonds to the substrate, cleaning the substrate with the pattern thereon, and a electroplating the pattern with the desired finish metal. In one method in which the mixture includes glass, a negative resist is adhesively secured to the substrate and the mixture is applied. The resist disintegrates upon heating. In another method, used when the substrate is plastic, a mixture of plastic and metal in past form is applied to the substrate by silk screening or pad printing to form the pattern.Type: GrantFiled: August 16, 1999Date of Patent: April 15, 2003Inventor: Peter Jaeger
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Publication number: 20030047459Abstract: The present invention refers to methods for the manufacture of gas-diffusion electrodes to be used for water electrolysis and ozone production, as well as electrodes for fuel cells and other electrochemical devices. A portion of protons of an ion-exchange polymer is substituted in the channels of a channel-cluster structure of an ion-exchange polymer with cations of metal catalyst. This substitution is performed via the ion exchange process. Then said cations are electrochemically reduced in the form of metal particles of a catalyst on those areas of substrate where the latter is in contact with the channels of the channel-cluster structure of the ion-exchange polymer layer.Type: ApplicationFiled: August 21, 2002Publication date: March 13, 2003Inventors: Alexander Timonov, Sergey Logvinov, Nikolay Shkolnik, Sam Kogan
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Patent number: 6530141Abstract: A method of forming a thin film magnetic head, including forming a first magnetic layer, forming a second magnetic layer as a magnetic flux passage in combination with the first magnetic layer, and forming a laminate structure body between the first magnetic layer and the second magnetic layer. The forming of the laminate structure body includes forming a third magnetic layer, a fourth magnetic layer and a non-magnetic conductive layer between the third magnetic layer and the fourth magnetic layer, projecting the laminate structure body more toward an air bearing surface than a projection of the first magnetic layer and the second magnetic layer toward the air bearing surface, and providing the laminate structure body with a width which is smaller than a width of the first magnetic layer and the second magnetic layer.Type: GrantFiled: June 14, 2001Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Matahiro Komuro, Tomohiro Okada, Moriaki Fuyama, Tetsuo Ito, Hiroshi Fukui, Yohji Maruyama, Miki Hara, Hisashi Takano
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Patent number: 6517894Abstract: A method and apparatus for plating a substrate is provided, wherein fine pits formed in the substrate, such as fine channels for wiring, are filled with a copper, copper alloy, or other material with low electrical resistance. The method is performed on a wafer W having fine pits (10) to fill the fine pits with a metal (13) and includes performing a first plating process (11) by immersing the wafer in a first plating solution having a composition superior in throwing power; and performing a second plating process (12) by immersing the substrate in a second plating solution having a composition superior in leveling ability.Type: GrantFiled: October 27, 2000Date of Patent: February 11, 2003Assignee: Ebara CorporationInventors: Akihisa Hongo, Mizuki Nagai, Kanji Ohno, Ryoichi Kimizuka, Megumi Maruyama
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Publication number: 20030010645Abstract: A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10&mgr; to 100&mgr; and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.Type: ApplicationFiled: June 14, 2002Publication date: January 16, 2003Applicant: Mattson Technology, Inc.Inventors: Chiu H. Ting, Igor Ivanov
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Publication number: 20030000844Abstract: One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.Type: ApplicationFiled: June 26, 2002Publication date: January 2, 2003Applicant: Applied Materials, Inc.Inventors: Daniel A. Carl, Barry Chin, Liang Chen, Robin Cheung, Peijun Ding, Yezdi Dordi, Imran Hashim, Peter Hey, Ashok K. Sinha
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Patent number: 6471879Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.Type: GrantFiled: September 21, 2001Date of Patent: October 29, 2002Assignee: Micron Technology, Inc.Inventors: Robert J. Hanson, Won-Joo Kim, Mike E. Pugh
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Publication number: 20020139686Abstract: A composition and method for cleaning and conditioning a non-conductive surface defined by a through hole in a printed circuit board (PCB) is disclosed. The through hole surface is contacted with the composition of the invention to provide a cleaned and conditioned surface. The clean and conditioned surface is coated with conductive carbon particles (usually graphite) to provide a carbon-coated surface. The carbon-coated surface is electro plated and then soldered using hot solder. Those surfaces that have been soldered and also treated with the composition of the invention exhibit fewer blow hole problems. The composition of the invention comprises carbonates, binders, and resins, and combinations thereof, that improve the adhesion and coverage of a coating containing graphite to a surface defined by a through hole bore or other substrate. (“Through holes” as used herein refers both to through holes and to vias.Type: ApplicationFiled: March 1, 2002Publication date: October 3, 2002Inventors: Michael V. Carano, Frank Polakovic
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Publication number: 20020139680Abstract: A method for fabricating an abrasive tool. A tool substrate is provided. A surface of the substrate is coated with an electroplatable bonding material. The electroplatable bonding material comprises a mixture of a conductive material and an adhesive material. Abrasive particles are adhered to the bonding material. The abrasive particles are adhered so as to have a predetermined distribution over the coated surface of the substrate. A metal layer is electroplated to the electroplatable bonding material to secure the abrasive particles to the substrate. Thus, in accordance with the present invention, the fabricated abrasive tool has abrasive particles having the predetermine distribution and fixed to the substrate by the adhesive material and the electroplated metal layer.Type: ApplicationFiled: March 27, 2002Publication date: October 3, 2002Inventor: Kosta Louis George
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Publication number: 20020130047Abstract: According to the invention, an article that is exposed to high temperature e.g., over 1000° C. during operation is disclosed. In one embodiment, a method for a gas turbine engine includes a directionally solidifed metallic substrate, e.g., a superalloy, which defines an airfoil, a root and a platform located between the blade and root. The platform has an underside adjacent the root, and a corrosion resistant overlay coating such as an MCrAlY or a noble metal containing aluminide or corrosion inhibiting ceramic is located on portions or the blade not previously covered with such coatings, e.g., the underside of the platform and the neck. The applied coating prevents corrosion and stress corrosion cracking of blade in these regions. Where the airfoil is also created, the airfoil coating may have a composition different from that of the coating on the underplatform surfaces.Type: ApplicationFiled: January 29, 2002Publication date: September 19, 2002Applicant: United Technologies CorporationInventors: William Patrick Allen, Walter E. Olson, Dilip M. Shah, Alan David Cetel