Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
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Publication number: 20080189943Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.Type: ApplicationFiled: April 7, 2008Publication date: August 14, 2008Applicant: IBIDEN CO., LTD.Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
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Patent number: 7407595Abstract: A manufacturing method of an optical member for optical path conversion to be connected to an optical waveguide provided in a substrate includes forming plural inclined surfaces on a wafer by etching, forming openings corresponding to the inclined surfaces in a plate-like member, forming a combined body, in which the inclined surfaces and the openings correspond to each other, by bonding the wafer and the plate-like member, and dividing the combined body into small pieces each of which includes the inclined surface and the opening.Type: GrantFiled: July 20, 2005Date of Patent: August 5, 2008Assignee: Fuji Xerox Co., Ltd.Inventor: Tomoki Umezawa
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Patent number: 7407596Abstract: A fluxgate sensor is integrated in a printed circuit board. The fluxgate sensor has two bar-type (or rectangular-ring shaped) soft magnetic cores to form a closed magnetic path on a printed circuit board and an excitation coil in the form of a metal film is wound around the two bar-type soft magnetic cores either in a united structure that winds the two bar-type soft magnetic cores altogether, or in a separated structure that winds the two bar-type soft magnetic cores respectively, both in a pattern of number ‘8’. A pick-up coil is mounted on the excitation coil, either winding the two bars altogether, or respectively, in a solenoid pattern. The fluxgate sensor integrated in the printed circuit board can be mass-produced at a cheap manufacturing cost. The fluxgate sensor also can be made compact-sized, and at the same time, is capable of forming a closed-magnetic path.Type: GrantFiled: February 28, 2007Date of Patent: August 5, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Won-youl Choi, Byeong-cheon Koh, Kyung-won Na, Sang-on Choi, Myung-sam Kang, Keon-yang Park
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Publication number: 20080178925Abstract: A thin film solar cell module of see-through type and method of fabricating the same is provided. The method includes forming scribe lines in two directions in a first electrode material layer disposed on an opaque substrate so as to avoid short circuit caused by a high-temperature laser scribing process and reduction of the process yield. Moreover, the thin film solar cell module of see-through type has holes through the opaque substrate so that the cell module increases the transmittance of the cells.Type: ApplicationFiled: April 3, 2008Publication date: July 31, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jian-Shu Wu, Te-Chi Wong
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Patent number: 7403095Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.Type: GrantFiled: October 4, 2005Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Brian Vialpando, Eric William Beach, Philipp Steinmann
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Publication number: 20080170727Abstract: A micromachined microphone or speaker embedded within, or positioned on top of, a substrate suitable for carrying microelectronic chips and components. The acoustic element converts sound energy into electrical energy which is then amplified by electronic components positioned on the surface of the substrate. Alternatively, the acoustic element may be driven by electronics to produce sound. The substrate can be used in standard microelectronic packaging applications.Type: ApplicationFiled: December 14, 2007Publication date: July 17, 2008Inventors: Mark Bachman, Guann-Pyng Li
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Patent number: 7399423Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer of a fuel cell so as to be capable of stably producing high purity hydrogen gas.Type: GrantFiled: December 16, 2005Date of Patent: July 15, 2008Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Hiroshi Yagi, Takanori Maeda, Yoshinori Oota, Yasuhiro Uchida
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Publication number: 20080164237Abstract: A piezoelectric-driven MEMS device can be fabricated reliably and consistently. The piezoelectric-driven MEMS device includes: a movable flat beam having a piezoelectric film disposed above a substrate with a recessed portion such that the piezoelectric film is bridged over the recessed portion, piezoelectric drive mechanisms disposed at both ends of the piezoelectric film and configured to drive the piezoelectric film, and a first electrode disposed at the center of the substrate-side of the piezoelectric film, and a second electrode disposed on a flat part of the recessed portion of the substrate and facing the first electrode of the movable flat beam.Type: ApplicationFiled: February 27, 2008Publication date: July 10, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi Kawakubo, Toshihiko Nagano, Kazuhide Abe, Michihiko Nishigaki
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Patent number: 7396475Abstract: The present invention provides a method for forming a stepped structure on a substrate that features transferring, into the substrate, an inverse shape of the stepped structure disposed on the substrate.Type: GrantFiled: April 25, 2003Date of Patent: July 8, 2008Assignee: Molecular Imprints, Inc.Inventor: Sidlgata V. Sreenivasan
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Patent number: 7393457Abstract: The present invention is to provide a method for making a shadow mask for an opposed discharge plasma display panel by etching one lateral surface of a metal slab to produce a plurality of parallel and equidistant barrier ribs along the vertical and horizontal directions on the lateral surface and a discharging cell by enclosing every four adjacent barrier ribs. A shadow hole is formed at the middle of each discharging cell and etched through the metal slab, and at least one groove interconnected to the shadow holes is produced on another lateral surface of the metal slab by utilizing a rolling process or a stamping process. The adjacent grooves are interconnected with each other, and a plurality of air guide channels is formed on another lateral side, such that a shadow mask can be made in a simple and fast manner, chemical pollutions caused by a traditional double-sided etching can be minimized, and the product yield rate and the manufacturing cost can be effectively improved and lowered.Type: GrantFiled: September 15, 2006Date of Patent: July 1, 2008Assignee: Marketech International CorporationInventors: Hsu-Pin Kao, Jang-Jeng Liang, Sheng-Wen Hsu, Hsu-Chia Kao
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Patent number: 7390422Abstract: A method for manufacturing a printing plate is realizes a precise and fine pattern by minimizing a variation of etching critical dimension. The method includes forming a hard mask having an opening on an insulating substrate; forming a first trench having a first depth in the insulating substrate using the hard mask; coating, patterning and developing a first photoresist over an entire surface of the insulating substrate including the hard mask; and forming at least a second trench having a second depth in the insulating substrate using the hard mask, wherein the second depth is deeper than the first depth.Type: GrantFiled: June 29, 2006Date of Patent: June 24, 2008Assignee: LG Display Co., Ltd.Inventors: Soon Sung Yoo, Oh Nam Kwon, Heung Lyul Cho, Jung Jae Lee, Seung Hee Nam
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Patent number: 7387740Abstract: An exemplary method of manufacturing a metal cover (1) with blind holes (3) therein includes: step (60), preparing a metal substrate; step (62), covering the metal substrate with a protective film formed by electrophoretic deposition; step (64), forming holes in the protective film according to an intended pattern of the blind holes in the metal cover, thus exposing the metal surface through the holes; step (66), etching the metal substrate in the exposed areas to form the blind holes; and step (68), removing a remainder of the protective film from the metal substrate, thereby obtaining the finished metal cover. The method involving etching is relatively low-cost. Additionally, because electrophoretic deposition is used to cover the metal substrate with the protective film, the protective film can be formed on all surfaces of the metal substrate. Thus the method is especially advantageous for manufacturing a metal cover having a three-dimensional shape.Type: GrantFiled: November 7, 2005Date of Patent: June 17, 2008Assignee: Sutech Trading LimitedInventor: Wen-Te Lai
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Patent number: 7387739Abstract: A plurality of penetrating holes are formed in a substrate, each of the penetrating holes connecting a first opening and a second opening larger than the first opening. An etching resistant film is formed on a first surface of the substrate avoiding areas in which the first openings will be formed, part of the second surface in which the penetrating holes are formed being exposed so as to expose areas each of which includes two or more of the second openings. Small holes are formed in the formation regions for each of the penetrating holes. Etching having crystal orientation dependence is performed from both the first and second surfaces of the substrate.Type: GrantFiled: April 14, 2003Date of Patent: June 17, 2008Assignee: Seiko Epson CorporationInventors: Shinichi Yotsuya, Kazushige Umetsu, Daisuke Sawaki
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Publication number: 20080129415Abstract: The object of the present invention is to provide a piezoelectric resonator of which vibration frequency can be accurately adjusted and the adjustment accuracy of the vibration frequency can be improved. The piezoelectric resonator of the present invention includes an vibrating arm extended from a base, and a metal film for adjusting frequency formed along the longitudinal direction from the tip of the vibrating arm, in which the metal film for adjusting frequency is provided with a block pattern divided into a plurality of blocks in compliance with the amount of frequency adjustment. Structuring as above, the frequency adjustment of the piezoelectric resonator is conducted by eliminating the blocks in compliance with the amount of frequency adjustment one by one, which makes it possible to adjust the vibration frequency with accuracy.Type: ApplicationFiled: November 29, 2007Publication date: June 5, 2008Inventor: Yu Iwai
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Publication number: 20080124554Abstract: A semiconductor device includes a substrate and a first insulating layer, contact plugs, metal wirings, and a second insulating layer sequentially formed over the substrate. The first insulating layer has via holes. The contact plugs are formed in the via holes. The metal wirings are electrically connected to the contact plugs. The substrate and the first and second insulating layers include first, second, and third insulating macromolecular substances, respectively, with flexible and insulating properties. The contact plugs and metal wirings include first and second conducting macromolecular substances, respectively, with flexible and conductive properties. Using the flexible macromolecular substances to form the components of the semiconductor device makes it resistant to being easily broken by impacts and increases the possibility of application to products, since it may be applicable to locations where bending may be necessary.Type: ApplicationFiled: October 31, 2007Publication date: May 29, 2008Inventor: Ji-Ho HONG
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Patent number: 7361284Abstract: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to the cavities is removed so that the remaining cap wafer forms a plurality of support blocks. A device wafer is provided, and the support blocks are bonded to the device wafer so that the support blocks and the transparent wafer hermitically seal the devices disposed in the device wafer.Type: GrantFiled: June 23, 2006Date of Patent: April 22, 2008Assignee: Touch Micro-System Technology Inc.Inventor: Chih-Hsien Chen
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Patent number: 7358184Abstract: A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low resistivity and thus may serve as an electrical connection between two separate conductive layers. This manufacturing method of the conductive via plug may achieve simultaneously deposition, patterning and etching purposes, which significantly simplifies the manufacturing process.Type: GrantFiled: April 7, 2004Date of Patent: April 15, 2008Assignee: Industrial Technology Research InstituteInventors: Chien-Hung Liu, Ming-Huan Yang, Jane Chang, Chun-Jung Chen, Chao-Kai Cheng, Kou-Chen Liu
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Publication number: 20080073318Abstract: When forming an opening conforming to a groove of a quartz resonator in a metal film serving as a mask of the quartz resonator by conducting etching, the outer periphery of the metal film is wavingly etched. Therefore, when the groove is formed on the quartz resonator, the quartz resonator is formed according to the above-described metal film, which results in appearance defects or dimension defects. In order to solve the problems, the outer shape of the metal film is formed smaller than the outer shape of the quartz resonator before forming the opening conforming to the groove of the quartz resonator in the metal film, then etching of the metal film and etching of the quartz resonator are performed.Type: ApplicationFiled: September 18, 2007Publication date: March 27, 2008Inventor: Takefumi Saito
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Publication number: 20080061027Abstract: A method is provided for fabricating a fuel cell that requires only front side alignment techniques to fabricate gas access holes. The method comprises etching the front side of a substrate (12) to provide a channel (24, 26), and forming a pedestal (54, 88) on the front side of the substrate, wherein the pedestal (54, 88) comprises an anode side (56, 89) defining a fuel region (68, 102) aligned with the channel (24, 26). An electrolyte (46, 96) is positioned between the anode side (56, 89) and a cathode side (58, 90), and the fuel region (68, 102) is capped with an insulator (66, 98). A portion of the substrate (12) is removed from a back side to expose the channel (24, 26).Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Pawitter S. Mangat, John J. D'Urso, Chowdary R. Koripella, Ramkumar Krishnan
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Patent number: 7323111Abstract: A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic etching of preferred crystal directions in single crystal materials such as silicon. A portion of the mold material adjacent the initial reference surface is removed to expose a new reference surface at a tilt angle with respect to the initial reference surface. The modified mold cavities have their respective axes at a new desired tilt angle relative to the new reference surface.Type: GrantFiled: January 31, 2005Date of Patent: January 29, 2008Assignee: Metadigm LLCInventor: Victor B. Kley
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Patent number: 7309641Abstract: A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench.Type: GrantFiled: November 24, 2004Date of Patent: December 18, 2007Assignee: United Microelectronics Corp.Inventor: Kao-Su Huang
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Patent number: 7303648Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.Type: GrantFiled: May 25, 2004Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Hyun-Mog Park, Vijayakumar Ramachandrarao
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Patent number: 7297285Abstract: A manufacturing process of an emboss type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic surface layer and the organic surface layer is solidified.Type: GrantFiled: August 5, 2005Date of Patent: November 20, 2007Inventor: Roger Chang
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Publication number: 20070243404Abstract: A manufacturing method of a glass circuit board includes the steps of providing a glass substrate; forming a metal layer on a surface of the glass substrate; forming a metal connecting layer on the metal layer; patterning the metal layer and the metal connecting layer to expose a part of the surface of the glass substrate; and forming an insulation layer with at least one opening on the patterned metal connecting layer and the exposed part of the surface. A glass circuit board is also disclosed, which includes a glass substrate, a patterned metal layer, a patterned metal connecting layer and an insulation layer. The glass substrate has a surface. The patterned metal layer is disposed on the surface of the glass substrate, and a part of the surface is exposed from the patterned metal layer. The patterned metal connecting layer is disposed on the patterned metal layer.Type: ApplicationFiled: April 13, 2007Publication date: October 18, 2007Applicant: GIGNO TECHNOLOGY CO., LTD.Inventor: Feng-Li Lin
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Patent number: 7279110Abstract: A method and apparatus for patterning an array of SLM mirrors with a phase step is disclosed. Additional embodiments of the present invention describe a method for processing a substrate, wherein the processed substrate is used in the apparatus for patterning an array of SLM mirrors with a phase step. The processed substrate is then placed in close proximity to the mirrors and the etching/deposition process is then done through openings in the substrate. In embodiments in which the processed substrate does not have a high enough density of openings, a stepping and repeating process is used in order to achieve complete process coverage of every mirror in an array of SLM mirrors.Type: GrantFiled: December 27, 2004Date of Patent: October 9, 2007Assignee: ASML Holding N.V.Inventor: Stephen Roux
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Patent number: 7261829Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.Type: GrantFiled: January 8, 2003Date of Patent: August 28, 2007Assignee: Infineon Technologies AGInventors: Dirk Efferenn, Hans-Peter Moll
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Patent number: 7257892Abstract: A method of manufacturing a wiring board, including: providing a resin substrate on which is formed a metal layer including a first layer and a second layer formed on the first layer; forming an interconnecting pattern by etching the metal layer so that the interconnecting pattern includes the patterned first layer and second layer and a part of the first layer remains outside the second layer as a residue of the first layer; electroless plating the interconnecting pattern and the residue of the first layer; and then washing the resin substrate. The washing of the resin substrate is performed by using at least one of an acidic solution used for dissolving and removing the residue of the first layer and a metal deposited on the residue of the first layer by the electroless plating and an alkaline solution used for dissolving the resin substrate to remove an area which supports the residue of the first layer.Type: GrantFiled: February 17, 2006Date of Patent: August 21, 2007Assignee: Seiko Epson CorporationInventors: Naoya Sato, Akihito Narita, Satoru Akatsuka, Tsutomu Abe
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Patent number: 7255801Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.Type: GrantFiled: April 8, 2004Date of Patent: August 14, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Hui Chen
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Patent number: 7256136Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.Type: GrantFiled: February 2, 2006Date of Patent: August 14, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Bei Chao Zhang, Liang Choo Hsia
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Patent number: 7255803Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.Type: GrantFiled: July 19, 2006Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Bradley J. Howard, Max F. Hineman
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Patent number: 7253705Abstract: An air-gap type thin-film bulk acoustic resonator. The air-gap type thin-film bulk acoustic resonator has a substrate having a cavity formed on a predetermined portion of an upper surface thereof; a resonance part having a structure of a first electrode, a piezoelectric substance, and a second electrode deposited in order and formed over the upper side of the cavity; and at least one via hole penetrating a lower surface of the substrate and connecting to the cavity.Type: GrantFiled: May 17, 2005Date of Patent: August 7, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: In-sang Song, Byeoung-ju Ha, Yun-kwon Park, Jong-seok Kim
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Patent number: 7250831Abstract: A filter using an air gap type film bulk acoustic resonator is provided. The present filter includes a substrate on which a first port, a second port, and a ground port are formed to be connected to an external terminal; at least one first film bulk acoustic resonator serially connecting the first port to the second port on the substrate; at least one second film bulk acoustic resonator parallel connected to an interconnection node formed between the first port and the second port; and at least one inductor serially connecting the second film bulk acoustic resonator to the ground port. The inductor included in the filter is fabricated with the first and second film bulk acoustic resonators as one body. Accordingly, a small-sized filter may be fabricated through a simplified process.Type: GrantFiled: May 17, 2005Date of Patent: July 31, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: In-sang Song, Byeoung-ju Ha, Yun-kwon Park, Jong-seok Kim, Duck-hwan Kim, Kuang-woo Nam, Hae-seok Park, Seog-woo Hong
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Patent number: 7250370Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.Type: GrantFiled: September 19, 2003Date of Patent: July 31, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Chung-Chi Ko, Tien I. Bao, Yun-Chen Lu
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Patent number: 7241396Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer of a fuel cell so as to be capable of stably producing high purity hydrogen gas.Type: GrantFiled: April 12, 2006Date of Patent: July 10, 2007Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Hiroshi Yagi, Takanori Maeda, Yoshinori Oota, Yasuhiro Uchida
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Patent number: 7235185Abstract: A wafer comprising a front surface and a back surface is provided. The wafer further includes a front pattern on the front surface, the front pattern having a plurality of holes. A low-viscosity fluid is formed on the front surface and filled into the holes. Following that, a high-viscosity fluid is formed and filled into the holes by diffusion.Type: GrantFiled: November 7, 2005Date of Patent: June 26, 2007Assignee: Touch Micro-System Technology Inc.Inventor: I-Ju Chen
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Publication number: 20070138129Abstract: A method for manufacturing carbon nanotube field emission includes the steps of: providing a substrate (110) with a metallic layer (130) thereon; defining a plurality of holes (131) in the metallic layer; oxidizing the metallic layer to form a metallic oxide layer (132) thereon; removing portions of the metallic oxide layer in the plurality of holes so as to expose corresponding portions of the metallic layer; forming a metal-salt catalyst layer (580) on the exposed portions of the metallic layer in the plurality of holes; and growing carbon nanotubes (690) on the substrate in the plurality of holes.Type: ApplicationFiled: August 29, 2006Publication date: June 21, 2007Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: Tsai-Shih Tung
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Patent number: 7217370Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.Type: GrantFiled: March 8, 2005Date of Patent: May 15, 2007Assignee: Hitachi Cable, Ltd.Inventors: Hiroshi Sugimoto, Tatsuya Ohtaka, Shigeharu Takahagi
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Patent number: 7217883Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.Type: GrantFiled: November 26, 2002Date of Patent: May 15, 2007Assignee: Shell Solar GmbHInventor: Adolf Münzer
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Patent number: 7204933Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.Type: GrantFiled: February 8, 2006Date of Patent: April 17, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naoto Kawamura, David R Thomas, David J Waller, Timothy L Weber
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Patent number: 7195714Abstract: A method for producing a system with a substrate with a surface and a component applied to a predetermined location of the surface of the substrate includes a step of generating a liquid volume containing the component and a step of applying the liquid volume containing the component on the surface of the substrate. At that, the liquid volume is sized so that it wets only a partial area of the surface of the substrate after its application. In the step of applying the liquid volume is placed on the surface of the substrate so that the partial area of the surface includes the predetermined location. The component or the predetermined location of the surface of the substrate is implemented so that after the application of the liquid volume a force acts on the component which is sufficient to drive the component within the liquid volume to the predetermined location. The method is completely independent of the speed of a gripper and its capability to grip and align a very small component.Type: GrantFiled: June 4, 2004Date of Patent: March 27, 2007Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.Inventor: Karlheinz Bock
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Patent number: 7192531Abstract: A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.Type: GrantFiled: June 24, 2003Date of Patent: March 20, 2007Assignee: Lam Research CorporationInventors: Sean S. Kang, Sangheon Lee, Wan-Lin Chen, Eric A. Hudson, Reza Sadjadi
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Patent number: 7163641Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.Type: GrantFiled: May 30, 2003Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, David S. Becker
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Patent number: 7141176Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.Type: GrantFiled: July 25, 2002Date of Patent: November 28, 2006Assignee: Alien Technology CorporationInventors: John Stephen Smith, Mark A. Hadley, Gordon S. W. Craig, Paul F. Nealey
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Patent number: 7128844Abstract: A metal layer 12 of aluminum or an aluminum alloy is formed on at least one side of a ceramic substrate 10, and a resist 14 having a predetermined shape is formed on the metal layer 12. Then, an etchant of a mixed solution prepared by mixing ferric chloride with water without adding any acids is used for etching and removing an undesired portion of the metal layer 12 to form a metal circuit 12 on the at least one side of the ceramic substrate 10.Type: GrantFiled: May 27, 2004Date of Patent: October 31, 2006Assignee: Dowa Mining Co., Ltd.Inventors: Nobuyoshi Tsukaguchi, Michihiro Kosaka
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Patent number: 7122131Abstract: The present invention is directed to a conductive paste for via conductor, comprising a Cu powder having a glass layer formed on the surface, a Ni powder having a metal oxide layer formed on the surface, and a ceramic component homogeneous as that of a ceramic component contained in a green sheet, a ceramic wiring board such as laminated ceramic capacitor, comprising via conductors formed of the same, and a method of manufacturing the same. According to the present invention, via conductors having excellent electrical conductivity can be formed by preventing the formation of a Cu—Ni alloy due to the reaction of the Cu powder and the Ni powder.Type: GrantFiled: February 25, 2005Date of Patent: October 17, 2006Assignee: Kyocera CorporationInventor: Hisashi Satou
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Patent number: 7112286Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.Type: GrantFiled: December 4, 2003Date of Patent: September 26, 2006Assignee: Texas Instruments IncorporatedInventors: Brian Vialpando, Eric William Beach, Philipp Steinmann
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Patent number: 7112287Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer of a fuel cell so as to be capable of stably producing high purity hydrogen gas.Type: GrantFiled: July 23, 2003Date of Patent: September 26, 2006Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Hiroshi Yagi, Takanori Maeda, Yoshinori Oota, Yasuhiro Uchida
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Patent number: 7078293Abstract: A method for fabricating an optical interference display cell is described. A first electrode and a sacrificial layer are sequentially formed on a transparent substrate and at least two openings are formed in the first electrode and the sacrificial layer to define a position of the optical interference display cell. An insulated heat-resistant inorganic supporter is formed in each of the openings. A second electrode is formed on the sacrificial layer and the supporters. Finally, a remote plasma etching process is used for removing the sacrificial layer.Type: GrantFiled: March 11, 2004Date of Patent: July 18, 2006Assignee: Prime View International Co., Ltd.Inventors: Wen-Jian Lin, Hsiung-Kuang Tsai
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Patent number: 7077969Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.Type: GrantFiled: November 25, 2002Date of Patent: July 18, 2006Assignee: Institut National D'OptiqueInventors: Hubert Jerominek, Christine Alain
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Patent number: 7063798Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.Type: GrantFiled: December 2, 2003Date of Patent: June 20, 2006Assignee: STMicroelectronics S.r.l.Inventors: Alessio M. D'arrigo Guiseppe, Rosario C. Spinella, Guiseppe Arena, Simona Lorenti