Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
  • Publication number: 20120267158
    Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.
    Type: Application
    Filed: July 1, 2012
    Publication date: October 25, 2012
    Applicant: International Business Machines Corporation
    Inventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
  • Publication number: 20120264064
    Abstract: The invention relates to an improved method for fabricating the amplification gap of an avalanche particle detector in which two parallel electrodes are spaced apart by dielectric spacer elements. A foil including a bulk layer made of dielectric material sandwiched by two mutually parallel metallic electrodes is provided, and holes are formed in one of the metallic layers by means of photolithography. The amplification gap is then formed in the bulk layer by means of carefully controlled etching of the bulk material through the holes formed in one of the metallic layers. The invention not only provides a simplified fabrication process, but also results in a detector with enhanced spatial and energy resolution.
    Type: Application
    Filed: September 17, 2010
    Publication date: October 18, 2012
    Applicants: CEA, CERN - EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH
    Inventors: Ioannis Giomataris, Rui De Oliveira
  • Patent number: 8287747
    Abstract: A method of processing a substrate includes the steps of providing a silicon substrate that has an etching mask layer with an opening portion at a first surface thereof and has plane orientation of {100} with the surface of the silicon being exposed from the opening portion; preparing a recessed portion that faces from the first surface to a second surface, opposite to the first surface, in the opening portion of the silicon substrate; and forming a penetration port that passes through the first surface and the second surface of the silicon substrate by executing crystalline anisotropic etching in the silicon substrate using an etching liquid in which an etching rate for etching a (100) surface of silicon is higher than an etching rate for etching a (110) surface of silicon, from the recessed portion of the silicon substrate toward the second surface.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: October 16, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Kishimoto, Taichi Yonemoto
  • Publication number: 20120257778
    Abstract: A vacuum sealed directional microphone and methods for fabricating said vacuum sealed directional microphone. A vacuum sealed directional microphone includes a rocking structure coupled to two vacuum sealed diaphragms which are responsible for collecting incoming sound and deforming under sound pressure. The rocking structure's resistance to bending aids in reducing the deflection of each diaphragm under large atmospheric pressure. Furthermore, the rocking structure exhibits little resistance about its pivot thereby enabling it to freely rotate in response to small pressure gradients characteristic of sound. The backside cavities of such a device can be fabricated without the use of the deep reactive ion etch step thereby allowing such a microphone to be fabricated with a CMOS compatible process.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 11, 2012
    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Neal A. Hall, Michael Louis Kuntzman, Karen Denise Kirk
  • Patent number: 8282842
    Abstract: A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: October 9, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Ju Wang, Jyh-Cherng Yau, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 8282841
    Abstract: A printed circuit board includes a flexible insulated substrate with a first surface and a second surface at both sides respectively, a wiring layer on the first surface, a reinforcement plate on a part of the second surface and an auxiliary layer between the second surface and the reinforcement plate. A reinforcement edge side of the reinforcement plate is located at the outside of an auxiliary edge side of the auxiliary layer.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 9, 2012
    Assignee: Fujikura Ltd.
    Inventors: Kanako Nakajima, Masatoshi Inaba, Yoshiharu Unami
  • Publication number: 20120245034
    Abstract: A low AC-loss multi-filament superconducting wire material of the invention includes an elongated base material, an intermediate layer formed on the base material; a superconducting layer formed on the intermediate layer, and a metal stabilizing layer formed on the superconducting layer, wherein a plurality of grooves extending along a long direction of the base material is formed in parallel in a width direction of the base material, and reach the intermediate layer from the metal stabilizing layer via the superconducting layer to expose the intermediate layer; and a difference ?d (=d1?d2) between a width d1 of the grooves at a lower part of the superconducting layer and a width d2 of the grooves at a lower part of the metal stabilizing layer is not more than 10 ?m.
    Type: Application
    Filed: April 26, 2012
    Publication date: September 27, 2012
    Applicants: FUJIKURA LTD., INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER
    Inventors: Takato MACHI, Hiroshi TOBITA, Yasuo TAKAHASHI, Keiichi TANABE, Teruo IZUMI
  • Patent number: 8273256
    Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: September 25, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Shu-Sheng Chiang, Tsung-Yuan Chen, Wei-Ming Cheng
  • Patent number: 8268182
    Abstract: A processing method of forming a through-hole in a workpiece by means of a pulsed laser beam includes the steps of providing a removable sacrifice layer on the workpiece, forming a through-hole in the workpiece by the laser beam in a state where the sacrifice layer is provided, and removing the sacrifice layer from the workpiece after the step of forming the through-hole.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: September 18, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hidehiko Mishima, Yasuhiro Okuda, Shuji Sakabe, Masaki Hashida, Seiji Shimizu
  • Publication number: 20120231624
    Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Audrey Barthelot, Jean-Philippe Polizzi
  • Patent number: 8252683
    Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: August 28, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Kwon-Seob Lim
  • Publication number: 20120205148
    Abstract: Provided is a device packaging structure including: an interposer substrate including a substrate, and a plurality of through-hole interconnections formed inside a plurality of through-holes passing through the substrate from a first main surface toward a second main surface, the first main surface being one main surface of the substrate, the second main surface being the other main surface thereof; a first device which includes a plurality of electrodes and is arranged so that these electrodes face the first main surface; and a second device which includes a plurality of electrodes of which an arrangement is different from an arrangement of each of the electrodes of the first device, and is arranged so that these electrodes face the second main surface.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 16, 2012
    Applicant: FUJIKURA LTD.
    Inventors: Satoshi YAMAMOTO, Hiroyuki HIRANO, Takanao SUZUKI
  • Patent number: 8241509
    Abstract: Fluidic conduits, which can be used in microarraying systems, dip pen nanolithography systems, fluidic circuits, and microfluidic systems, are disclosed that use channel spring probes that include at least one capillary channel. Formed from spring beams (e.g., stressy metal beams) that curve away from the substrate when released, channels can either be integrated into the spring beams or formed on the spring beams. Capillary forces produced by the narrow channels allow liquid to be gathered, held, and dispensed by the channel spring probes. Because the channel spring beams can be produced using conventional semiconductor processes, significant design flexibility and cost efficiencies can be achieved.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: August 14, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Thomas Hantschel, David K. Fork, Eugene M. Chow, Dirk De Bruyker, Michel A. Rosa
  • Publication number: 20120194496
    Abstract: This disclosure provides systems, methods and apparatuses for supporting a mechanical layer. In one aspect, an electromechanical systems device includes a substrate, a mechanical layer, and a post positioned on the substrate for supporting the mechanical layer. The mechanical layer is spaced from the substrate and defines one side of a gap between the mechanical layer and the substrate, and the mechanical layer is movable in the gap between an actuated position and a relaxed position. The post includes a wing portion in contact with a portion of the mechanical layer, the wing portion positioned between the gap and the mechanical layer. The wing portion can include a plurality of layers configured to control the curvature of the mechanical layer.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Fan Zhong, David Heald, Wenyu Sun, Chuan Pu, Chandra Tupelly
  • Publication number: 20120187278
    Abstract: A microchannel plate (1) having an array of channels (5),includes a substrate (2) and, deposited on the substrate, a hydrogenated amorphous silicon film (3) having a thickness ranging between 50 ?m and 200 ?m, preferably between 80 ?m and 120 ?m, the film including the array of channels (5). Preferably, the substrate (2) is an integrated circuit having an internal electronic readout circuit and pixilated collection electrodes (8), and the film (3) is integrated on the substrate (2). The channels (5) may be formed by a Deep Reactive Ion Etching (DRIE) process.
    Type: Application
    Filed: July 8, 2010
    Publication date: July 26, 2012
    Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Pierre Jarron, Nicolas Wyrsch
  • Publication number: 20120187077
    Abstract: Provided are a micro-electromechanical systems (MEMS) microphone and a method of manufacturing the same. A manufacturing process is simplified compared to a conventional art using both upper and lower substrate processes. Since defects which may occur during manufacturing are reduced due to the simplified manufacturing process, the manufacturing throughput is improved, and since durability of the MEMS microphone is improved, system stability against the external environment is improved.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 26, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jae Woo LEE, Kang Ho PARK, Jong Dae KIM
  • Publication number: 20120175340
    Abstract: In order to provide a method for manufacturing a wiring board free from contact fault, a method of the present invention, which manufactures a wiring board (1) including an Al alloy pad (3) on a base layer (2), a gate insulating film (4) and an interlayer insulating film (5) above the Al alloy pad (3), and a contact hole whose opening part reaches a part of the Al alloy pad (3), includes the steps of: forming a contact hole (7) in the gate insulating film (4) and the interlayer insulating film (5) by dry etching so as to expose, in the contact hole (7), at least part of an end part (20) of the Al alloy pad (3) and a part (10) of the base layer (2) which part (10) is adjacent to at least the part of the end part (20); and removing, after forming the contact hole (7), an electrically nonconductive layer (9) caused on a surface of the Al alloy pad (3) by the dry etching.
    Type: Application
    Filed: April 28, 2010
    Publication date: July 12, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Publication number: 20120167659
    Abstract: Various embodiments relate to a pressure sensor and related methods of manufacturing and use. A pressure sensor may include an electrical contact included in a flexible membrane that deflects in response to a measured ambient pressure. The electrical contact may be separated from a signal path through a cavity formed using a sacrificial layer and PVD plugs. At one or more defined touch-point pressure thresholds, the membrane of the pressure sensor may deflect so that the state of contact between an electrical contact and one or more sections of a signal path may change. In some embodiments, the change of state may cause the pressure sensor to trigger an alarm in the electrical circuit. Various embodiments also enable the operation of the electrical circuit for testing and calibration through the use of one or more actuation electrode layers.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: NXP B.V.
    Inventors: Willem Frederik Adrianus Besling, Peter Gerard Steeneken, Olaf Wunnicke
  • Publication number: 20120168212
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a base substrate having a metal pattern for a circuit; and a surface roughness provided on the metal pattern, wherein the surface roughness has a first surface roughness in an anchor structure and a second surface roughness having a black oxide layer in a needle structure formed on the first surface roughness.
    Type: Application
    Filed: November 30, 2011
    Publication date: July 5, 2012
    Applicants: KOREA E&S CO., LTD., SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Gi HA, Jae Won JUNG, Yong Hwan KIM, Jong Jin LEE, Ja Ho KOO, Young Hwan SHIN, Dong Kyu LEE
  • Patent number: 8211322
    Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gun Park, Dong-Won Kim, Sung-Young Lee, Yang-Kyu Choi, Chang-Hoon Kim, Ju-Hyun Kim
  • Publication number: 20120152890
    Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 21, 2012
    Applicant: PHILTECH INC.
    Inventor: Yuji FURUMURA
  • Patent number: 8203776
    Abstract: A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second sacrificial layer is formed over the metal layer, and a portion thereof is removed. A third sacrificial layer is formed over the second sacrificial layer, and an upper metal layer is formed over the third sacrificial layer. A portion of the upper metal layer is removed, and the first, second and third sacrificial layers are removed.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: June 19, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Rosemary Urmese Anthraper, Lucius M. Sherwin, Irma Izzeth Annillo
  • Patent number: 8202439
    Abstract: A diaphragm is formed by etching a substrate. This substrate has a first surface provided with a depression by isotropic dry etching, and a second surface opposite the first surface. Furthermore, a through-hole is formed from the depression to the second surface by anisotropic dry etching. The depression and the through-hole are formed by using one resist mask. The depression has a hemispherical shape or a semi-elliptical spherical shape.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: June 19, 2012
    Assignee: Panasonic Corporation
    Inventors: Masaya Nakatani, Soichiro Hiraoka, Hiroshi Ushio, Akiyoshi Oshima, Hiroaki Oka, Fumiaki Emoto
  • Publication number: 20120132614
    Abstract: A flexible substrate layer haying metallic bus-lines and connecting stitches is formed. A trace layer haying electrical traces and thermal vias is also formed. The substrate layer and the trace layer are bonded together by way of respective thermal pathways and electrically interconnected. The resulting layer-wise assembly is configured to support and electrically interconnect an array of photovoltaic cells and to channel away heat during operation.
    Type: Application
    Filed: February 7, 2012
    Publication date: May 31, 2012
    Inventor: Karl S. Weibezahn
  • Patent number: 8187478
    Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: May 29, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Yi-Chun Liu
  • Publication number: 20120125882
    Abstract: A method of patterning a conductor on a substrate, the conductor including a unique location indicia that may be sensed with a sensing device, and the location on the substrate determined therefrom.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Inventors: Billy L. Weaver, Brock A. Hable
  • Patent number: 8181594
    Abstract: A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, Hendrik F. Hamann, Herschel M. Marchman, Robert J. Von Gutfeld
  • Publication number: 20120118852
    Abstract: In a method for manufacturing a quartz crystal unit, a metal film is formed on a quartz crystal wafer which is then etched to form a quartz crystal tuning fork resonator having first and second tines vibratable in flexural and fundamental modes. A groove is chemically etched in a first main surface of both tines such that a first surface of the groove is opposite a first side surface of the corresponding tine. The width of the groove is greater than a distance in the width direction from the groove first surface to the first side surface of the corresponding tine. An electrode is formed on each groove first surface and on the first side surface of both tines with the electrode on the groove first surface of the first tine having the same electrical polarity as the electrode on the first side surface of the second tine.
    Type: Application
    Filed: December 8, 2011
    Publication date: May 17, 2012
    Inventor: Hirofumi Kawashima
  • Publication number: 20120118624
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Application
    Filed: September 25, 2011
    Publication date: May 17, 2012
    Applicant: GETAC TECHNOLOGY CORPORATION
    Inventor: Cheng-Hung Chiang
  • Patent number: 8177988
    Abstract: A method for manufacturing a substrate for a liquid discharge head having a silicon substrate provided with a supply port of a liquid comprises steps of preparing a substrate which is provided with a passive film on one side face thereof, has a first recess and a second recess provided therein so as to penetrate from the one side face into the inner part through the passive film, wherein the recesses satisfy a relation of a ×tan 54.7 degrees?d, where a is defined as a distance between the first recess and the second recess, and d is defined as a depth of the second recess, and forming the supply port by anisotropically etching the crystal from the one side face.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: May 15, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroto Komiyama, Hirokazu Komuro, Satoshi Ibe, Takuya Hatsui, Keisuke Kishimoto, Shimpei Otaka, Sadayoshi Sakuma
  • Publication number: 20120112387
    Abstract: A heating mold for thermal nanoimprint lithography comprising resistive heating means and collecting means for collecting the electromagnetic energy of a variable electromagnetic field emitted by a source located outside the mold, said collecting means being connected to said resistive heating means (34) in which said energy is dissipated. Method for manufacturing this mold. A thermal nanoimprint lithography device comprising said mold. A method for preparing a substrate comprising a surface nanostructured by a thermal nanoimprint lithography technique, wherein said mold is applied.
    Type: Application
    Filed: September 7, 2011
    Publication date: May 10, 2012
    Applicant: Commissariat a I'energie atomique et aux energies alternatives
    Inventors: Stefan Landis, Sergio Nicoletti
  • Publication number: 20120111825
    Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaushik Chanda, Cathryn J. Christiansen, Daniel C. Edelstein, Satyanarayana V. Nitta, Son V. Nguyen, Shom Ponoth, Hosadurga Shobha
  • Patent number: 8173033
    Abstract: In a nano filter structure for breathing and a manufacturing method of the nano filter structure, a semiconductor process technology is used for manufacturing a nano filter structure comprising a top gate, a bottom gate, a plurality of sidewall gates and a plurality of supports. The sidewall gates include a plurality of filterable gratings, and the filterable gratings are controlled precisely to a nanoscale by a semiconductor process technology. Therefore, the nano filterable gratings can be manufactured easily and quickly, and the multilayer design of the filterable gratings enhances the aperture ratio of a filter material, such that users can inhale or exhale easily through the filter material.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: May 8, 2012
    Inventor: Shu-Yuan Chuang
  • Patent number: 8166635
    Abstract: In a current collector laminating step, a current-collector laminate unit 30 composed of current-collector materials 31 and 32 and a film material 33 is formed. Resist layers 34 having a predetermined pattern are formed on both surfaces of the current-collector laminate unit 30. An etching process is performed with the resist layers 34 used as a mask, whereby through-holes 20a and 23a are formed on the respective current-collector materials 31 and 32. The resist layers 34 are removed from the current-collector laminate unit 30. Since the etching process is performed on the plural current-collector materials 31 and 32, productivity of an electrode can be enhanced. During the application of the slurry, the film material 33 prevents the leakage of the electrode slurry. Therefore, the current-collector laminate unit 30 can be conveyed in the horizontal direction, whereby the productivity of the electrode can be enhanced.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: May 1, 2012
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Mitsuru Nagai, Nobuo Ando, Takashi Utsunomiya, Yutaka Sato, Ken Baba
  • Patent number: 8166648
    Abstract: There is provided a wiring substrate manufacturing method. The wiring substrate includes: a plurality of conductor patterns formed on a mounting surface on which an electronic component is to be mounted, wherein each of the conductor patterns is covered with a corresponding one of solder layers; and partition walls made of insulating material and formed along the conductor patterns on the mounting surface such that each of the partition walls is provided between the adjacent conductor patterns with a clearance interposed therebetween.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 1, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Katsuya Fukase
  • Patent number: 8163586
    Abstract: A method for producing a device with at least one suspended membrane, including the following steps: Producing a trench through a first sacrificial layer and a second layer deposited on the first sacrificial layer, the trench completely surrounding at least a portion of the first sacrificial layer and at least a portion of the second layer, filling all or a portion of the trench with at least one material capable of resisting at least one etching agent, and etching the portion of the first sacrificial layer with the etching agent through at least one opening made in the second layer, the portion of the second layer forming at least one portion of the suspended membrane.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 24, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Patrice Rey, Mouna Salhi
  • Publication number: 20120094323
    Abstract: Disclosed is a device for determining the cardiotoxicity of a chemical compound, comprising a substrate (10) carrying a deformable stack (34), said stack being partially detached from the substrate by a cavity (32) allowing an out-of-plane deformation of the stack, said stack comprising a first deformable layer (16), a second deformable layer (20) and a multi-electrode structure (18) sandwiched between the first and second deformable layers, the second deformable layer carrying a pattern of cardiomyocytes (28) adhered thereto; and a liquid container (26) mounted on the substrate for exposing the cardiomyocytes to the chemical compound. A method of manufacturing such a device is also disclosed. The present invention further relates to the use of the device for drug target discovery and/or drug development and a method for developing a disease model for a disease that is caused by or modified by stretching of cells, in particular a cardiac disease model.
    Type: Application
    Filed: February 2, 2010
    Publication date: April 19, 2012
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Ronald Dekker, Anja Van De Stolpe
  • Patent number: 8158521
    Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Chung-Chi Ko, Tien I Bao, Yun-Chen Lu
  • Publication number: 20120087522
    Abstract: A piezoelectric microspeaker and a method of fabricating the same are provided. The piezoelectric microspeaker includes a substrate having a through hole therein; a diaphragm disposed on the substrate and covering the through hole; and a plurality of piezoelectric actuators including a piezoelectric member, a first electrode, and a second electrode, wherein the first and second electrodes are configured to induce an electric field in the piezoelectric member. The piezoelectric actuators include a central actuator, which is disposed on a central portion of the diaphragm and a plurality of edge actuators, which are disposed a predetermined distance apart from the central actuator and are formed on a plurality of edge portions of the diaphragm.
    Type: Application
    Filed: June 27, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo-Ho LEE, Dong-Kyun KIM, Sang-Hun LEE, Seok-Whan CHUNG
  • Patent number: 8153019
    Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, J. Neil Greeley
  • Publication number: 20120081348
    Abstract: The present disclosure provides systems, methods, and apparatus to facilitate edge routing among a plurality of microelectromechanical devices arranged in a mosaic or array. In one aspect, the disclosed implementations modify the construction of a movable layer, such that portions of the movable layer, in addition to serving their original functions, also facilitate routing from a single edge of the device. In some implementations, portions of the movable layer are re-oriented to achieve edge routing, while in others, the orientation remains the same but electrical connections are altered.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventor: Yeh-Jiun Tung
  • Publication number: 20120080400
    Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 5, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Sho AKAI, Tatsuya Imai, Iku Tokihisa
  • Patent number: 8142669
    Abstract: An electromechanical element includes a mechanically movable element through a hollow formed on a substrate, and a plurality of holes formed in the movable element. In the electromechanical element, the plurality of holes are arranged such that at least two holes are in a same line, at least one hole is in another line located adjacent to the one line with at least two holes, and a distance between one of the holes arranged in the same line and the other hole located at the closest position from the one of the two holes arranged in the same line is longer than a distance between the holes adjacently arranged in the same line.
    Type: Grant
    Filed: February 19, 2007
    Date of Patent: March 27, 2012
    Assignee: Sony Corporation
    Inventors: Akira Akiba, Shun Mitarai
  • Publication number: 20120061348
    Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Zhong L. Wang, Christopher J. Summers, Xudong Wang, Elton D. Graugnard, Jeffrey King
  • Publication number: 20120061347
    Abstract: A method for manufacturing a printed wiring board including preparing a carrier, forming a metal layer on the carrier, forming an etching resist on the metal layer, forming a metal film from the metal layer underneath the resist by removing portion of the metal layer exposed through the resist and part of the metal layer contiguous to the portion of the metal layer and underneath the resist, forming a coating layer on side surface of the film and the carrier, forming a pad on the coating layer, removing the resist, forming a resin insulation layer on the film and surface of the pad, forming an opening reaching the surface of the pad in the insulation layer, forming a conductive circuit on the insulation layer, forming a via conductor connecting the circuit and the pad in the opening, removing the carrier from the film and coating layer, and removing the film.
    Type: Application
    Filed: October 14, 2011
    Publication date: March 15, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Satoru KAWAI, Kenji Sakai, Liyi Chen
  • Patent number: 8128993
    Abstract: Methods for forming anisotropic nanotube fabrics are disclosed. In one aspect, a nanotube application solution is rendered into a nematic state prior to its application over a substrate. In another aspect, a pump and narrow nozzle assembly are employed to realize a flow induced alignment of a plurality of individual nanotube elements as they are deposited onto a substrate element. In another aspect, nanotube adhesion promoter materials are used to form a patterned nanotube application layer, providing narrow channels over which nanotube elements will self align during an application process. Specific dip coating processes which are well suited for aiding in the creation of anisotropic nanotube fabrics are also disclosed.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: March 6, 2012
    Assignee: Nantero Inc.
    Inventors: Thomas Rueckes, Ramesh Sivarajan, Rahul Sen
  • Publication number: 20120048604
    Abstract: Glass interposer panels and methods for forming the same are described herein. The interposer panels include a glass substrate core formed from an ion-exchangeable glass. A first layer of compressive stress may extend from a first surface of the glass substrate into the thickness T of the glass substrate core to a first depth of layer D1. A second layer of compressive stress may be spaced apart from the first layer of compressive stress and extending from a second surface of the glass substrate core into the thickness T of the glass substrate core to a second depth of layer D2. A plurality of through-vias may extend through the thickness T of the glass substrate core. Each through-via is surrounded by an intermediate zone of compressive stress that extends from the first layer of compressive stress to the second layer of compressive stress adjacent to a sidewall of each through-via.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 1, 2012
    Inventors: Ivan A. Cornejo, Sinue Gomez, James Micheal Harris, Lisa Anne Moore, Sergio Tsuda
  • Patent number: 8123960
    Abstract: Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8123962
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Publication number: 20120043814
    Abstract: An integrated photovoltaic cell and battery device, a method of manufacturing the same and a photovoltaic power system incorporating the integrated photovoltaic cell and battery device. The integrated photovoltaic cell and battery device includes a photovoltaic cell, a battery, and interconnects providing three-dimensional integration of the photovoltaic cell and the battery into an integrated device for capturing and storing solar energy. Also provided is a design structure readable by a machine to simulate, design, or manufacture the above integrated photovoltaic cell and battery device.
    Type: Application
    Filed: August 18, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Fei Liu