Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.

Abstract: A method of manufacturing a liquid-discharge-head substrate is provided, which includes a plurality of elements for discharging liquid, and a heating member for heating the liquid-discharge-head substrate, the method including the steps of preparing a substrate having an insulating layer made of an insulating material provided on or above the substrate, providing a conductive layer made of a conductive material, and forming a conductive line being configured to supply current for driving the element and a part of a heating member by using the conductive layer.

Abstract: A method for fabricating an integrated circuit includes providing a substrate having thereon a material layer; forming trenches in the material layer; forming damascened wires in the trenches; covering the damascened wires and the material layer with a cap layer; forming a through hole in the cap layer that exposes a portion of the material layer; and removing the material layer thereby forming an air gap between the damascened wires.

Abstract: A structural body comprising a substrate and a structural layer formed on the substrate through an air gap in which the structural layer functions as a micro movable element is produced by a process comprising a film-deposition step of successively forming a sacrificial layer made of a silicon oxide film and the structural layer on the substrate, an air gap-forming step of removing the sacrificial layer by etching with a treating fluid to form the air gap between the substrate and the structural layer, and a cleaning step. By using a supercritical carbon dioxide fluid containing a fluorine compound, a water-soluble organic solvent and water as the treating fluid, the sacrificial layer is removed in a short period of time with a small amount of the treating fluid without any damage to the structural body.

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

Abstract: A substrate for suspension 10 comprises a metallic substrate 1, an insulating layer 2 formed on the metallic substrate 1, a conductor layer 3 formed on the insulating layer 2, and a cover layer 4 covering the conductor layer 3. The insulating layer 2 and the cover layer 4 are formed from different materials, whose coefficients of hygroscopic expansion are in the range between 3×10?6/% RH and 30×10?6/% RH. The difference between the coefficients of hygroscopic expansion of the two materials is 5×10?6/% RH or less.

Abstract: A laminated body of the present invention includes a resin layer in which a core portion composed of a fiber base member having a thickness of 25 ?m or less is embedded, the resin layer having two surfaces, and the resin layer through which at least one via-hole is adapted to be formed, and a metal layer bonded to at least one of the two surfaces of the resin layer, and the metal layer having at least one opening portion provided so as to correspond to the via-hole to be formed. Further, a method of manufacturing a substrate of the present invention includes preparing the above laminated body, forming the via-hole so as to pass through the resin layer by irradiating a laser beam onto the resin layer, and removing the metal layer from the resin layer after the via-hole is formed. Further, a substrate of the present invention is manufactured by using the above method. Furthermore, a semiconductor device of the present invention includes the above substrate, and a semiconductor element mounted on the substrate.

Abstract: There is provided a method for removing molten and scattered Cu and overhang that are generated around a via opening during laser machining in a direct laser via forming method of directly machining an outer-layer copper foil. In a manufacturing method of a printed wiring board of machining the via by laser directly through the copper foil of a copper-clad laminate in which the copper foil is clad on a base material resin, a process for machining the via is carried out in a sequence of (a) a copper foil surface treatment step of forming an oxide film on the surface of said copper foil, (b) a laser via machining step, (c) an alkali treatment step and (d) a molten and scattered Cu etching step. It is desirable to carry out (e) a de-smearing treatment after the molten and scattered Cu etching.

Abstract: A hydrogen-purification membrane comprises a Pd alloy film joined to one surface of a porous support substrate. Each pore in the porous support substrate is such that between the thickness T of the porous support substrate, the opening diameter D1 of the pore on the side joined to the Pd alloy film and the opening diameter D2 of the pore on the opposite side, there are relations represented by 1.0?D1/T?5.0 and 1.0?D2/T?5.0, and between the opening diameter D1 of the pore on the side joined to the Pd alloy film, the opening diameter D2 of the pore on the opposite side and the opening diameter D3 of the narrowest portion of the pore there are relations represented by D3/D1<0.8, D3/D2<0.9 and D3<250 ?m. Furthermore, the total opening area of the pores on the side joined to the Pd alloy film accounts for 20 to 80% of the area of the porous support substrate.

Abstract: A band filter using a film bulk acoustic resonator and a method of fabricating the same. The method includes the steps of forming a membrane layer on a substrate, forming a plurality of resonators on an upper surface of the membrane layer, depositing a mask layer on a lower surface of the membrane layer and patterning the mask layer to form a plurality of main windows and sub windows, and forming cavities along the main windows in the substrate and forming sub walls in the cavities in such a way that the sub walls are separated apart from the membrane layer by using the notch effect caused during a dry etching. It is possible to precisely form cavities with desired sizes even if the cavities have different sizes, to reduce the notched areas in the cavities, to reduce the total size of the filter by decreasing a distance between the cavities and to reduce the total length of wires.

Abstract: A microfluidic embedded nanoelectromechanical system (NEMs) force sensor provides an electrical readout. The force sensor contains a deformable member that is integrated with a strain sensor. The strain sensor converts a deformation of the deformable member into an electrical signal. A microfluidic channel encapsulates the force sensor, controls a fluidic environment around the force sensor, and improves the read out. In addition, a microfluidic embedded vacuum insulated biocalorimeter is provided. A calorimeter chamber contains a parylene membrane. Both sides of the chamber are under vacuum during measurement of a sample. A microfluidic cannel (built from parylene) is used to deliver a sample to the chamber. A thermopile, used as a thermometer is located between two layers of parylene.

Abstract: Disclosed is a method of manufacturing an inkjet printhead. The method includes: forming a chamber layer comprising a plurality of ink chambers on a substrate; forming a sacrificial layer comprising water soluble polymer on the chamber layer so as to fill the ink chambers; forming a nozzle layer comprising a plurality of nozzles on the sacrificial layer and the chamber layer; forming an ink feed hole for ink supply in the substrate; and removing the sacrificial layer. The sacrificial layer and the chamber layer may be planarized using a chemical mechanical polishing (CMP) process. The CMP process may utilize a hard polishing, in which an oil based slurry along with polishing pad of hard material to reduce the occurrences of dishing phenomenon.

Abstract: A device for measuring cellular potential includes a substrate, a first electrode tank, a first electrode, a second electrode tank and a second electrode. The first electrode tank and the second electrode tank are disposed on the upper side and lower side of the substrate, respectively. The first electrode is disposed inside the first electrode tank and the second electrode is disposed inside the second electrode tank. The substrate includes a single crystal plate having a diamond structure with (100) plane orientation or (110) plane orientation. The substrate has a first surface provided with a depression and a second surface facing this first surface. From the depression to the second surface, a through-hole is formed. The depression has an inner wall extending from the opening of the through-hole to the outer periphery, curving and being connected to the first surface.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: An electronic substrate manufacturing method includes: forming a wiring pattern on a substrate; providing a mask with an opening for the substrate on which the wiring pattern has been formed; performing a specified treatment in a part area of the wiring pattern through the opening of the mask. The opening has a size based on an accuracy of an alignment between the substrate and the mask.

Abstract: The present invention relates to a process for producing a carbon nanotube (CNT) mat (580) on a conductive or semiconductor substrate (510). According to this process, a catalytic complex (530,570) comprising at least one metal layer (570) is firstly deposited on said substrate. Said metal layer then undergoes an oxidizing treatment. Finally, carbon nanotubes are grown from the metal layer thus oxidized. The present invention also relates to a process for producing a via using said CNT mat production process.

Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract: In order to achieve low cost of manufacture of a display device by reducing the use of primary material used in a manufacturing process of a display device and saving labor taken for a vacuum process, according to the invention, liquid droplets containing conductive particles are ejected on a film being processed by using a first liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices, thereby a conductive film is formed. After that, a resist pattern is locally formed on the conductive film by using a second liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices. The conductive film is etched with the resist pattern as a mask to form a wiring.

Abstract: A method of fabricating a printed wiring board that is capable of forming a minute via hole with high accuracy is provided. This method of fabricating a printed wiring board 1 comprises: a step of forming an insulation resin layer on at least one surface side of a core wiring board; a step of forming a first resist layer on a predetermined region of a surface of the insulation resin layer; a step of forming a first metal layer with a plating method on a region of the surface of the insulation resin layer except the region where the first resist layer is formed; and a step of forming a via hole by laser machining using the first metal layer as a mask.

Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.

Abstract: A method of manufacturing a cap layer includes providing a substrate having at least a conductive layer, a base layer and a dielectric layer; forming a tensile stress cap layer on the substrate; forming a patterned hard mask layer o the tensile stress cap layer; and performing an etching process to each the tensile stress cap layer through the patterned metal hard mask layer to form at least an opening in the tensile stress cap layer.

Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film using reactive ion etching to a depth whereat said irregularity does not disappear; and sputter-etching the surface of the amorphous Si.

Abstract: A method for etching doughnut-type glass substrates, which comprises laminating a plurality of doughnut-type glass substrates each having a circular hole at its center so that the circular holes form a cylindrical hole, and applying an etching treatment to inner peripheral edge surfaces of the plurality of the laminated doughnut-type glass substrates all at once by means of an etching liquid or an etching gas, wherein the etching liquid or the etching gas is supplied from one end of the cylindrical hole, made to flow in the cylindrical hole, and discharged from the other end of the cylindrical hole so that it is not in contact with exposed main surfaces of the doughnut-type glass substrates at both ends of the laminate consisting of the doughnut-type glass substrates.

Abstract: A solid state device is formed through thin film deposition techniques which results in a self-supporting thin film layer that can have a precisely defined channel bored therethrough. The device is useful in the chacterization of polymer molecules by measuring changes in various electrical characteristics as molecules pass through the channel. To form the device, a thin film layer having various patterns of electrically conductive leads are formed on a silicon substrate. Using standard lithography techniques, a relatively large or micro-scale aperture is bored through the silicon substrate which in turn exposes a portion of the thin film layer. This process does not affect the thin film. Subsequently, a high precision material removal process is used (such as a TEM) to bore a precise nano-scale aperture through the thin film layer that coincides with the removed section of the silicon substrate.

Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.

Abstract: The present invention relates to a process of nano fabrication based on nucleated SAM growth, to patterned substrates prepared thereby, to a nano wire or grid of nanowires prepared thereby and to electronic devices including the same. In particular, there is provided a process which comprises applying a first SAM-forming molecular species to a first surface region of the substrate surface, so as to provide a first SAM defining a scaffold pattern on the first surface region; and applying a second SAM-forming molecular species to at least a second surface region of said substrate surface which is not covered by the first SAM, whereby a second replica SAM comprising the second SAM-forming molecular species selectively forms on substrate surface adjacent to at least one edge of said first SAM.

Abstract: An electromechanical resonator including a vibrating body, at least one excitation electrode, and at least one detection electrode. The vibrating body includes a first part made of a first material with a first Young's modulus and a second part made of a second material with a second Young's modulus, less than the first Young's modulus, the second part being at least partially located facing the detection electrode.

Abstract: A circuit board having high thermal conductivity comprises a substrate, a plurality of thermal conductive insulating layers, a patterned electrical conductive layer, a plurality of through-holes and a soldering layer. The substrate has an upper surface and a lower surface; the thermal conductive insulating layers are respectively formed on the upper surface and the lower surface of the substrate. The patterned electrical conductive layer is disposed on the surfaces of the thermal conductive insulating layers. The plurality of through-holes are extended through the substrate and electrically connected to the patterned electrical conductive layer, and the soldering layer is partially formed on the patterned electric conductive layer. The present invention also discloses a method for manufacturing the circuit board as above-mentioned.

Abstract: The invention discloses a method for fabricating a conductive pattern on a flexible substrate. A flexible substrate having a conductive layer thereon is provided. A protective ink is screen printed on the conductive layer, wherein a portion of the conductive layer is exposed through the protective ink. The exposed portion of the conductive layer is removed by etching using the protective ink as a mask. The protective ink is then removed, thus providing a conductive pattern with a minimum line width of not greater than 150 ?m. The invention also discloses a composition for the protective ink.

Abstract: A wiring substrate and method of forming a wiring substrate. The wiring substrate includes a base substrate, a first resin insulating layer provided on the base substrate and a laminated capacitor formed within the first resin insulating layer. The laminated capacitor includes a plurality of capacitors laminated to each other by adhesive, each capacitor including a first electrode, a second electrode opposing the first electrode and a dielectric layer interposed between the first and second electrodes. A first via conductor electrically connects the first electrodes of the plurality of capacitors to each other, and a second via conductor electrically connects the second electrodes of the plurality of capacitors to each other. A first external terminal electrically connects to the first via conductor, and a second external terminal electrically connects to the second via conductor.

Abstract: A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 sccm and 40 sccm for CHF3 and between about 10 sccm and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: Disclosed are a printed circuit board and a manufacturing method thereof. The method of manufacturing a printed circuit board in accordance with an embodiment of the present invention includes: providing a first resin layer having a first pattern on one surface thereof; forming a conductive bump, which is electrically connected to the first pattern, on one surface of the first resin layer; compressing an insulation layer and the first resin layer such that the conductive bump passes through the insulation layer; laminating a second resin layer, which has a second pattern on a surface thereof facing the insulation layer, on the insulation layer; and forming an opening by etching a part of at least one of the first resin layer and the second resin layer.

Abstract: In a current collector laminating step, a current-collector laminate unit 30 composed of current-collector materials 31 and 32 and a film material 33 is formed. Resist layers 34 having a predetermined pattern are formed on both surfaces of the current-collector laminate unit 30. An etching process is performed with the resist layers 34 used as a mask, whereby through-holes 20a and 23a are formed on the respective current-collector materials 31 and 32. The resist layers 34 are removed from the current-collector laminate unit 30. Since the etching process is performed on the plural current-collector materials 31 and 32, productivity of an electrode can be enhanced. During the application of the slurry, the film material 33 prevents the leakage of the electrode slurry. Therefore, the current-collector laminate unit 30 can be conveyed in the horizontal direction, whereby the productivity of the electrode can be enhanced.

Abstract: An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier (1) provided with an insulating layer (7) which is patterned at a front side. Conducting material in an electrode layer (4) is applied in the cavities of the patterned insulating layer and in contact with the carrier. An connection layer (5) is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.

Abstract: An interposer and a method of manufacturing the same are provided. The interposer includes a substrate and a conductor portion formed inside the substrate. At least one insulating layer is formed on the substrate and on the conductor portion. A signal wiring portion is formed inside the insulating layer or on the insulating layer. A first pad is configured to receive an electronic part, and is formed on an outermost insulating layer of the at least one insulating layer. A connection conductor is formed in the at least one insulating layer so as to electrically connect the conductor portion to the first pad.

Abstract: The method comprises the following steps: preparing a sheet having thickness of 5 ?m to a few tens of micrometers, suitable for being etched by a lithographic operation; making a mask on a face of the sheet, the mask presenting etching selectivity S of at least 5; depositing a layer of photosensitive resin on the mask; making through holes in the layer of resin by photolithography; etching through the mask via the pores in the layer of resin; and anisotropically etching through the sheet from the pores in the mask in order to make pores in the sheet having an aspect ratio greater than 5. The invention is applicable to fabricating micron and sub-micron filters.

Abstract: A substrate structure and the fabrication method thereof are provided herein. The present invention utilizes a laminate as the support of the package process and then removes the laminate after the following package steps so as to obtain a quite smooth surface for using in the internal-plane structure of the circuit board and a stacking structure that can be applied to many different types of the chip package structures.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a plurality of conductor patterns formed on a mounting surface on which an electronic component is to be mounted, wherein each of the conductor patterns is covered with a corresponding one of solder layers; and partition walls made of insulating material and formed along the conductor patterns on the mounting surface such that each of the partition walls is provided between the adjacent conductor patterns with a clearance interposed therebetween.

Abstract: The present invention relates to masks for use in mass spectrometry, in particular MALDI, tissue section analysis, comprising a plate made of or coated by an opaque material and having a thickness of less than 150 ?m, said plate comprising regularly spaced openings, wherein in the plate upper plane, the diameter D of the largest circle comprising only one opening is superior to the diameter d of a mass spectrometer, in particular a MALDI analyzer, laser beam divided by sin ?, wherein ? is the mass spectrometer, in particular a MALDI analyzer, laser beam incidence angle with respect to the sample plane. The invention also concerns processes of manufacture of the masks according to the invention, the use thereof for mass spectrometry, in particular MALDI, imaging of tissue sections, and a method for MALDI imaging of a tissue section using said masks.

Abstract: In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.

Abstract: There is disclosed a method, system, and screen for reducing solder voids on circuit boards. In an embodiment, there is provided a method of reducing solder voids on a circuit board, comprising: locating via holes provided at a conductive landing pad; and covering at least some of the via holes with a coating, whereby gases from the covered via holes are prevented from expanding and forming voids. In another embodiment, the method further comprises covering the location of at least some of the via holes in a pattern of strips, whereby more of the via holes may be covered by the coating while reducing areas of the conductive landing pad covered by the coating. In another embodiment, the coating and removal process may be performed at the same time as when all other areas of the circuit board are coated and removed, such that a separate manufacturing step is not required.

Abstract: A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Abstract: A micro cell fuel cell using a nano porous structure according to a thin film process and an anodizing process as a template for implementing a porous structure of an electrode, its fabrication method, and a micro fuel cell stack using the same are disclosed. The micro-fuel cell includes a solid electrolyte and first and second electrodes separately formed on the electrolyte, wherein at least one of the first and second electrodes is supported by a template having a plurality of nano pores formed by depositing, anodizing and etching a thin film, and is a porous electrode with nano pores formed at positions corresponding to the entirety or a portion of the plurality of nano pores formed on the template. The micro-fuel cell can be fabricated based on the thin film process, and unit cells can be highly integrated to implement a micro-fuel cell system generating a high voltage and a high current.

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.