Abstract: Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: Methods for fabricating sublithographic, nanoscale polymeric microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: In a method for manufacturing a printed circuit board, a substrate, including a number of plated through holes (PTHs) is provided. Each of the PTHs has an electrically conductive layer plated on its inner wall and includes an electrically connecting portion and a stub. A protective layer is formed on a surface of the substrate adjacent to the stub. An etching device, including an upper plate and a number of spray tubes corresponding to the PTHs, is provided. Each of the spray tubes includes a protruding portion beyond the upper plate. The substrate is arranged in such a manner that the protective layer is in contact with the upper plate and the protruding portions are received in the stubs. After that, the protruding portions spray an etchant to etch and remove the electrically conductive layer of the stubs, and the protective layer is removed.

Abstract: Provided are a meta material and a method of manufacturing the same. The meta material comprises: a substrate; at least one conductive nano pattern patterned on the substrate and having a size with a negative refractive index in a predetermined electromagnetic wavelength band; and a dielectric layer covering the conductive nano patterns.

Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. The metal oxide structures and patterns may be used, for example, as a mask for sublithographic patterning during various stages of semiconductor device fabrication. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface.

Abstract: A TAMR (Thermal Assisted Magnetic Recording) write head uses the energy of optical-laser generated plasmons in a magnetic core plasmon antenna to locally heat a magnetic recording medium and reduce its coercivity and magnetic anisotropy. To enable the TAMR head to operate most effectively, the maximum gradient and value of the magnetic recording field should be at a point of the magnetic medium that is as close as possible to the point being heated. In addition, the coupling between the optical mode and the plasmon mode should be efficient so that maximum energy is transmitted to the medium. The present invention achieves both these objects by surrounding the magnetic core of a plasmon antenna by a variable thickness plasmon generating layer, whose thinnest and shortest portion is at the ABS end of the TAMR head and whose thickest and longest portion efficiently couples to the optical mode of a waveguide to produce a plasmon.

Abstract: Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

Abstract: A method for forming a minute pattern includes depositing a material layer on a semiconductor substrate having a conductive region, forming a first mask layer on the material layer, forming a recess region in the first mask layer, performing layer processing to form a first mask pattern in the recess region, and etching the material layer to form a material layer pattern.

Abstract: Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multilayer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.

Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

Abstract: A method of manufacturing a mounting substrate, the method including: providing an insulation layer, the insulation layer having a circuit pattern formed in one side thereof; forming at least one bonding pad in the other side of the insulation layer, the bonding pad electrically connected with the circuit pattern; and etching the bonding pad such that a surface of the bonding pad is recessed from a surface of the insulation layer by a predetermined depth.

Abstract: A method for forming a nanofluidic channel measuring system is disclosed. The method includes forming a first trench in a substrate, forming a second trench in the substrate, the first trench and the second trench are separated by a first width, providing a first conductor pad at a first location, providing a second conductor pad at a second location, forming a first nano-wire for coupling the first conductor pad with the second conductor pad, and forming a nano-channel through the first nano-wire, the nano-channel also coupling the first trench and the second trench, the nano-channel configured to sever the first nano-wire. A nanofluidic channel measuring system is also disclosed.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20?) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30?) of a first aspect ratio containing first conductors (36, 36?) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22?) from the rear surface (22) to form a modified wafer (20?) of smaller final thickness (21?) with a new rear surface (22?), and (iii) forming from the new rear surface (22?), much deeper vias (40, 40?) of second aspect ratios beneath the device region (26) with second conductors (56, 56?) therein contacting the first conductors (36, 36?), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area.

Abstract: A method for manufacturing a multilayer printed wiring board which enables the dielectric layers to have excellent thickness uniformity, the capacitor circuits to have high registration accuracy and the unnecessary dielectric layer is removed as large as possible; and a multilayer printed wiring board with an embedded capacitor circuit manufactured by the method.

Abstract: Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate.

Abstract: A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.

Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer a fuel cell so as to be capable of stably producing high purity hydrogen gas.

Abstract: A piezoelectric-driven MEMS device can be fabricated reliably and consistently. The piezoelectric-driven MEMS device includes: a movable flat beam having a piezoelectric film disposed above a substrate with a recessed portion such that the piezoelectric film is bridged over the recessed portion, piezoelectric drive mechanisms disposed at both ends of the piezoelectric film and configured to drive the piezoelectric film, and a first electrode disposed at the center of the substrate-side of the piezoelectric film, and a second electrode disposed on a flat part of the recessed portion of the substrate and facing the first electrode of the movable flat beam.

Abstract: The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.

Abstract: A microstructure includes a substrate, a fixed supporting portion fixed to the substrate, a first movable portion, a second movable portion enhancing the rigidity of the first movable portion, and an elastic supporting portion elastically interconnecting the first movable portion and the fixed supporting portion. The second movable portion is secured to the first movable portion with a gap interposed therebetween and in such a manner as to cover the elastic supporting portion and the fixed supporting portion. The first movable portion and the second movable portion are elastically supported by the elastic supporting portion in such a manner as to be displaceable together relative to the fixed supporting portion.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.

Abstract: A method for manufacturing printed circuit board includes steps below. A first electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface is provided. A number of first traces directly formed on the second surface. A first insulating layer is formed on the second surface of the first electrically conductive layer and the surface of the first traces. The electrically conductive layer is etched to form a number of second traces, the second traces superpose the first traces, the first traces and the second traces constitute a circuit pattern.

Abstract: A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.

Abstract: A traveling wave device includes a slow wave circuit supported by a dielectric membrane. The dielectric membrane can have a thickness substantially smaller than a wavelength of operation of the traveling wave device.

Abstract: A method of forming a sensor with an embedded cavity can include forming at least one cavity (50) in a substrate (52). The cavity (50) can include at least one membrane wall (54) having a plurality of holes (64) in the membrane wall (54), the plurality of holes (64) being formed in a two-dimensional array. A piezoresistive system (58) can be mechanically associated with the membrane wall (54). The method can be a front-side or back-side process for forming the cavity (50). The membrane (54) simultaneously acts as a diaphragm and a fluid passage into the cavity (50). Such sensors can be suitable as pressure sensors, chemical sensors, flow sensors and the like.

Abstract: The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.

Abstract: The invention relates to a method for producing a slotted guide, in which: a) a layer of a material having a refractive index less than that of silicon, for example Material having a refractive index less than that of silicon (26), is formed on an etching barrier layer (22), b) two parallel trenches are etched into said material having a refractive index less than that of silicon, with the etching barrier on said etching barrier layer, these two trenches being separated by a wall of said material having a refractive index less than that of silicon (36), c) the trenches thus made are filled with silicon (42, 44).

Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

Abstract: A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

Abstract: An integrated conductor/suspension structure for supporting and electrically connecting a write/read head in a hard disk drive and methods of making the conductor/suspension structure are provided. The integrated conductor/suspension structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The suspension structure includes apertures formed therein that result in a reduction in the lossy material and its effect on the electrical signals. In addition, the conductor/suspension structure of the present invention provides shielding to reduce the interference from external electric fields.

Abstract: A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method.

Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.

Abstract: A method and apparatus of imprint lithography wherein the method includes depositing a material on a patterned surface of a conductive substrate, and pressing a transparent substrate and the conductive substrate together, wherein the pressing causes the material to conform to the patterned surface. Energy is applied to the material to form patterned material from the material. The transparent substrate and the conductive substrate are separated, wherein the patterned material adheres to the transparent substrate.

Abstract: A circuit board and a method of manufacturing the circuit board are provided. The method includes forming at least one protruded bump on a first side of a conductive board, forming a dielectric layer on the first side of the conductive board where the at least one bump is formed so as to cover the at least one bump; and etching a second side of the conductive board so as to partially remove the board to form a pattern.

Abstract: A method for forming a bump of a probe card is disclosed. In accordance with the method, a bump having a high aspect ratio for supporting a probe tip and a probe beam is formed using a semiconductor substrate as a mold eliminating a need for a photoresist film.

Abstract: The present invention is to provide a printed wiring board having a fine wiring formed on a resin base material by the semi-additive method, and is also to provide an electroless copper plating method capable of producing the printed wiring board, a method for producing a printed wiring board using the electroless copper plating method, a printed wiring board produced by the production method, and a semiconductor device provided with the printed wiring board. An electroless copper plating method comprising the step of performing acid treatment before an electroless copper plating step including cleaner, providing palladium catalyst, palladium reduction, and electroless copper plating process, a method for producing a printed wiring board using the electroless copper plating method, a printed wiring board produced by the method for producing the printed wiring board, and a semiconductor device provided with the printed wiring board.

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract: A fabrication method of an electronic device is provided. First, a substrate is provided. Then, a patterned amorphous carbon (?-C) layer is formed on the substrate and exposes part of the substrate. Next, a first ?-C layer covering the patterned ?-C layer and part of the substrate is formed. Then, part of the substrate and part of the first ?-C layer covering part of the substrate are removed, so as to form a patterned substrate and a second ?-C layer.

Abstract: Methods for manufacturing a gas electron multiplier. One method comprises a step of preparing a blank sheet comprised of an insulating sheet with first and second metal layers on its surface, a first metal layer hole forming step in which the first metal layer is patterned by means of photolithography, such as to form holes through the first metal layer, an insulating sheet hole forming step, in which the holes formed in the first metal layer are extended through the insulating layer by etching from the first surface side only, and a second metal layer hole forming step, in which the holes are extended through the second metal layer. Alternatively, the second metal layer hole forming step is performed by electrochemical etching, such that the first metal layer remains unaffected during etching of the second metal layer.

Abstract: Disclosed is a method of manufacturing a printed circuit board, including (A) forming a first circuit layer on a base substrate and forming a first insulating layer thereon, (B) forming trenches including dummy trenches and wiring trenches on the first insulating layer and plating the trenches, thus providing a trench circuit layer including a dummy circuit pattern and a wiring circuit pattern, (C) removing the dummy circuit pattern of the trench circuit layer, and (D) forming a second insulating layer on the trench circuit layer from which the dummy circuit pattern was removed. The method reduces deviation of plating thickness and thus realizes the design density of a trench circuit layer.

Abstract: A method for manufacturing an appearance-modifying device (2, 6, 9; 10; 30), for modifying the visual appearance of a surface covered thereby is disclosed. The method comprises the steps of: providing a first substrate (11) having, on a first side thereof, a first electrode layer (17) covered by a dielectric layer (21); providing a second substrate (12) opposite the first side of the first substrate (11); arranging a spacer structure (13) between the first (11) and second (12) substrates to form a plurality of-cells (15, 16; 31) in such a way that an area occupied by each cell includes a portion of the first electrode layer (17); providing a second electrode (18) spaced apart from the first electrode layer (17) at least by the dielectric layer (21), forming, in each of the cells (15, 16; 31), a recess in the dielectric layer (21); and providing, in each of the cells(15, 16; 31), an optically transparent fluid (19) having a plurality of particles (20) dispersed therein.

Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or more address wires that overlays the first layer. The nanoscale device may also include an intermediate layer positioned between the first layer and the second layer. Two or more redundant electrical component patterns may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.

Abstract: A manufacturing method for a micromechanical component having the following steps: at least partially covering a first side of a substrate using a first insulating layer, forming at least one actuator plate electrode, at least one contact terminal, and at least one spring component from at least one first conductive material, covering at least the at least one actuator plate electrode, the at least one contact terminal, and the at least one spring component using a second insulating layer, forming at least one stator plate electrode from at least one second conductive material, forming at least one first trench in the substrate for producing a displaceable mass and a frame of a mounting, etching being performed in a first direction, and removing at least one partial mass of the second insulating layer, which is between the at least one actuator plate electrode and the at least one stator plate electrode, etching being performed in a second direction. Also described is a related micromechanical component.

Abstract: Disclosed herein is a printed circuit board, including: a base substrate; insulation layers which are formed on both sides of the base substrate and in which trenches are formed; and circuit layers including circuit patterns and vias formed in the trenches using a plating process. The printed circuit board is advantageous in that trenches are formed in both sides of a base substrate, so that a fine circuit pattern can be simultaneously formed on both sides thereof, thereby simplifying the manufacturing process thereof.

Abstract: Provided are an apparatus for generating/detecting terahertz wave and a method of manufacturing the same. The apparatus includes a substrate, a photo conductive layer, a first electrode and a second electrode, and a lens. The photo conductive layer is formed on an entire surface of the substrate. The first electrode and a second electrode are formed on the photo conductive layer. The first and second electrodes are spaced from each other by a certain gap. The lens is formed on the first and second electrodes. The lens is filled in the gap between the first and second electrodes.

Abstract: An inkjet head having an electrostatic actuator and a manufacturing method of the same are disclosed. The inkjet head having an electrostatic actuator, comprising a stator, on which is formed a plurality of comb pattern shaped first protrusion parts and second protrusion parts in both directions, and a rotor consisting of a first component and a second component, the ends of which join with the diaphragm, wherein a third protrusion part is formed on the first component, facing the first protrusion parts and meshing with the first protrusion parts without contact; and a fourth protrusion part is formed on the second component, facing the second protrusion parts and meshing with the second protrusion parts without contact, may decrease the size of the head composition and may increase the electrostatic force so that a large displacement may be obtained with little voltage to increase the ink discharge pressure.

Abstract: A Twisted Nematic Liquid Crystal Display (TN-LCD for short below) with fast response time includes polarizer, glass substrates, indium tin oxide (ITO) electrodes, alignment layers, liquid crystal material, sealing material, spacers. The TN-LCD employs a method of improving its response time that can improve color saturation of the field sequential LCD or the response time of the optical shutter.

Abstract: A device for controlling the flow of electric current is provided. The device comprises a first conductor as thin film form; a second conductor switchably coupled to the first conductor to alternate between an electrically connected state with the first conductor and an electrically disconnected state with the first conductor. At least one conductor further comprises an electrical contact, the electrical contact comprising a solid matrix comprising a plurality of pores; and a filler material disposed within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575 K. A method to make an electrical contact is provided. The method includes the steps of: providing a substrate; providing a plurality of pores on the substrate; and disposing a filler material within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575 K.

Abstract: In a method of forming patterns of a semiconductor device, a to-be-etched layer is formed on a semiconductor substrate. First etch mask patterns are formed over the to-be-etched layer. An auxiliary layer is formed on the first etch mask patterns and the to-be-etched layer. The auxiliary layer is thicker on upper sidewalls of the first etch mask patterns than on lower sidewalls thereof. Second etch mask patterns are formed in concave portions of the auxiliary layer. The auxiliary layer between the first and second etch mask patterns is removed. The to-be-etched layer is patterned using the first and second etch mask patterns as an etch mask.