Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
  • Publication number: 20090159559
    Abstract: A method for manufacturing a multilayer printed circuit board includes the following steps. A number of laminate units are provided. Each of the laminate units includes an electrically conductive layer with a circuit pattern defined therein, and a release layer releasably attached to the electrically conductive layer. A number of insulation layers are provided. Each of the insulation layers definies a metalized through hole therein. The electrically conductive layers and the insulation layers are stacked alternately one on another such that adjacent electrically conductive layers are insulated by one insulation layer and the metalized through holes electrically connects the circuit patterns of the adjacent electrically conductive layers. In the stacking step, the release layer is removed from the laminate unit after the electrically conductive layer is stacked onto the respective insulation layer, thereby obtaining a pre-laminated multilayer printed circuit board.
    Type: Application
    Filed: June 30, 2008
    Publication date: June 25, 2009
    Applicants: FUKUI PRECISION COMPONENT (SHENZHEN) CO., LTD., FOXCONN ADVANCED TECHNOLOGY INC.
    Inventors: YUN-LI ZHU, YUNG-WEI LAI, SHING-TZA LIOU
  • Publication number: 20090145652
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Application
    Filed: September 26, 2008
    Publication date: June 11, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 7544304
    Abstract: A process for laser forming a blind via in at least one layer of a circuit substrate having a plurality of capture pads of varying geometry can include, for at least one blind via to be formed in at least one layer of a circuit substrate, evaluating a capture pad geometry value (such as area and/or volume) within a predetermined distance from a drilling location with respect to a blind via geometry value (such as area and/or volume) to be formed at the drilling location. The process can include setting at least one laser operating parameter based on the evaluation in order to obtain a desired capture pad appearance after blind via formation. The process can include imaging a capture pad area defined as an area within a predetermined distance from a blind via drilling location in at least one layer of a circuit substrate, quantifying at least one appearance value for the imaged capture pad area, and determining an acceptability of the imaged capture pad areas based on the quantified appearance value.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: June 9, 2009
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Hisashi Matsumoto, Mark Singer, Leo Baldwin, Jeffrey E. Howerton, David V. Childers
  • Publication number: 20090139328
    Abstract: A method is provided for making packaged micro-devices each including a micro movable element, a first packaging member formed with a recess, and a second packaging member formed with another recess. The micro movable element has a movable part. In accordance with the method, a device wafer is prepared for forming a plurality of micromovable elements. A first packaging wafer, formed with a plurality of recesses corresponding in position to the movable parts of the respective movable elements, is bonded to one surface of the device wafer. A second packaging wafer, formed with a plurality of recesses, is bonded to the other surface of the device wafer. The resulting laminate assembly is cut into separate products.
    Type: Application
    Filed: February 27, 2008
    Publication date: June 4, 2009
    Applicants: FUJITSU LIMITED, FUJITSU MEDIA DEVICES LIMITED
    Inventors: Hiroaki Inoue, Fumihiko Nakazawa, Hiroshi Ishikawa, Takashi Katsuki, Takayuki Yamaji
  • Patent number: 7541286
    Abstract: A semiconductor device manufacturing method using a KrF light source is disclosed. Embodiments relate to a method for manufacturing a semiconductor device including forming an oxide film over a semiconductor substrate. A gate conductor may be formed over the oxide film. An antireflective film may be formed over the gate conductor. A photoresist film may be formed over the antireflective film. The photoresist film may be photo-etched, thereby forming a first photoresist film pattern having a first line width. The antireflective film may be etched, using the first photoresist film pattern as a mask, thereby forming an antireflective film pattern. The first photoresist film pattern may be simultaneously laterally etched, thereby forming a second photoresist film pattern having a second line width corresponding to a final design value for the gate conductor.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chang-Myung Lee
  • Patent number: 7540969
    Abstract: A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 2, 2009
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chung W. Ho, Leo Shen
  • Patent number: 7540968
    Abstract: A micro movable device includes a base substrate, a fixed portion bonded to the base substrate, a movable portion having a fixed end connected to the fixed portion and extending along the base substrate, and a piezoelectric drive provided on the movable portion and the fixed portion on a side opposite to the base substrate. The piezoelectric drive has a laminate structure provided by a first electrode film contacting the movable portion and the fixed portion, a second electrode film and a piezoelectric film between the first and the second electrode films. At least one of the movable portion and the fixed portion is provided with a groove extending along the piezoelectric drive.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: June 2, 2009
    Assignee: Fujitsu Limited
    Inventors: Anh Tuan Nguyen, Tadashi Nakatani, Takeaki Shimanouchi, Masahiko Imai, Satoshi Ueda
  • Publication number: 20090133910
    Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 ?m or below.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 28, 2009
    Applicants: AJINOMOTO CO., INC, SHINKO ELECTRIC INDUSTRIES CO.,LTD.
    Inventors: Seiichiro OHASHI, Eiichi Hayashi, Shigeo Nakamura, Takaaki Yazawa, Junichi Nakamura
  • Publication number: 20090133918
    Abstract: In one embodiment of the present invention, a connecting device of a double-sided wiring board includes a first-side connecting land portion configured by a first-side conductive layer and a first-side connecting conductive layer and a second-side connecting land portion configured by a second-side conductive layer; the first-side connecting land portion and the second-side connecting land portion face each other at respective central portions with an insulating substrate sandwiched therebetween; a substrate hole is formed corresponding to a peripheral end portion of the first-side connecting land portion and a peripheral end portion of the second-side connecting land portion; and the peripheral end portion of the first-side connecting land portion and the peripheral end portion of the second-side connecting land portion are connected to each other via the substrate hole.
    Type: Application
    Filed: August 18, 2008
    Publication date: May 28, 2009
    Inventor: Hitoshi KASHIO
  • Patent number: 7534361
    Abstract: The present invention relates to a circuit board including a flexible film provided with an extremely fine circuit pattern, a laminated member for a circuit board, and a method for making a laminated member for a circuit board with excellent productivity. A circuit board of the present invention includes a flexible film and a circuit pattern composed of a metal provided on the flexible film, and dimensional change rate of the circuit pattern is within ±0.01%. A laminated member for a circuit board of the present invention includes a reinforcing plate, a self-stick, removable organic layer, a flexible film, and a circuit pattern composed of a metal laminated in that order.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: May 19, 2009
    Assignee: Toray Industries, Inc.
    Inventors: Takayoshi Akamatsu, Futoshi Okuyama, Nobuyuki Kuroki, Hiroshi Enomoto, Tetsuya Hayashi, Yoshio Matsuda, Yoichi Shinba, Masahiro Oguni
  • Patent number: 7531100
    Abstract: A method of making a fuel cell component using a mask, which is removed after further processing to yield a surface with variable properties.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: May 12, 2009
    Assignee: GM Global Technology Operations, Inc.
    Inventors: Scott L Peters, Thomas A. Trabold, Gayatri Vyas, Reena L. Datta, Jeffrey M Guzda
  • Publication number: 20090107844
    Abstract: Embodiments of the present invention may provide a microchip applicable to an electrophoresis employing UV detection and a method of manufacturing the same. The microchip of the present invention has a glass channel plate, which is formed on an upper surface thereof with a loading channel and a separation channel and is provided on the upper surface thereof with an optical slit layer made of silicon except the channel region, and a glass reservoir plate, which is formed with sample solution reservoirs and buffer solution reservoirs. The loading channel and the separation channel are formed on the channel plate by deep reactive ion etching. The sample solution reservoirs and the buffer solution reservoirs are formed in the reservoir plate by sand blasting. The channel plate and the reservoir plate are combined by anodic bonding the optical slit layer and the reservoir plate. Electrodes for sample and electrodes for buffer are deposited by sputtering Pt with a shadow mask after anodic bonding.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Inventors: Myung-Suk Chun, Tae Ha Kim
  • Patent number: 7524429
    Abstract: The present invention provides a method of manufacturing a double-sided printed circuit board. An insulation substrate is first formed by creating a plurality of through holes on a Copper Clad Laminate (CCL) whose copper foil surface has been removed. Next, an electro-less copper layer is plated on the substrate for forming a plurality of plated through holes. After a wire pattern is formed on the substrate, a solder preventive layer is formed on top of the wire pattern. Next, a plurality of openings is created in between the solder preventive layer for exposing the contact pads. Finally, a protective layer is plated on top of the contact pads.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: April 28, 2009
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Hung-En Hsu, Binwei Wang, Shing-Fun Ho
  • Publication number: 20090102512
    Abstract: An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be changed to a second permanent logic state by modifying any one of the metal and via masks that are used to form the metal interconnect structure.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Inventor: Richard J. Doyon JR.
  • Publication number: 20090098030
    Abstract: The invention relates to a microreactor having a substrate (10, 20, 80) with at least one catalytically active material arranged in and/or on a cavity structure (14, 24, 84). The substrate (10, 20, 80) has a first layer (11, 21, 80) and optionally at least one additional layer (12, 22) of a ceramic material, with the first layer (11, 21, 80) being formed from a first component of a crystalline ceramic material and/or a glass material as the matrix and a second component of an additional crystalline ceramic material. The surface areas of the crystals and/or crystal agglomerates of the second component in the first layer (11, 21, 80) are etched out in at least some areas to form the cavity structure (14, 24, 84).
    Type: Application
    Filed: September 15, 2008
    Publication date: April 16, 2009
    Inventors: Dieter Schwanke, Mirco Harnack, Achim Bittner, Ulrich Schmid
  • Publication number: 20090090548
    Abstract: A circuit board is disclosed, including a core board, wherein at least one surface thereof has a core circuit layer with a plurality of conductive lands; a first dielectric layer disposed on the core board and disposed with a plurality of openings for exposing the conductive lands; a first coupling layer disposed on the first dielectric layer, the first coupling layer having a plurality of openings disposed corresponding to the openings of the first dielectric layer; and a first circuit layer disposed on the first coupling layer and a plurality of first conductive vias disposed in the openings of the first coupling layer for electrically connecting to the conductive lands of the core circuit layer. By the formation of the first coupling layer that connects the first circuit layer and the first dielectric layer, the bond strength between the first circuit layer and the first dielectric layer is enhanced, thereby preventing detachment and delamination as encountered in the prior art.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 9, 2009
    Applicant: Phoenix Precision Technology Corporation
    Inventors: Chao-Wen Shih, Ya-Lun Yen
  • Publication number: 20090072214
    Abstract: A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed on the phase-change material layer and fills the first opening.
    Type: Application
    Filed: November 24, 2008
    Publication date: March 19, 2009
    Applicant: International Business Machines Corporation
    Inventors: Jonathan Zanhung Sun, Simone Raoux, Hemantha Wickramasinghe
  • Publication number: 20090071934
    Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.
    Type: Application
    Filed: July 31, 2008
    Publication date: March 19, 2009
    Inventors: Sang-moo Choi, Jung-hun Sung, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park
  • Publication number: 20090057146
    Abstract: An analyte, system, strip and method are described. In one example, an analyte test strip is provided that includes a substrate, electrically conductive material and an isolated portion of the electrically conductive material. The substrate has a generally planar surface that extends from a first end to a second end. The electrically conductive material is disposed on the generally planar surface to define a plurality of electrodes spaced apart from each other. The isolated portion of the electrically conductive material is disposed between at least two electrodes so that the isolated portion is not in electrical communication with the plurality of electrodes.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 5, 2009
    Applicant: LifeScan, Inc.
    Inventors: Maria Teodorczyk, Remedios Dato, Koon-wah Leong
  • Patent number: 7497960
    Abstract: A method for manufacturing a filter is provided which can easily manufacture the filter that has both excellent anti-corrosion properties and anti-abrasion properties. In the method, a first substrate is produced that has a plurality of holes, a ceramic layer will be formed by depositing extremely small particles of ceramic material on one side of the first substrate, and a filter having a plurality of holes will be obtained. The manufactured filter is composed of ceramic material, and has excellent anti-abrasion and anti-corrosion properties.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 3, 2009
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroto Sugahara
  • Patent number: 7497959
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: March 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt
  • Publication number: 20090050602
    Abstract: A method for forming holes in making a printed circuit board includes the step of: providing a copper clad laminate including an insulation layer and a copper layer laminated on the insulation layer; forming a carbon nano-material on the copper layer of the copper clad laminate; and applying a laser beam onto a portion of the carbon nano-material to define a hole in the copper clad laminate beneath the portion of the carbon nano-material.
    Type: Application
    Filed: June 9, 2008
    Publication date: February 26, 2009
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-HSIEN LIN, WEN-CHIN LEE, KAI-LI JIANG
  • Publication number: 20090040704
    Abstract: A printed circuit board includes a core layer, an insulation layer formed on the core layer and having a cavity formed on a part of the insulation layer, and a circuit pattern formed on the insulation layer, wherein the circuit pattern comprises one or more external terminals positioned above the cavity.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 12, 2009
    Inventors: Ho-Seong Seo, Young-Min Lee, Kyu-Sub Kwak
  • Patent number: 7488428
    Abstract: A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: February 10, 2009
    Assignee: Foxconn Advanced Technology Inc.
    Inventors: Wen-Chin Lee, Cheng-Hsien Lin
  • Publication number: 20090032493
    Abstract: A method for manufacturing a predetermined pattern is generally used to manufacture a predetermined pattern on PCBs. The method comprises a step of etching an insulating substrate of the PCB with a laser beam instead of chemical solutions to produce the predetermined pattern according to the layout of the predetermined patterns. The method may further comprise a step of applying metallization treatment on the predetermined pattern, thereby forming a desired trace. The laser etching has the advantages such as high precision and no chemical wastewater. The laser etching also overcomes the disadvantages of conventional manufacturing methods, such as uneven thickness and imprecision.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 5, 2009
    Inventor: Tsung Kuei Chang
  • Publication number: 20090026168
    Abstract: A method for manufacturing a rigid-flex board is disclosed. After the formation of each layer of the rigid-flex board, a laser-etched groove is formed at the interface between a rigid part and a bending area of the rigid-flex board. After the laser etching process, a circuit-board routing process is performed to remove materials along the sideward perimeter of the bending area. The exposed copper layer is then removed from inside the laser-etched groove. Thereafter, a redundancy rigid structure within the bending area is readily removed to expose the flex board within the bending area.
    Type: Application
    Filed: December 17, 2007
    Publication date: January 29, 2009
    Inventors: Tzong-Woei Tsai, Yu-Lun Lin, Hung-En Hsu
  • Publication number: 20090029500
    Abstract: An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.
    Type: Application
    Filed: June 8, 2008
    Publication date: January 29, 2009
    Inventor: Chang-Feng Wan
  • Publication number: 20090020501
    Abstract: A method of forming a passage in a substrate for a MEMS module is disclosed to include the steps of respectively forming a first support layer and a second support layer in a first space and a second space, which are respectively formed in a bottom side and a top side of a substrate by etching, by injection molding to define a sacrifice portion between the first and second support layers, and removing the sacrifice portion from the substrate by etching to form a passage defined between the first support layer and the second support layer in the substrate with two ends in communication with ambient atmosphere.
    Type: Application
    Filed: November 6, 2007
    Publication date: January 22, 2009
    Applicant: Lingsen Precision Industries
    Inventors: Chiung-Yueh TIEN, Hsi-Chen YANG
  • Publication number: 20090014410
    Abstract: A producing method of a suspension board with circuit includes simultaneously forming a conductive pattern formed on an insulating layer formed on a metal supporting board and having a terminal portion for connecting to an electronic component, and a mark formed on the metal supporting board, or on the insulating layer and having an opening for forming a reference hole for mounting the electronic component, and forming the reference hole by etching the metal supporting board disposed in the opening of the mark, or the insulating layer and the metal supporting board each disposed in the opening of the mark.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: Nitto Denko Corporation
    Inventors: Takahiko Yokai, Yasunari Ooyabu, Toshiki Naito
  • Publication number: 20090017305
    Abstract: A method for producing integrated microelectromechanical components is provided, whereby a first conductive layer is produced on a first insulating layer, the first conductive layer is structured, a second insulating layer is produced, a second conductive layer is produced, at least one etch opening is produced for at least partial etching of the second insulating layer beneath the second conductive layer in order to produce at least one hollow space, and at least a part of the first conductive layer and the second conductive layer is electrically contacted.
    Type: Application
    Filed: July 28, 2008
    Publication date: January 15, 2009
    Inventors: Franz Dietz, Alida Wuertz
  • Publication number: 20090009200
    Abstract: A method for aligning a probe relative to a Supporting substrate defining a first planar surface, an edge, and a first crystal plane includes the steps of masking the surface of the substrate to define an exposed area on the first surface at the edge; and etching, using an etch reagent, a recess in the exposed area, the recess defining first and second opposed sidewalls, an end wall remote from the edge, and a bottom wall. The method further includes the step of providing a probe substrate defining a second planar surface and a second crystal plane identical to the first crystal plane, and positioning the probe substrate so that the first and the second crystal planes are positioned identically when forming a probe from the probe substrate using the etch reagent, wherein the probe defines congruent surfaces to the first and second sidewalls.
    Type: Application
    Filed: June 21, 2005
    Publication date: January 8, 2009
    Applicant: Capres A/S
    Inventors: Peter Folmer Nielsen, Peter R.E. Petersen, Jesper Erdman Hansen
  • Publication number: 20090007681
    Abstract: A gauge pressure sensor apparatus and a method of forming the same. A constraint wafer can be partially etched to set the diaphragm size, followed by bonding to a top wafer. The thickness of the top wafer is either the desired diaphragm thickness or is thinned to the desired thickness after bonding. The bonding of top wafer and constraint wafer enables electrochemical etch stopping. This allows the media conduit to be etched through the back of the constraint wafer and an electrical signal produced when the etching reaches the diaphragm. The process prevents the diaphragm from being over-etched. The invention allows the die size to be smaller than die where the diaphragm size is set by etching from the back side.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Inventors: Carl E. Stewart, Gilberto Morales, Richard A. Davis
  • Publication number: 20080314866
    Abstract: Described herein are systems, devices, and methods relating to packaging electronic devices, for example, microelectromechanical systems (MEMS) devices, including optical modulators such as interferometric optical modulators. The interferometric modulator disclosed herein comprises a movable mirror. Some embodiments of the disclosed movable mirror exhibit a combination of improved properties compared to known mirrors, including reduced moving mass, improved mechanical properties, and reduced etch times.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 25, 2008
    Applicant: IDC, LLC.
    Inventors: Clarence Chui, Jeffrey B. Sampsell
  • Publication number: 20080314865
    Abstract: A method for fabricating the hermetic electrical feedthrough. The method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thickfilm paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.
    Type: Application
    Filed: October 25, 2007
    Publication date: December 25, 2008
    Inventors: Jerry Ok, Robert J. Greenberg
  • Publication number: 20080302760
    Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.
    Type: Application
    Filed: April 30, 2008
    Publication date: December 11, 2008
    Inventors: Dong-Gun Park, Dong-Won Kim, Sung-Young Lee, Yang-Kyu Choi, Chang-Hoon Kim, Ju-Hyun Kim
  • Publication number: 20080296736
    Abstract: A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Qian Fu, Shenjian Liu, Wonchul Lee, Bryan Pu
  • Publication number: 20080277375
    Abstract: A method for manufacturing a flexible electrophoretic display device, including: providing a metal mother substrate having a first thickness, including a unit display panel region and a non-display region adjacent the unit display panel region; forming a display element in the unit display panel region; forming a groove in the non-display region of the mother substrate; cutting the mother substrate along the groove to separate the unit display panel region from the mother substrate; thinning the substrate of the separated unit display panel region; and forming an electrophoretic film on the unit display panel region.
    Type: Application
    Filed: October 31, 2007
    Publication date: November 13, 2008
    Inventors: Seung Han Paek, Kyoung Mook Lee, Sung Hwan Kim, Su Ho Kim
  • Publication number: 20080280099
    Abstract: Silicon grids with electron-transparent SiO2 windows for use as substrates for high-resolution transmission electron microscopy of chemically-modified SiO2 surfaces are fabricated by forming an oxide layer on a silicon substrate. An aperture is defined in the silicon substrate by etching the substrate to the oxide layer. A single substrate can include a plurality of apertures that are in respective frame regions that are defined by one or more channels in the substrate. Tabs are provided to secure the frame regions to the substrate, and the tabs are readily broken to obtain a particular frame region. Conductive or other features can be defined on the oxide layers prior to separation of the frame regions from the substrate.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 13, 2008
    Inventors: James E. Hutchison, Gregory J. Kearns
  • Patent number: 7442318
    Abstract: A method of manufacturing a thermal print head includes a conductor layer formation step, a first measurement step, a conductor layer splitting step and a second measurement step. In the conductor layer formation step, a single conductor layer including first and second measurement points is formed on a substrate. In the first measurement step, the electrical resistance is measured in the conductor layer, between the first and the second measurement points. In the conductor layer splitting step, a predetermined portion of the conductor layer is removed, so that a first electrode including the first measurement point and a second electrode including the second measurement point are formed. In the second measurement step, the resistance between the first and the second electrodes is measured. If the conductor layer has a disconnected portion in the first measurement step, a repairing conductor is formed on the disconnected portion.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: October 28, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Masaya Yamamoto, Shinobu Obata
  • Publication number: 20080251496
    Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 16, 2008
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Hideki Yonekura, Tadashi Kodaira
  • Patent number: 7431860
    Abstract: A method for etching a pattern in a material in precise target areas comprising depositing selectively onto the material droplets of a substance for dissolving or reacting chemically with the material. Droplets may be deposited from a print head of the type having a nozzle from which the material may be ejected as a series of droplets, such as an ink jet print head. In a preferred application, a series of ridges can be etched from an organic insulator layer overlying a photoemissive organic polymer. A conductive layer is then deposited and the ridges of organic insulator are dissolved by solvent washing to provide an array of conductive stripes which can be used as a cathode for an electroluminescent display device. In combination, both anode and cathode can be fabricated for a display device without the need for photolithography, which is particularly advantageous for the fabrication of large area display devices.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: October 7, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Takeo Kawase
  • Patent number: 7429335
    Abstract: A method for forming an opening through a substrate includes removing a first portion of a first face of a substrate to form a first recessed surface oblique to the first face and removing a second portion of the substrate to form a passage extending through the substrate such that the passage is bordered by the first surface.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: September 30, 2008
    Inventor: Shen Buswell
  • Publication number: 20080233752
    Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.
    Type: Application
    Filed: October 30, 2007
    Publication date: September 25, 2008
    Inventors: Sang-Choon KO, Chi-Hoon JUN, Hyeon-Bong PYO, Seon-Hee PARK
  • Publication number: 20080230512
    Abstract: The invention is to provide a printed circuit board in which advance of packaging density of the printed circuit board and reduction in production cost can be attained while processing quality can be made uniform, a method for processing the printed circuit board and a method for producing the printed circuit board. There is provided a printed circuit board including an alternate laminate of electric conductor layers and electrically insulating layers, wherein a coating layer capable of absorbing laser light but insoluble in an etching solution dissolving the electric conductor layers is provided on a front surface of a first one of the electric conductor layers. In this case, the coating layer may be provided on a front surface of a rear one of the electric conductor layers. Each of the electric conductor layers may contain Cu as a main component while the coating layer may contain CuO as a main component. The coating layer may have a thickness not thinner than 0.6 ?m.
    Type: Application
    Filed: April 28, 2008
    Publication date: September 25, 2008
    Applicant: HITACHI VIA MECHANICS, LTD.
    Inventors: Kunio Arai, Haruo Akahoshi
  • Publication number: 20080223435
    Abstract: A method of making a micron gap thermal photovoltaic device wherein at least one standoff is formed on a photovoltaic substrate, a sacrificial layer is deposited on the photovoltaic substrate and about the standoff, an emitter is attached to the standoff and has a lower planar surface separated from the photovoltaic substrate by the sacrificial layer, and the sacrificial layer is removed to form a sub-micron gap between the photovoltaic substrate and the lower planar surface of the emitter.
    Type: Application
    Filed: May 20, 2008
    Publication date: September 18, 2008
    Inventors: Paul Greiff, Robert Stephen DiMatteo
  • Publication number: 20080218559
    Abstract: A piezoelectric device includes a substrate; and a laminated film formed above the substrate. The laminated film includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer formed in this order, and the lower electrode layer is a metal electrode layer containing as one or more main components one or more nonnoble metals and/or one or more nonnoble alloys. Preferably, the one or more main components are one or more of the metals Cr, W, Ti, Al, Fe, Mo, In, Sn, Ni, Cu, Co, and Ta, and alloys of the metals.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Inventors: Takamichi FUJII, Takayuki Naono, Yoshikazu Hishinuma
  • Patent number: 7422696
    Abstract: Multicomponent nanorods having segments with differing electronic and/or chemical properties are disclosed. The nanorods can be tailored with high precision to create controlled gaps within the nanorods or to produce diodes or resistors, based upon the identities of the components-making up the segments of the nanorods. Macrostructural composites of these nanorods also are disclosed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 9, 2008
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Lidong Qin, Sungho Park, Ling Huang, Sung-Wook Chung
  • Publication number: 20080210661
    Abstract: There is provided a method for forming a via hole (2) in a substrate (10) for a flexible printed circuit board, the method being capable of simply forming a via hole having an excellent circularness of an opening portion and high reliability. In a method for forming a via hole in a substrate for a flexible printed circuit board, the method includes the steps: forming a first thin film layer (11) containing metal or alloy and having a thickness of less than 2 ?m on one surface (15) of a substrate, disposing a second thin film layer (12) over the first thin film layer (11), selectively removing a portion, corresponding to a region where the via hole (2) is formed, of the second thin film layer (12), etching the first thin film layer (11), and subjecting the substrate (10) to chemical milling to form the via hole (2).
    Type: Application
    Filed: May 23, 2006
    Publication date: September 4, 2008
    Inventors: Kazuo Satoh, Hideo Yamazaki
  • Publication number: 20080206681
    Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
    Type: Application
    Filed: May 5, 2008
    Publication date: August 28, 2008
    Inventors: Christoph Nolscher, Dietmar Temmler, Peter Moll
  • Publication number: 20080202114
    Abstract: The present invention relates generally to micro heat engines (MHEs) and methods of manufacture. More particularly, the present invention relates to an MHE including a substrate having a sealed microchannel for operatively containing a liquid droplet within the microchannel and a thermal bridge for providing a heat source or heat sink to the microchannel. The MHFE also includes a piezoelectric sensor responsive to a pressure change within the microchannel to induce voltage across the piezoelectric sensor and a power output.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 28, 2008
    Inventors: Gregory Frank Naterer, Peter Stephen Glockner