Abstract: A method of patterning a cylindrical tool, including providing a stamp including a base and a layer of solid state ionic conductor thereon, applying a negative of a predetermined pattern of features on a major surface of the solid state ionic conductor, providing a cylindrical tool having a metallic surface positioned proximate the stamp, and applying an electric field between the metallic surface and a cathode while moving the stamp against the metallic surface in rolling line contact so as to impart the predetermined pattern of features onto the metallic surface, wherein the cathode is either the base or a conductive element positioned adjacent to the base. The positive of the predetermined pattern of features may include a multiplicity of nano-sized features.

Abstract: Systems and methods for controlling directionality of ion flux at an edge region within a plasma chamber are described. One of the systems includes a radio frequency (RF) generator that is configured to generate an RF signal, an impedance matching circuit coupled to the RF generator for receiving the RF signal to generate a modified RF signal, and a plasma chamber. The plasma chamber includes an edge ring and a coupling ring located below the edge ring and coupled to the first impedance matching circuit to receive the modified RF signal. The coupling ring includes an electrode that generates a capacitance between the electrode and the edge ring to control the directionality of the ion flux upon receiving the modified RF signal.

Abstract: A temperature controller of a plasma-processing apparatus including a heating unit and a cooling unit. The heating unit is configured to heat a liner on an inner surface of a plasma chamber in which a plasma is formed. The cooling unit is configured to cool the liner to controls a temperature of an upper electrode in the plasma chamber.

Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.

Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.

Abstract: An etching apparatus includes: a placement table serving as a lower electrode and configured to place a workpiece to be subjected to an etching processing thereon; a DC power supply configured to generate a negative DC voltage applied to the placement table; and a controller configured to: periodically apply a negative DC voltage to the placement table from the DC power supply when the etching processing on the workpiece placed on the placement table is initiated, and decrease a frequency of the negative DC voltage applied to the placement table with an elapse of processing time of the etching processing.

Abstract: Disclosed is a dry etching method for etching a laminated film of silicon oxide layers and silicon nitride layers on a substrate. The dry etching method includes providing a mask on the laminated film, generating a plasma from a dry etching agent and etching the laminated film by the plasma through the mask under a bias voltage of 500 V or higher to form a through hole in the laminated film vertically to the layers, wherein the dry etching agent contains at least C3H2F4, an unsaturated perfluorocarbon represented by CxFy and an oxidizing gas, and wherein a volume of the unsaturated perfluorocarbon contained in the dry etching agent is 0.1 to 10 times a volume of the C3H2F4 contained in the dry etching agent.

Abstract: A method of processing a substrate is provided. The method includes loading a substrate in a processing chamber. The substrate is supported on a bottom electrode and the processing chamber includes a top electrode opposing the bottom electrode. The method includes placing a plasma containment structure over a selected portion of the surface of the substrate to define a plasma containment region of the selected portion of the surface of the substrate. Then, injecting at least one process gas into the plasma containment region and biasing the top electrode and the bottom electrode. The method further includes exhausting process byproducts from the plasma containment region and moving the plasma containment region relative to the substrate to selectively passes over the entire surface of the substrate.

Abstract: A method for fabrication of free standing mechanical and photonic structures is presented. A resist mask is applied to a bulk substrate. The bulk substrate is attached to a movable platform. The bulk substrate is exposed to an ion stream produced by a reactive ion beam etching source. The platform is moved relative to the ion stream to facilitate undercutting a portion of the bulk substrate otherwise shielded by the mask.

Abstract: Disclosed is a substrate treating apparatus which includes a chamber, a support unit, a dielectric plate, a gas supplying unit, an antenna, and a heating unit. The chamber has a processing space therein, and an upper surface of the processing space is opened. The support unit is disposed in the chamber and supports a substrate. The dielectric plate is installed on the opened upper surface of the chamber to cover the opened upper surface. The gas supplying unit supplies a gas in the chamber. The antenna is disposed above the dielectric plate and creates plasma from the gas. The heating unit is disposed above the antenna and heats the dielectric plate.

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

Abstract: An electrostatic chuck assembly includes a dielectric plate having an absorption electrode to generate an electrostatic force, the dielectric plate securing a substrate by the electrostatic force, a conductive base plate under the dielectric plate to be applied with a high frequency electric power, the conductive base plate being an electrode to generate plasma, and an insulating plate under the base plate, the insulating plate having an insulation body and an insulation sink, and the insulation sink having a dielectric constant lower than that of the insulation body.

Abstract: A method and a system for monitoring a plasma chamber are provided. The method includes receiving process chamber characteristics from the plasma chamber; determining whether one or more variables associated with the process chamber characteristics are within predetermined specification. The method further includes updating a status of the plasma chamber to failure when the chamber characteristics are not within the predetermined specification. The method generates a warning notification when the chamber characteristics are within predetermined specification and when an operation status of the plasma chamber received from a fault detection system indicates a failure.

Abstract: A plasma processing method in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.

Abstract: In a processing method according to one exemplary embodiment, a first nitrified region of a workpiece is etched. The first nitrified region is provided on a first protrusion made of silicon. The workpiece further has a second protrusion, a second nitrified region, and an organic region. The second protrusion is made of silicon. The second nitrified region contains silicon and nitrogen and is provided on the second protrusion. The organic region covers the first and second protrusions and the first and second nitrified regions. In the processing method, the organic region is partially etched to expose the first nitrified region. Then, a silicon oxide film is formed to cover the surface of an intermediate product produced from the workpiece. Then, the silicon oxide film is etched to expose an upper surface of the first nitrified region. Then, the first nitrified region is isotropically etched.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.

Abstract: An electrostatic chucking apparatus includes a movable member arranged for movement relative to an axial axis, at least one electrostatic chuck coupled to the movable member, and a stationary member. At least one moving insulated electrode is coupled to the movable member, and at least one stationary insulated electrode is coupled to the stationary member in an axial position corresponding to the at least one moving insulated electrode. A slip ring contact couples electrical energy from the at least one stationary insulated electrode to the at least one moving insulated electrode.

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.

Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following operations. (a) A substrate is patterned. (b) A polymer layer is formed on the patterned substrate. (c) The polymer layer is patterned. Steps (a), (b) and (c) are repeated alternatingly. An intensity of an emission light generated by a reaction of a plasma and a product produced in steps (a), (b) and (c) is detected. An endpoint in patterning the substrate is determined according to the intensity of the emission light generated by the reaction of the plasma and the product produced in only one step of steps (a), (b) and (c). A sampling rate of the intensity is ranged from 1 pt/20 ms to 1 pt/100 ms. A smooth function is used to process the intensity of the emission light generated by the reaction of the plasma and the product.

Abstract: Embodiments of method and system for controlling plasma performance are described. In an embodiment a method may include supplying power at a first set of power parameters to a plasma chamber. Additionally, the method may include forming plasma within the plasma chamber using the first set of power parameters. The method may also include measuring power coupling to the plasma at the first set of power parameters. Also, the method may include supplying power at a second set of power parameters to the plasma chamber. The method may additionally include measuring power coupling to the plasma at the second set of power parameters to the plasma. The method may also include adjusting the first set of power parameters based, at least in part, on the measuring of the power coupling at the second set of power parameters.

Abstract: Embodiments described herein include a modular high-frequency emission source comprising a plurality of high-frequency emission modules and a phase controller. In an embodiment, each high-frequency emission module comprises an oscillator module, an amplification module, and an applicator. In an embodiment, each oscillator module comprises a voltage control circuit and a voltage controlled oscillator. In an embodiment, each amplification module is coupled to an oscillator module, in an embodiment, each applicator is coupled to an amplification module. In an embodiment, the phase controller is communicatively coupled to each oscillator module.

Abstract: In a mask blank comprising a transparent substrate and a single layer or multilayer film formed thereon, the film is formed only on the front surface of the substrate, but not on the side surface, chamfer, front surface-chamfer boundary, and back surface-chamfer boundary. The mask blank contains few particle defects, especially the number of particle defects with a certain size is zero.

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.

Abstract: A plasma source includes a ring plasma chamber, a primary winding around an exterior of the ring plasma chamber, multiple ferrites, wherein the ring plasma chamber passes through each of the ferrites and multiple plasma chamber outlets coupling the plasma chamber to a process chamber. Each one of the plasma chamber outlets having a respective plasma restriction. A system and method for generating a plasma are also described.

Abstract: An apparatus (9) for plasma treating multiple containers. The apparatus includes a manifold (2) comprising at least a first chamber with multiple outlet openings and multiple hollow, electrically-conductive nozzles (10) for at least one of delivering or exhausting plasma-generating gas. The multiple hollow, electrically-conductive nozzles are connected to the multiple outlet openings and protrude from the manifold. A method of plasma treating multiple containers is also disclosed. The method includes providing a reactor system comprising an apparatus disclosed herein, inserting the multiple hollow, electrically-conductive nozzles into the multiple containers (30), evacuating the multiple containers, grounding the multiple hollow, electrically-conductive nozzles while applying radio frequency power to the multiple containers, providing a gas inside the containers, and generating a plasma. At least one of evacuating or providing the gas is carried out through the hollow, electrically-conductive nozzles.

Abstract: An etching method for etching a silicon oxide film is provided that includes generating a plasma from a gas including a hydrogen-containing gas and a fluorine-containing gas using a high frequency power for plasma generation, and etching the silicon oxide film using the generated plasma. The fluorine-containing gas includes a hydrofluorocarbon gas, and the sticking coefficient of radicals generated from the hydrofluorocarbon gas is higher than the sticking coefficient of radicals generated from carbon tetrafluoride (CF4).

Abstract: A system includes a cold plasma applicator configured to couple directly to a container, wherein the cold plasma applicator is configured to generate a cold plasma within the container. A method includes operating a cold plasma applicator to generate a cold plasma to treat contents within a container, wherein the cold plasma applicator is configured to directly couple to the container, or the cold plasma applicator comprises a varying geometry application surface having a plurality of protruding electrode portions spaced apart from one another to define a plurality of intermediate recessed portions, or a combination thereof.

Abstract: A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma.

Abstract: A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.

Abstract: Embodiments of the present invention relate to apparatus for enhancing deposition rate and improving a plasma profile during plasma processing of a substrate. According to embodiments, the apparatus includes a tuning electrode disposed in a substrate support pedestal and electrically coupled to a variable capacitor. The capacitance is controlled to control the RF and resulting plasma coupling to the tuning electrode. The plasma profile and the resulting deposition rate and deposited film thickness across the substrate are correspondingly controlled by adjusting the capacitance and impedance at the tuning electrode.

Abstract: A substrate processing method includes a fluorine-based gas supply step of supplying a fluorine-based gas into a processing chamber where a substrate having a silicon-based film is accommodated, a purge gas supply step of supplying a purge gas for discharging the supplied fluorine-based gas into the processing chamber. The substrate processing method further includes a nitrogen-based gas supply step of supplying a nitrogen-based gas into the processing chamber from which the fluorine-based gas has been discharged. In the substrate processing method, at least in the fluorine-based gas supply step and the purge gas supply step, a temperature of the substrate is maintained at 60° C. or less.

Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract: A plasma processing apparatus or a plasma processing method that processes a wafer to be processed, which is placed on a surface of a sample stage arranged in a processing chamber inside a vacuum container, using a plasma formed in the processing chamber, the apparatus or method including processing the wafer by adjusting a first high-frequency power to be supplied to a first electrode arranged inside the sample stage and a second high-frequency power to be supplied, via a resonant circuit, to a second electrode which is arranged in an inner side of a ring-shaped member made of a dielectric arranged on an outer peripheral side of a surface of the sample stage on which the wafer is placed, during the processing.

Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide while maintaining a relative humidity within the processing region below about 50%. Subsequent to the removal, the methods may include increasing the relative humidity within the processing region to greater than or about 50%. The methods may further include removing an additional amount of the exposed oxide.

Abstract: An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.

Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Abstract: Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container.

Abstract: The present invention provides a plasma processing method that uses a plasma processing apparatus including a plasma processing chamber in which a sample is plasma processed, a first radio-frequency power supply that supplies a first radio-frequency power for generating plasma, and a second radio-frequency power supply that supplies a second radio-frequency power to a sample stage on which the sample is mounted, wherein the plasma processing method includes the steps of modulating the first radio-frequency power by a first pulse; and controlling a plasma dissociation state to create a desired dissociation state by gradually controlling a duty ratio of the first pulse as a plasma processing time elapses.

Abstract: A method for processing substrate in a chamber, which has at least one plasma generating source, a reactive gas source for providing reactive gas into the interior region of the chamber, and a non-reactive gas source for providing non-reactive gas into the interior region, is provided. The method includes performing a mixed-mode pulsing (MMP) preparation phase, including flowing reactive gas into the interior region and forming a first plasma to process the substrate that is disposed on a work piece holder. The method further includes performing a MMP reactive phase, including flowing at least non-reactive gas into the interior region, and forming a second plasma to process the substrate, the second plasma is formed with a reactive gas flow during the MMP reactive phase that is less than a reactive gas flow during the MMP preparation phase. Perform the method steps a plurality of times.

Abstract: According to one embodiment, a plasma processing apparatus includes: a processing chamber; a decompression section configured to decompress inside of the processing chamber; a member including a control section to be inserted into a depression provided on mounting side of a workpiece, the control section being configured to thereby control at least one of in-plane distribution of capacitance of a region including the workpiece and in-plane distribution of temperature of the workpiece; a mounting section provided inside the processing chamber; a plasma generating section configured to supply electromagnetic energy to a region for generating a plasma for performing plasma processing on the workpiece; and a gas supply section configured to supply a process gas to the region for generating a plasma. The control section performs control so that at least one of the in-plane distribution of capacitance and the in-plane distribution of temperature is made uniform.

Abstract: A plasma processing apparatus 1 includes a chamber 10, a mounting table 16, a focus ring 24a, a first electrode plate 36 and a second electrode plate 35. The focus ring 24a is provided around the mounting table 16 to surround a mounting surface of the mounting table 16. The first electrode plate 36 is provided above the mounting table 16. The second electrode plate 35 is provided around the first electrode plate 36 to surround the first electrode plate 36 and is insulated from the first electrode plate 36. The plasma processing apparatus 1, in a first process, performs a preset processing on a semiconductor wafer W mounted on the mounting surface with plasma generated within the chamber, and, in a second process, increases an absolute value of a negative DC voltage applied to the second electrode plate 35 depending on an elapsed time of the first process.

Abstract: A method includes performing one or more times of a sequence and reducing a film thickness of a fluorocarbon-containing film formed by performing one or more times of the sequence. Each of the one or more times of the sequence includes forming the fluorocarbon-containing film on a processing target object by generating plasma of a processing gas containing a fluorocarbon gas and not containing an oxygen gas; and etching a first region with radicals of fluorocarbon contained in the fluorocarbon-containing film. In the method, an alternating repetition in which the one or more times of the sequence and the reducing of the film thickness of the fluorocarbon-containing film are alternately repeated is performed.

Abstract: A reaction system for processing semiconductor substrates is disclosed. The reaction system includes a susceptor for holding the substrate as well as a baseplate as a part of housing for the reaction system. A pin located on the susceptor can interact with a baseplate feature located on the baseplate to result in a variable gap between the susceptor and the baseplate. The baseplate feature may take the form of a series of steps, a wedge, or a milled-out feature.

Abstract: A method of plasma etching one or more features in a silicon substrate includes performing a main etch using a cyclical etch process in which a deposition step and an etch step are alternately repeated, and performing an over etch to complete the plasma etching of the features. The over etch includes one or more etch steps of a first kind and one or more etch steps of a second kind, each of the etch steps of the first and second kind include etching by ion bombardment of the silicon substrate. The ion bombardment during the one or more etch steps of the second kind has an inward inclination with respect to ion bombardment during the one or more etch steps of the first kind.

Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.