Of Electrical Device (e.g., Semiconductor) Patents (Class 228/179.1)
  • Publication number: 20140299170
    Abstract: The invention relates to a thermoelectric device comprising: a plurality of elements (4), called thermoelectric elements, allowing an electrical current to be produced from a temperature gradient between two of their faces (3a, 3b), called contact faces; electrically conductive tracks (20); and a solder joint between said contact faces (3a, 3b) and the electrically conductive tracks. According to the invention, said solder comprises an alloy based on aluminum and silicon. The invention also relates to a process for manufacturing such a device, using solid-state soldering.
    Type: Application
    Filed: November 22, 2012
    Publication date: October 9, 2014
    Inventors: Michel Simonin, Patrick Boisselle, Cédric De Vaulx
  • Patent number: 8851356
    Abstract: Embodiments of the invention include flexible circuit board interconnections and methods regarding the same. In an embodiment, the invention includes a method of connecting a plurality of flexible circuit boards together comprising the steps applying a solder composition between an upper surface of a first flexible circuit board and a lower surface of a second flexible circuit board; holding the upper surface of the first flexible circuit board and the lower surface of the second flexible circuit board together; and reflowing the solder composition with a heat source to bond the first flexible circuit board and the second flexible circuit board together to form a flexible circuit board strip having a length longer than either of the first flexible circuit board or second flexible circuit board separately.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 7, 2014
    Assignee: Metrospec Technology, L.L.C.
    Inventors: Henry V. Holec, Wm. Todd Crandell, Eric Henry Holec
  • Publication number: 20140263582
    Abstract: A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer conforms to a shape of the contacted portion of the replicate. The conductive layer is formed to have a base and a plurality of conductive posts projecting away from the base. Each conductive post is formed to have a post end opposite the base. A dielectric layer is formed to cover the base and to separate adjacent ones of the posts from each other. The posts are for forming vias. Conductive material is removed from the conductive layer to insulate at least one post from at least one other post.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 8833637
    Abstract: A device using the live welding method for aluminum electrolytic cell overhauling under series full current consists of short-circuit buses at the bottom of the cell (1), pillar buses (2), an anode bus (3), a balance bus (4), a inter-cell standby bus (5), a door-shaped pillar clamp (6), an arcuate clamp (7) of anode buses, a current conversion switch (8, a mechanical switching device (9) for the short-circuit port, a voltage sensor and wires thereof (10), a temperature sensor and wires thereof (11), a system (12) for data acquiring, displaying, analyzing and alarming, an A-side welding area (13), a B-side welding area (14) and compression-joint points (15) on pillar soft belts of overhauling cells; and the live welding method comprises the following steps: when welding is required to be performed in some zone, the currents of short-circuit buses at the bottom of the cell (1) and pillar buses (2) which influence the welding area most are cut off, the serial currents are shunted to other pillar buses (2), other
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: September 16, 2014
    Assignee: China Aluminum International Engineering Corporation Limited
    Inventors: Tao Yang, Bin Cao
  • Patent number: 8820611
    Abstract: The present invention relates to a method for printing a substrate, in particular a printed circuit board, with a printing paste, in particular a solder paste, comprising the following steps: —applying a printing screen to the substrate, —printing the substrate using screen printing technology through openings in the printing screen so as to achieve at least one printed structure consisting of printing paste, —separating the printing screen and the substrate by lifting these parts off from one another, —inserting an optical inspection unit between the printing screen and the substrate, —checking the printed structure in terms of the printing paste thickness thereof by means of the inspection unit, —ending the printing when the result of the printing corresponds to at least one preset value. The invention furthermore relates to an inspection unit (1) and a printing device (2).
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 2, 2014
    Assignee: Ekra Automatisierungssysteme GmbH
    Inventor: Torsten Vegelahn
  • Patent number: 8807416
    Abstract: A reflow soldering system wherein a heating oven is provided with a contact heating unit which has a transport rail and a top heat transfer heater, and with a hot gas blowing heating unit, the transport rail and top heat transfer heater are respectively provided with heaters which heat the outer edge part of the printed circuit board, and the transport rail or top heat transfer heater moves in an up-down direction so that the transport rail and top heat transfer heater clamp and heat the outer edge part of the printed circuit board.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: August 19, 2014
    Assignee: Denso Corporation
    Inventors: Takuji Sukekawa, Hiroyuki Yamada, Noriyasu Inomata
  • Patent number: 8794501
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 5, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 8794499
    Abstract: In a method for manufacturing a substrate, connections are provided through metal columns of bumps press-fitted into an insulating resin layer between metal foils contact-bonded to a thermosetting insulating resin layer. Bumps of a conductive paste containing metal fillers are formed on a metal foil which is to be contact-bonded to an insulating resin layer, the bumps are heated to bound the metal fillers to each other, and form a metallic bond between the bumps and the metal foil, the metal columns are press-fitted into the insulating resin layer to contact-bond the metal foil to the insulating resin layer, and join the tips of the metal columns to a metal foil, the metal columns are then reheated to form a metallic bond between the metal columns and the metal foil.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: August 5, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasuyuki Sekimoto
  • Publication number: 20140193658
    Abstract: Methods and apparatus are provided for attaching a heat spreader to a die and includes disposing a solder thermal interface material between a first surface of a die and a first surface of a heat spreader without disposing a liquid flux between the die and the heat spreader to form an assembly, wherein at least one of the first surface of the die and a first surface of the heat spreader have disposed thereon a metallization structure comprising a transition layer and a sacrificial metallization layer, the sacrificial metallization layer disposed as an outer layer to the metallization structure adjacent the solder thermal interface material; and heating the assembly to melt the thermal interface and attach the die to the heat spreader.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 10, 2014
    Applicant: Indium Corporation
    Inventors: Jordan Peter Ross, Amanda Hartnett, Robert Norman Jarrett
  • Patent number: 8763884
    Abstract: The present invention relates to a joint (10) that includes a first member (11) to be jointed, a second member (12) to be jointed and a jointing layer (13) located between the first member (11) and the second member (12). The jointing layer (13) is made of Sn metal and a metallic material with a melting point higher than the melting point of the Sn metal. The present invention relates also to a method of joining this first member (11) to the second member (12).
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Takahashi, Tatsuoki Kono, Mitsuhiro Oki, Akiko Suzuki
  • Patent number: 8752754
    Abstract: Disclosed are an apparatus for adhering solder powder to finely adhere the solder powder to an electronic circuit board and a method for adhering solder powder to the electronic circuit board.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 17, 2014
    Assignee: Showa Denko K.K.
    Inventors: Takashi Shoji, Takekazu Sakai
  • Patent number: 8740046
    Abstract: A soldering system includes a track, a laying device, a boiler, a shelter, a transmission roller, a position sensor, a thermal radiation heating device, and a driving device. At least one hole is formed on the shelter, and a shape and a dimension of at least one hole on the shelter corresponds to a shape and a dimension of a DIP component. The transmission roller rotates the shelter according to a transmission speed of the track. The position sensor detects a position of a circuit board relative to the boiler. The thermal radiation heating device heats an area on a second surface of the circuit board different from a first surface adjacent to the DIP component through the at least one hole on the shelter continuously, so as to increase a temperature of the second surface when the first surface of the circuit board is passing through the boiler.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 3, 2014
    Assignee: Wistron Corporation
    Inventors: Hao-Chun Hsieh, Chia-Hsien Lee
  • Publication number: 20140134473
    Abstract: An electrical interconnect is disclosed that includes an inner conductive material having a top surface and a bottom surface; and an outer conductive material different from the inner conductive material, wherein the outer conductive material is clad on the top and bottom surfaces of the inner conductive material, wherein the electrical interconnect is configured to be secured to a first terminal of a first electrochemical cell and a second terminal of a second electrochemical cell. A method of manufacturing an electrical interconnect is also disclosed.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Kristopher John FRUTSCHY, Bhat Radhakrishna BADEKILA, Alec Roger TILLEY, Thomas R. RABER, William H. SCHANK
  • Publication number: 20140118881
    Abstract: There is provided a capacitor, including: a first substrate: a first capacitance generation part formed on the first substrate; a protective layer formed on the first capacitance generation part; a second capacitance generation part formed on the protective layer; and a second substrate formed on the second capacitance generation part.
    Type: Application
    Filed: January 14, 2013
    Publication date: May 1, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Yoon KIM, Young-Sik KANG, Sung Min CHO, Yeong Gyu LEE
  • Patent number: 8704137
    Abstract: This invention introduces the welding technology of an electrical connector and its welding device. The welding device comprises of a base frame, IR lamp that can emit infrared rays, and convex lens used to collect infrared rays. The lamp and lens are set in the base frame, with the convex lens in front, which collects all infrared rays from the lamp and irradiates them to the solder paste, allowing for fast heating. The melted solder paste forms defect-free welding spots with sound electrics performance and low energy consumption, thus saving energy. This invention of welding device is used for the welding when electrical connector is assembled, solder paste is put and the connector is fixed in the conveying belt. The electrical connector goes through the heating zone in welding device, which enables the automatic welding of each cored wire in the electrical connector and wire connecting terminal. The welding is fast and the production can be continuous free of any tack welding.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 22, 2014
    Inventor: Ching-Jen Hsu
  • Patent number: 8698053
    Abstract: A method for producing an electronic device is disclosed. One embodiment provides two soldering partners to be connected to one another at an envisaged joining location and at least one of which includes an electronic component or is formed as such a component, a soldering apparatus having an inductor, and an intermediate plate The soldering partners, the inductor and the intermediate plate are positioned in such a way that the intermediate plate is arranged between the electronic component and the envisaged joining location, on the one hand, and the inductor. The soldering partners are connected at the envisaged joining location by using a solder that is melted by energy emitted by the inductor.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies AG
    Inventor: Alfred Kemper
  • Patent number: 8690041
    Abstract: A method of soldering a DIP component on a circuit board includes piercing the DIP component through the circuit board, laying fluxer on the circuit board, passing a first surface of the circuit board through a boiler so that molten tin from the boiler flows between the DIP component and the circuit board through the first surface of the circuit board, and heating a second surface of the circuit board different from the first surface so as to increase temperature of the second surface by a thermal radiation heating device to when the first surface of the circuit board passes through the boiler.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: April 8, 2014
    Assignee: Wistron Corporation
    Inventors: Hao-Chun Hsieh, Chia-Hsien Lee
  • Patent number: 8679591
    Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu
  • Publication number: 20140063168
    Abstract: A light-emitting substrate including: a first and second light-emitting devices each including terminals; and a substrate including a first hole and a second hole, the first hole and the second hole respectively having at least one receiving portion, wherein the receiving portion of the first hole receives the terminal of the first light-emitting device, and the receiving portion of the second hole receives the terminal of the second light-emitting device, a first line drawn through a center of the receiving portion of the first hole and a center of the first hole, and a second line drawn through a center of the receiving portion of the second hole and a center of the second hole are not aligned in line.
    Type: Application
    Filed: August 12, 2013
    Publication date: March 6, 2014
    Inventors: Katsuhiko MAEDA, Hiroyuki Basho, Masashi Suzuki, Yuugo Matsuura
  • Publication number: 20140043783
    Abstract: Provided is a printed wiring board including a first heat dissipation pattern placed in one surface layer on which a semiconductor package is to be mounted, a second heat dissipation pattern placed in the other surface layer, and an inner layer conductor pattern placed in an inner layer, in which through holes are formed in the printed wiring board; the first heat dissipation pattern has a joint portion which is placed in an opposed region opposed to a heat sink of the semiconductor package and which is joined to the heat sink with solder; at least one of the through holes is placed in the opposed region; and the second heat dissipation pattern is formed in a pattern in which an end portion of a conductor film in the one of the through holes on the other surface layer side is separated.
    Type: Application
    Filed: July 29, 2013
    Publication date: February 13, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Masaharu Ohira
  • Publication number: 20130342986
    Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Inventors: Tsung-Yu Chen, Rebecca Shia
  • Publication number: 20130334291
    Abstract: Disclosed are a method of forming a solder on pad on a fine pitch PCB and a method of flip chip bonding a semiconductor device using the same. The method of forming a solder on pad on a fine pitch PCB includes: applying a solder bump maker (SBM) paste with a predetermined thickness to an entire surface of a PCB including a metal pad and a solder mask; heating the SBM paste at a temperature higher than a melting point of solder contained in the SBM paste and then cooling the SBM paste to form a solder on pad; and washing a residual polymer resin and residual solder particles of the SBM paste by using a solvent.
    Type: Application
    Filed: February 6, 2013
    Publication date: December 19, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung EOM, Kwang-Seong Choi, Jung Hyun Noh
  • Publication number: 20130334292
    Abstract: A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1 nm to 10 ?m.
    Type: Application
    Filed: July 22, 2013
    Publication date: December 19, 2013
    Inventors: Frank Ferdinandi, Rodney Edward Smith, Mark Robson Humphries
  • Publication number: 20130308276
    Abstract: A semiconductor device has, at least, a cooling base and a plurality of insulating substrates with conductive patterns fixed onto the cooling base through a solder. A solder pool portion is provided on the cooling base to contact a position of the cooling base directly below an edge of each of the insulating substrates with conductive patterns with a shortest distance from a center point of the cooling base.
    Type: Application
    Filed: September 13, 2011
    Publication date: November 21, 2013
    Applicant: FUJI ELECTRIC CO., LTD
    Inventor: Kenji Suzuki
  • Patent number: 8586857
    Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Miasole
    Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
  • Patent number: 8573469
    Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 5, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Hsin-Hua Hu, Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law
  • Publication number: 20130288544
    Abstract: A voltage tap element configured to tap off the voltage of a battery cell of a battery unit by an electronics unit, a cell supervisory unit having such voltage tap elements, and a battery unit having such a cell supervisory unit, and methods for producing the cell supervisory unit and the battery unit. The voltage tap element is designed as a clip composed of a first metal, with a first end of the clip having a first contact region which establishes a operative connection to the electronics unit, and a second end of the clip having a second contact region for establishing a connection to the battery cell. In the first contact region, the clip is permanently connected to an intermediate piece which is composed of a second metal which differs from the first metal. The intermediate piece is configured for operative connection to the electronics unit by a solder connection using SMD technology.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 31, 2013
    Applicant: MAGNA STEYR Battery Systems GmbH & Co OG
    Inventors: Michael ERHART, Uwe GEIDL, Martin HAFELLNER, Thomas KORHERR
  • Publication number: 20130277818
    Abstract: In one embodiment, a chip carrier support system includes a chip carrier support structure and a chip carrier. The chip carder forms a complementary fit with the chip carder support structure and includes an integrated circuit and a plurality of leads in communication with the integrated circuit.
    Type: Application
    Filed: January 20, 2011
    Publication date: October 24, 2013
    Inventors: Chi Hock Goh, Soon Peng Jason Sim, Poh Boon Teo
  • Publication number: 20130277098
    Abstract: The present invention has an aspect to provide a mounted structure of which heat-resistant fatigue characteristic is improved. A mounted structure is provided with a substrate having a substrate electrode, an electronic component having a component electrode, and a bonding part bonding the substrate electrode and the component electrode, wherein the bonding part is constituted by a solder reinforcing part and a solder bonding part, the solder reinforcing part is a side vicinity part of the bonding part, and is constituted by In of 3 wt % or more and 8 wt % or less and Sn of 88 wt % or more, and the solder bonding part is constituted by a Sn—Bi system solder material and In of 0 wt % or more and less than 3 wt %.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 24, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Kiyohiro Hine, Akio Furusawa, Masato Mori
  • Patent number: 8561878
    Abstract: Techniques for linear cell stringing are disclosed. In some embodiments, a plurality of sets of solar cells are linearly positioned, a plurality of tabbing ribbon segments are placed in contact with the plurality of sets of solar cells, and the plurality of sets of solar cells and corresponding plurality of tabbing ribbon segments are soldered together to form a plurality of solar cell strings. In some cases, the plurality of solar cell strings is substantially simultaneously formed in parallel.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Banyan Energy, Inc.
    Inventors: David Sheldon Schultz, John Hunter Mack, Kenneth Evan Rakestraw
  • Patent number: 8561879
    Abstract: Devices and methods for assembling co-planar electrical contacts in a connector are provided herein. In one aspect, an exemplary method of assembly comprises depositing solder in a connector plug enclosure, positioning electrical contacts on the solder deposits, advancing the hotbar toward the enclosure contacting each of the electrical contacts so as to planarize a top surface of each of the electrical contacts with the enclosure and melting the solder with the heated hotbar to solder the electrical contacts to the enclosure. In one aspect, an exemplary hotbar device includes a magnet for releasably coupling the electrical contacts to the hotbar. In another aspect, the hotbar includes metallic portions for heating the electrical contacts and insulated ceramic portions for contacting the enclosure. In another aspect, an electrically conductive hotbar includes side portions that extend away from the bottom heating surface facilitating more uniform current flow through the hotbar.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 22, 2013
    Assignee: Apple Inc.
    Inventors: Eric S. Jol, Mathias W. Schmidt, Edward Siahaan, Albert J. Golko
  • Patent number: 8556159
    Abstract: Forming an embedded electronic component includes attaching an electronic component to a first conductive layer and forming a layer stack with a first partially cured dielectric layer having a first opening and a substrate having a second opening. The partially cured dielectric layer is located over the first conductive layer and the substrate is located over the first partially cured dielectric layer such that the first and second openings surround the electronic component. Heat and pressure are applied to the layer stack such that the first partially cured dielectric layer flows for filling gaps within the first and second openings and becomes fully cured.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 15, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tu-Anh N. Tran, Burton J. Carpenter
  • Patent number: 8536045
    Abstract: A reflow method of a solder ball provided to a treatment object may include providing a coil, applying a current to the coil, and moving the treatment object through an internal space surrounded by the coil.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minill Kim, Kwang Yong Lee, Jonggi Lee, Ji-Seok Hong
  • Patent number: 8516692
    Abstract: A solder layer, a substrate for device joining utilizing the same and a method of manufacturing the substrate are provided whereby the device joined remains thermally unaffected, an initial bonding strength in solder joint is enhanced and the device can be soldered reliably. The solder layer formed on a base substrate (2) consists of a plurality of layers (5a) of a solder free from lead, which are different in its phase from one another. They are constituted by a layer of a phase that is completely melted, and a layer of a phase that is not completely melted at a temperature not less than a eutectic temperature of the solder. The solder layer (5) can be applied to a device joining substrate (1) comprising an electrode layer (4) formed on the base substrate (2) and the solder layer (5) formed on the electrode layer.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: August 27, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Oshika, Munenori Hashimoto, Masayuki Nakano
  • Publication number: 20130201631
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 8, 2013
    Applicant: CRANE ELECTRONICS, INC.
    Inventor: Crane Electronics, Inc.
  • Patent number: 8492673
    Abstract: Avoiding contaminant generation within a hard disk drive due to increased temperatures during a solder reflow process is described. Energy from a beam of energy that is directed toward a plurality of polyimide regions is received. Each of the plurality of polyimide regions are disposed adjacent to at least one solder pad. The plurality of polyimide regions and the at least one solder pad comprises a first component of a hard disk drive. Then, a portion of the energy is reflected away from the plurality of polyimide regions to prevent an absorption of the portion by the plurality of polyimide regions and a burning of the plurality of polyimide regions.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 23, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Edgar Rothenberg, Jr-Yi Shen
  • Patent number: 8485417
    Abstract: A micromachined switch is provided including a base substrate, a bond pad on the base substrate, a cantilever arm connected to the bond pad, the cantilever arm having a conductive via from the bond pad, a first actuation electrode on the base substrate, and a second actuation electrode on the cantilever arm connected to the bond pad by way of the conductive via, positioned such that an actuation voltage applied between the first actuation electrode and the second actuation electrode will deform the cantilever arm, wherein the first actuation electrode is facing a side of the cantilever arm opposite the second actuation electrode.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 16, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: David T. Chang, Tsung-Yuan Hsu
  • Patent number: 8485416
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8485418
    Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a “temporary” (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 16, 2013
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Publication number: 20130157498
    Abstract: In exemplary implementations of this invention, electrical connections are fabricated between two orthogonal surfaces by electroplating. The two surfaces are separated (except for the electrical connections) by a gap of not more than 100 micrometers. Multiple electrical connections may be fabricated across the gap. In preparatory steps, conductive pads on the two surfaces may be separately electroplated to build up “bumps” that make it easier to bridge the remainder of the gap in a final plating step. Alternately, electroless deposition may be used instead of electroplating. In exemplary implementations, a 3D probe array may be assembled by inserting array structures into an orthogonal base plate. The array structures may be aligned and held in place, relative to the base plate, by mechanical means, including side hooks, stabilizers, bottom hooks, alignment parts and a back plate.
    Type: Application
    Filed: November 12, 2012
    Publication date: June 20, 2013
    Applicant: Massachusetts Institute of Technology
    Inventors: Jorg Scholvin, Anthony Zorzos, Clifton Fonstad, Edward Boyden
  • Patent number: 8453917
    Abstract: A system includes a device of the surface-mounting type having an insulating package provided with a mounting surface and a contact pin exposed on the mounting surface. The device is attached to an insulating board including a gluing surface and an opposite surface. The process for manufacturing the system includes forming through holes a contact region on the gluing surface. The mounting surface is glued to the gluing surface with the contact pin aligned with the contact region. Wave soldering is performed to electrically join the device to the board by hitting the opposite surface with a wave of soldering paste to form, by capillary action with the soldering paste ascending in the through holes up to the overflow on the gluing surface, a conductive contact electrically connecting the contact pin of the electronic device through a solder connection to the contact region of the electronic board.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Concetto Privitera, Cristiano Gianluca Stella
  • Patent number: 8448834
    Abstract: A board printing system is provided with a printing apparatus for printing solder paste on each board, a printing inspection apparatus for inspecting a printed state of solder paste on each board, a transfer device for transferring each board in a forward direction from an unloading portion of the printing apparatus to a loading portion of the printing inspection apparatus, a reversible feed holding device configured to be able to hold a failure board which was taken out from the loading portion of the printing inspection apparatus as a result of being judged by the printing inspection apparatus to be rejected, after feeding the failure board in a reverse direction and then, to load the failure board to the loading portion of the printing inspection apparatus by feeding the failure board in the forward direction, and a selection device for enabling the transfer device and the reversible feed holding device to be used selectively.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 28, 2013
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Tomohiko Hattori, Hiroshi Tsuta
  • Publication number: 20130127041
    Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Kim-Yong Goh
  • Patent number: 8444043
    Abstract: An array of solder balls is attached to solder pads of one of a first substrate and a second substrate. After aligning the array of solder balls relative to solder pads of the other of the first substrate and the second substrate, a thermal-mass-increasing fixture is placed on a surface of the second substrate to form an assembly of the first substrate, the second substrate, and the array of the solder balls therebetween, and the thermal-mass-increasing fixture. The thermal-mass-increasing fixture is in physical contact with at least a surface of a periphery of the second substrate. The thermal-mass-increasing fixture reduces the cool-down rate of peripheral solder balls after a reflow step, thereby increasing time for deformation of peripheral solder balls during the cool-down and reducing the mechanical stress on the solder balls after the cool-down.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Marcus E. Interrante, Rajneesh Kumar, Chenzhou Lian, Janak G. Patel, Peter Slota, Jr.
  • Publication number: 20130119118
    Abstract: This method for manufacturing a semiconductor laser apparatus includes steps of forming a first semiconductor laser device having a first electrode, forming a second semiconductor laser device having a second electrode, forming a first solder layer with a first melting point through a first barrier layer on a third electrode, forming a second solder layer with a second melting point through a second barrier layer on a fourth electrode, bonding the first electrode to the third electrode through a first reaction solder layer, a melting point of which rises to a third melting point higher than the second melting point by reacting the first electrode with the first solder layer, and bonding the second electrode to the fourth electrode by applying heat of a first heating temperature to melt the second solder layer with the second melting point after the step of bonding the first electrode to the third electrode.
    Type: Application
    Filed: December 27, 2012
    Publication date: May 16, 2013
    Applicants: SANYO OPTEC DESIGN CO., LTD., SANYO ELECTRIC CO., LTD.
    Inventors: SANYO ELECTRIC CO., LTD., SANYO OPTEC DESIGN CO., LTD.
  • Patent number: 8439249
    Abstract: A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventors: Roland Speckels, Thomas Licht, Karsten Guth
  • Patent number: 8434665
    Abstract: Disclosed are an electronic component mounting system and an electronic component mounting method capable of reducing the space occupied by equipment and equipment cost and ensuring high connection reliability. An electronic component mounting system (1) includes a solder printing device (M1), a coating/inspection device (M2), a component mounting device (M3), a bonding material supply/substrate mounting device (M4), and a reflow device (M5). The electronic component mounting system (1) mounts an electronic component on a main substrate (4) and connects a module substrate (5) to the main substrate (4). A cream solder is printed on the main substrate (4) to mount an electronic component, a bonding material in which solder particles are contained in thermosetting resin is supplied to a first connection portion of the main substrate (4), and a second connection portion of the module substrate (5) is landed on the first connection portion through the bonding material.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Koji Motomura, Hideki Eifuku, Tadahiko Sakai
  • Publication number: 20130105980
    Abstract: Disclosed is a sinterable bonding material which is a liquid or a paste containing copper nanoparticles having a particle diameter of 1,000 nm or less, in which the copper nanoparticles have one or more particle diameter peaks of a number-based grain size distribution within a class of particle diameter of 1 to 35 nm and within a class of particle diameter of more than 35 nm and 1,000 nm or less respectively, and in which the copper nanoparticles include individual particles (primary particles) and secondary particles, each of the secondary particles being a fused body of the primary particles. Thus, oxidation resistance and bondability are made compatible in a sinterable bonding material using copper nanoparticles, and ion migration is suppressed in a bonded portion of a semiconductor device, etc. manufactured by using the sinterable bonding material.
    Type: Application
    Filed: October 24, 2012
    Publication date: May 2, 2013
    Applicant: HITACHI, LTD.
    Inventor: Hitachi, Ltd.
  • Publication number: 20130105558
    Abstract: A soldering method capable of alleviating positional displacement between substrates even though a step of removing flux can be omitted is provided. A temporary bonding agent 55 is applied onto multiple substrates 50a, 50b, and a heater 33 heats the substrates while the substrates are temporarily bonded with the temporary bonding agent 55 interposed therebetween, and before the solder 54 is melted or while the solder 54 is melted, the temporary bonding agent 55 is evaporated, and the substrates 50a, 50b are bonded with solder with the melted solder 54 interposed therebetween.
    Type: Application
    Filed: June 24, 2011
    Publication date: May 2, 2013
    Applicant: AYUMI INDUSTRY CO., LTD.
    Inventors: Hideyuki Abe, Kazuaki Mawatari
  • Publication number: 20130105195
    Abstract: A conductor for a communications cable includes an elongated metal wire and a metal sheet that includes a plurality of carbon nanotubes that at least partially surrounds the elongated metal wire. The metal wire may include copper, and the metal sheet may likewise include copper and may be welded to an outside surface of the metal wire to surround the metal wire. This conductor may be used in a variety of communications cables that carry high frequency signals.
    Type: Application
    Filed: April 13, 2012
    Publication date: May 2, 2013
    Inventor: Luc Walter Adriaenssens