Of Electrical Device (e.g., Semiconductor) Patents (Class 228/179.1)
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Patent number: 7918381Abstract: The present invention relates to a method and apparatus for mounting electrical components to electric circuit boards. Specifically, the present invention relates to a method for mounting electrical components having near-zero standoff height to electrical printed circuit boards.Type: GrantFiled: November 28, 2005Date of Patent: April 5, 2011Assignee: Delphi Technologies, Inc.Inventors: Michael R. Witty, David W. Ihms, Joel D. Hunt
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Publication number: 20110071397Abstract: A modular and tileable sensor array with routing in the interposer carrying the signals from the sensors to the integrated circuits. In one embodiment a large area modular sensor array assembly includes one or more tileable modules coupled together. The tileable modules have a plurality of transducer cells forming a sensor, an interposer coupled on a first side to the plurality of transducer cells by a plurality, one or more integrated circuits coupled to a second side of the interposer, wherein the interposer is configured to form the connection of at least some of the transducer cells to the integrated circuits, and one or more input/output connectors coupled to the interposer and providing an external interface.Type: ApplicationFiled: February 26, 2010Publication date: March 24, 2011Applicant: GENERAL ELECTRIC COMPANYInventors: Robert Gideon Wodnicki, Rayette Ann Fisher, Charles Gerard Woychik, Shubhra Bansal, Albert Taesung Byun
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Publication number: 20110057299Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.Type: ApplicationFiled: September 9, 2010Publication date: March 10, 2011Inventors: Yasuki TAKATA, Kaori Sumitomo, Hiroshi Horibe, Hideyuki Arakawa
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Publication number: 20110049221Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.Type: ApplicationFiled: September 1, 2009Publication date: March 3, 2011Applicant: International Business Machines CorporationInventors: Pascal P. Blais, Paul F. Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L. Toutant, Alain A. Warren
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Publication number: 20110051758Abstract: A high power laser source comprises at least a bar of laser diodes with a first coefficient of thermal expansion (CTEbar), a submount onto which said laser bar is affixed with a second coefficient of thermal expansion (CTEsub), and a cooler onto which said submount is affixed with a third coefficient of thermal expansion (CTEcool). The submount/cooling assembly exhibits an effective fourth coefficient of expansion (CTEeff). According to the invention, mechanical stress exerted to the laser bar improves reliability and optical performance. To effect this, CTEeff must differ from CTEbar, CTEeff?CTEbar. Preferably, CTEeff should differ by a predetermined amount from CTEbar. The difference is achieved in two ways: either by selecting CTEsub>CTEbar and CTEsub?CTEcool, or by selecting CTEsub<CTEbar and CTEsub<CTEcool. Thereby, all coefficients must be selected such that CTEeff differs from CTEbar: CTEeff?CTEbar, preferably by a percentage of 5% or by a predetermined amount of +/?3-4×10?7K?1.Type: ApplicationFiled: September 1, 2010Publication date: March 3, 2011Applicant: OCLARO TECHNOLOGY PLCInventors: Martin KREJCI, Norbert LICHTENSTEIN, Stefan WEISS, Julien BOUCART, René TODT
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Patent number: 7898076Abstract: Assemblies for dissipating heat from integrated circuits and circuit chips are disclosed. The assemblies include a low melt solder as a thermal interface material (TIM) for the transfer of heat from a chip to a heat sink (HS), wherein the low melt solder has a melting point below the maximum operating temperature of the chip. Methods for making the assemblies are also disclosed.Type: GrantFiled: April 30, 2007Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Bruce Furman, Madhusudan K. Iyengar, Paul A. Lauro, Yves Martin, Roger R. Schmidt, Da-Yuan Shih, Theodore G. Van Kessel, Wei Zou
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Patent number: 7880124Abstract: An embodiment of the present invention is a technique to package a device. Heat is localized on a die having bumps on a package substrate using a first induction heater operating at a first frequency. Heat is localized on at least an integrated heat spreader (IHS), a thermal interface material (TIM), an underfill, and a sealant on the die using a second induction heater operating at a second frequency.Type: GrantFiled: November 13, 2006Date of Patent: February 1, 2011Assignee: Intel CorporationInventor: Thomas Joseph DeBonis
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Patent number: 7861914Abstract: A method is provided for the production of a bond between a first element having at least one first metal coating and at least one further element having a second metal coating, the at least one further element being freely moveable in a medium and the at least one first metal coating of the first element and the second metal coating of the at least one further element being in a solid state, a liquid phase being formed upon contact of the at least one first metal coating with the second metal coating.Type: GrantFiled: October 7, 2009Date of Patent: January 4, 2011Assignee: Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.Inventor: Hans-Hermann Oppermann
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Patent number: 7850060Abstract: A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions having been selected such that heating to a first temperature will cause a change in at least one of the at least two compositions such that the change will result in a new composition having a new composition melting point of a second temperature, greater than the first temperature and the melting point of at least a first of the at least two compositions, and heating the pair of contacts and the at least two compositions to the first temperature.Type: GrantFiled: April 5, 2007Date of Patent: December 14, 2010Inventor: John Trezza
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Publication number: 20100310964Abstract: In order to provide a sealing assembly for a fuel cell stack comprising a plurality of fuel cell units, which are arranged consecutively in a stacking direction, wherein each of the fuel cell units comprises a housing with at least one housing part made of a metallic material, which also has an adequate electrical insulation effect and an adequate mechanical strength at a high operating temperature of the fuel cell stack, it is proposed that the sealing assembly comprises at least one intermediate element made of a metallic material, wherein the intermediate element is soldered to a housing part of a first fuel cell unit at least one location by means of a metal solder and is secured to a housing part of a second fuel cell unit at least another location, wherein the intermediate element and/or the housing part of the first fuel cell unit is provided with a coating made of a ceramic material.Type: ApplicationFiled: August 3, 2010Publication date: December 9, 2010Inventors: Hans-Rainer Zerfass, Armin Diez, Peter Schenk, Wolfgang Fritz, Peter Lamp, Manfred Wier, Joachim Tachtler
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Patent number: 7842897Abstract: A wire bonding apparatus including a joining machine unit for joining a wire to a subject device, a measurement unit for measuring the connection state between the subject device and the wire, and a control unit for controlling the operation of the entire apparatus. An AC-C measurement circuit of the measurement unit includes an AC power supply, an equivalent capacitance circuit that creates an essentially the same capacitance as the capacitance component of the joining machine unit before bonding, a differential circuit that finds the difference between the capacitance of the joining machine unit after bonding and the capacitance of the equivalent capacitance circuit, an amplification circuit, a rectification circuit, an AID conversion circuit, a judgment unit that judges the connection state, and an output unit.Type: GrantFiled: December 23, 2005Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ShinkawaInventors: Toshimichi Miyahara, Yuu To, You Kawamoto
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Patent number: 7842891Abstract: There is provided a sealing board (30) for sealing a container containing an electronic component, constituted of a base which is made of a material exhibiting a low wettability to a brazing filler metal (31) and on a surface of which a metal layer exhibiting a high wettability to the brazing filler metal (31) is formed, a brazing filler metal portion formed on the metal layer to form a closed region, and an exposed portion in which a surface of the base is exposed in at least a part of the closed region. By making at least a part of the sealing board as the exposed portion, it is possible to produce the sealing board with the brazing filler metal for a package stable in quality and inexpensively.Type: GrantFiled: January 20, 2006Date of Patent: November 30, 2010Assignee: Citizen Holdings Co. Ltd.Inventors: Takao Kasai, Haruyuki Hiratsuka
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Publication number: 20100291732Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.Type: ApplicationFiled: July 8, 2010Publication date: November 18, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Yoichiro Kurita
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Publication number: 20100276813Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.Type: ApplicationFiled: July 19, 2010Publication date: November 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luc Belanger, David Danovitch, John U. Knickerbocker
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Publication number: 20100246099Abstract: A solid electrolytic capacitor includes a capacitor element, an external conduction member and a fuse conductor. The capacitor element includes a porous sintered body made of valve metal, an anode wire projecting from the porous sintered body, and a dielectric layer and a solid electrolyte layer covering the porous sintered body. The fuse conductor electrically connects the external conduction member and one of the anode wire and the solid electrolyte layer to each other. The fuse conductor is made of a metal containing one of Au—Su-based alloy, Zn—Al-based alloy, Sn—Ag—Cu-based alloy, Sn—Cu—Ni—based alloy and Sn—Sb—based alloy.Type: ApplicationFiled: March 17, 2010Publication date: September 30, 2010Applicant: ROHM CO., LTD.Inventors: Kentaro Naka, Takahiro Maeda
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Publication number: 20100246148Abstract: Disclosed herein is an electronic apparatus produced using a high-temperature lead-free solder alloy which makes it possible to form soldered joints having no variations in strength and which has an excellent balance between strength and solderability. The lead-free solder alloy is an alloy which is made of an element A and an element B and which has a composition composed of AmBn being a stable phase and the element B in an equilibrium state at room temperature. When the lead-free solder alloy is solidified by quenching, the element A is dissolved in a room-temperature stable phase of the element B so that a supersaturated solid solution is formed, and when melted for soldering and then solidified, the alloy returns to its equilibrium state and has a composition composed of the stable phase AmBn and the element B and therefore maintains strength due to the presence of the stable phase AmBn even when reheated to a soldering temperature.Type: ApplicationFiled: December 20, 2007Publication date: September 30, 2010Applicant: SANYO SPECIAL STEEL CO., LTD.Inventors: Hiroki Ikeda, Katsu Yanagimoto
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Publication number: 20100230474Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Leslie Buchwalter, Bruce K. Furman, Peter A. Gruber, Jae-Woong Nah, Da-Yuan Shih
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Publication number: 20100230475Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Applicant: International Business Machines CorporationInventors: Stephen Leslie Buchwalter, Bruce K. Furman, Peter A. Gruber, Jae-Woong Nah, Da-Yuan Shih
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Patent number: 7765678Abstract: A method of bonding a metal ball for a magnetic head assembly is provided. The method comprises: preparing a capillary; disposing the capillary so as to face a bonding surface of the electrode pad of the slider and that of the electrode pad of the flexible printed circuit board; carrying the metal ball to the bonding surfaces by introducing the metal ball and the inactive gas stream into the carrying route of the capillary; positioning and retaining the metal ball on the bonding surfaces by the inactive gas stream passing through the carrying route and issued radially from the cutoff portions; and melting the metal ball by directly applying laser beams via the cutoff portions of the capillary, and bonding the electrode pad of the slider and the electrode pad of the flexible printed circuit board by the melted metal.Type: GrantFiled: June 30, 2006Date of Patent: August 3, 2010Assignee: TDK CorporationInventors: Ooki Yamaguchi, Takao Haino
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Patent number: 7753253Abstract: A dispensing device (4) for charging underfill agent into a gap between a substrate (K) and a chip (C) includes means for storing underfill agent (66, 67), a chamber (52) provided for containing substrate (K) to be charged with underfill agent and capable of being opened/closed, a dispenser (73) provided in the chamber (52) and discharging underfill agent introduced from the storing means (66, 67) into the gap between the substrate (K) and the chip (C), and a first pressure reducing means (46) for reducing the pressure in the chamber (52) at a predetermined vacuum pressure prior to the discharge of underfill agent by the dispenser (73). The dispensing device (4) can supply underfill agent with no bubbles to the substrate (K). A mounting system using this dispensing device (4) is also provided by the invention.Type: GrantFiled: November 9, 2006Date of Patent: July 13, 2010Assignee: Toray Engineering Co., Ltd.Inventors: Katsumi Terada, Takashi Takei
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Patent number: 7748116Abstract: A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material.Type: GrantFiled: April 5, 2007Date of Patent: July 6, 2010Inventor: John Trezza
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Publication number: 20100163605Abstract: A ball-implantation method and a system applying the method are provided. To begin with, solder balls are implanted onto a flux applied to each of the ball pads on a substrate plate. Then, a vibration force of preset magnitude is exerted on the substrate plate, inducing vibration and causing any solder balls that have deviated from positions corresponding to the ball pads exposed from the openings of a solder mask provided on the substrate plate to return to the correct orientation and be kept therein by the vibration force and gravity. Subsequently, the ball implantation process is completed using a reflow process to solder the implanted solder balls. Using this method and the system thereof, the problem of missing or misaligned solder balls that occurs after the reflow process is solved, thereby dispensing with rework and improving the production yield and product reliability.Type: ApplicationFiled: August 19, 2009Publication date: July 1, 2010Applicant: UNITED TEST CENTER INC.Inventor: Shiann-Tsong Tsai
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Patent number: 7743963Abstract: A solderable cover for solder attachment to an electronic substrate comprises a non-solderable cover defining an attachment pattern, a solderable metal layer in the shape of the attachment pattern, and a layer of adhesive bonding the solderable metal layer to the attachment pattern of the non-solderable cover, wherein the adhesive exhibits bond strength and resiliency sufficient to maintain the solderable metal layer attached to the non-solderable cover when raised in temperature to a melting temperature of a solder.Type: GrantFiled: February 28, 2006Date of Patent: June 29, 2010Assignee: Amerasia International Technology, Inc.Inventor: Kevin Kwong-Tai Chung
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Publication number: 20100155456Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: ApplicationFiled: August 5, 2009Publication date: June 24, 2010Applicant: International Business Machines Corp.Inventors: GARETH G. HOUGHAM, KAMALESH K. SRIVASTAVA, SUNG K. KANG, DA-YUAN SHIH, BRIAN R. SUNDLOF, S. JAY CHEY, DONALD W. HENDERSON, DAVID R. DI MILIA, RICHARD P. FERLITA, ROY A. CARRUTHERS
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Patent number: 7726543Abstract: A method for the production of a soldered joint between at least two contact partners (22, 23) of a bonding arrangement (21), with a formed piece of solder material (27) being arranged at a distance to the bonding arrangement. The formed piece of solder material is at least partially melted off. The at least partially melted off formed piece of solder material being thrust against a bonding arrangement in such a way that both bonding partners are wetted in a bonding area to establish an electrically conductive bonding.Type: GrantFiled: February 25, 2008Date of Patent: June 1, 2010Assignee: Smart Pac GmbH Technology ServicesInventor: Ghassem Azdasht
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Patent number: 7718927Abstract: A micro solder pot includes a dielectric substrate having at least one hole formed therein, a conductive coating coupled to the interior of the hole, and at least one heat transfer pad spaced from the hole in thermal communication with the conductive coating of the hole. When the heat transfer pad is exposed to a heat source, the conductive coating inside the hole is heated. The micro solder pot may also include a thermally activated conductive material disposed within the hole. When the heat transfer pad is exposed to a heat source, the thermally activated conductive material becomes liquidus such that a component can be inserted into the liquidus material. When the heat source is removed, the thermally activated conductive material cools to couple the component to the conductive coating in the hole.Type: GrantFiled: March 14, 2006Date of Patent: May 18, 2010Assignee: MEDCONX, Inc.Inventors: Harold B. Kent, James J. Levante, Aaron T. Fine, Joseph R. Layton
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Publication number: 20100116869Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.Type: ApplicationFiled: November 9, 2009Publication date: May 13, 2010Inventors: Stephen C. Jacobsen, David P. Marceau, Shayne M. Zurn, David T. Markus
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Patent number: 7712649Abstract: An electronic component mounting device according to the invention includes a bonding head for holding and pressure bonding an electronic component to a mounting substrate, a local stage provided with a support surface formed in an area which is almost equal to or slightly larger than that of a mounting surface of the electronic component and serving to support a pressure bonding force from an antimounting surface of the mounting substrate through the support surface, a length measuring mechanism for measuring a distance between the bonding head and the mounting substrate, thereby calculating a virtual plane in a predetermined mounting position on the mounting substrate, and a tilting and moving mechanism for tilting and moving the bonding head and the local stage, thereby causing a normal of the virtual plane in the mounting position to be coincident with an action line of the pressure bonding force, and the pressure bonding is carried out along the normal.Type: GrantFiled: June 26, 2008Date of Patent: May 11, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventor: Toshiyuki Kuramochi
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Publication number: 20100108117Abstract: A package is adapted to a thermoelectric module in which a plurality of thermoelectric elements is electrically connected in series and aligned between a lower electrode and an upper electrode and is constituted of a metal frame and a metal base which is a metal plate having good thermal conductivity composed of copper, aluminum, silver, or alloy. The metal frame is bonded onto the periphery of the metal base via a low melting point solder whose melting point is lower than that of the solder used for forming the thermoelectric module. The thermoelectric module is circumscribed by the metal frame so that the lower electrode thereof is attached onto the metal base via an insulating resin layer.Type: ApplicationFiled: October 28, 2009Publication date: May 6, 2010Applicant: YAMAHA CORPORATIONInventors: TETSUTSUGU HAMANO, Hiroyuki Yamashita, Naoshi Horiai
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Publication number: 20100108122Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.Type: ApplicationFiled: November 4, 2008Publication date: May 6, 2010Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
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Patent number: 7694868Abstract: Provided is a method and apparatus for mounting a plurality of electronic components. The method comprises mounting a first electronic component on a substrate; forming a mask on the substrate to expose the first electronic component and a region of the substrate on which a solder paste is to be applied; forming a guide on a portion of the mask disposed around the first electronic component; applying the solder paste onto the substrate by using a squeezer contacting a portion of the mask disposed around the region of the substrate on which the solder paste is to be applied; removing the guide and the mask; and mounting a second electronic component on the solder paste.Type: GrantFiled: December 2, 2008Date of Patent: April 13, 2010Assignee: Samsung Digital Imaging Co., Ltd.Inventors: Kyeong-heon Kim, Tae-hun Kim, Dong-hee Kim
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Patent number: 7677431Abstract: A large electronic device having a bonding area on one side that comprises first and second portions may be bonded by first locating the first portion but not the second portion of the electronic device for bonding by a bonding tool. After the first portion of the electronic device has been bonded, the electronic device is conveyed to a rotary platform that is rotatable along a substantially horizontal plane. The electronic device is rotated on the rotary platform to change the respective positions of the bonded first portion and unbonded second portion of the electronic device, before the electronic device is conveyed to the bonding tool such that the second portion of the electronic device is located for bonding by the bonding tool. The second portion of the electronic device may then be bonded.Type: GrantFiled: August 22, 2007Date of Patent: March 16, 2010Assignee: ASM Technology Singapore Pte Ltd.Inventors: Yam Mo Wong, Keng Yew James Song, Ka Shing Kenny Kwan
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Patent number: 7658001Abstract: A method for electrically connecting disk drive suspension assembly elements including positioning a first component having a first terminal with an edge adjacent to a second component having a second terminal and applying solder to form a solder joint over the edge of the first terminal and onto the second terminal. Heat to melt the solder is provided from a source that is physically remote from the components.Type: GrantFiled: November 6, 2007Date of Patent: February 9, 2010Assignee: Hutchinson Technology IncorporatedInventor: Galen D. Houk
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Publication number: 20090321501Abstract: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first semiconductor die may be electrically coupled to the substrate with a plurality of stitches in a forward ball bonding process. The second semiconductor die may in turn be electrically coupled to the first semiconductor die using a second set of stitches bonded between the die bond pads of the first and second semiconductor die. The second set of stitches may each include a lead end having a stitch ball that is bonded to the bond pads of the second semiconductor die. The tail end of each stitch in the second set of stitches may be wedge bonded directly to lead end of a stitch in the first set of stitches.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: XingZhi Liang, HaiBo Fang, Li Wang
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Patent number: 7635077Abstract: A method of forming a sensor for sensing a physical property of a media. A substrate is provided having circuitry thereon including at least one electrical contact and a die is provided having disposed thereon corresponding electrical contacts and a sensing element for sensing a physical property of a media applied to said sensing element. One or more bonding ring or portions are arranged on the die. The die electrical contact(s) and bonding ring(s) can be bonded substantially simultaneously, with conductive bonding material, to the corresponding substrate electrical contact(s) and a surface of said substrate, respectively, to thereby form a sensor. The bonding ring(s) form a pressure seal. The substrate can include corresponding bonding ring(s). The die can include an ASIC for compensating temperature effects on said pressure sensor.Type: GrantFiled: September 27, 2005Date of Patent: December 22, 2009Assignee: Honeywell International Inc.Inventor: Paul C. Schubert
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Publication number: 20090267227Abstract: A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These may be constructed in this manner initially or may be retrofitted plastic ball grid arrays from which the solder balls are removed and, the stiffener is attached to the top, and the solder columns have been added to replace the solder balls. The stiffener is a bonded thin metal or ceramic plate attached to the top of the PGA to maintain its flatness over temperature during the column attach process. An aluminum plate bonded to the top of a PGA results in a significant reduction in warping during a temperature cycle. This allows attachment of solder columns to the PBGA. The high melt solder columns are attached to an area array pattern on the PBGA substrate. This array is typically either a solid or perimeter grid.Type: ApplicationFiled: April 24, 2008Publication date: October 29, 2009Applicant: LOCKHEED MARTIN CORPORATIONInventors: Charles H. Dando, III, Stephen G. Gonya, William E. Murphy
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Patent number: 7596864Abstract: A method for soldering a soft wire to a printed circuit board conveniently includes the following step: providing a bracket having a through hole and an enameled wire; fastening the enameled wire to the bracket with the conductive wire crossing over the through hole; providing a printed circuit board formed with conductive pads thereon and setting the printed circuit board onto the bracket with the pad aligned to the through hole so that a portion of the magnet wire crossing the through hole lies on the conductive pad; providing a soldering tool having a thermal contact portion and inserting the thermal contact portion into the through hole to solder the magnet wire to the conductive pad.Type: GrantFiled: March 15, 2007Date of Patent: October 6, 2009Assignee: Hon Hai Precision Ind. Co., Ltd.Inventors: John Chow, Huan Chen, Chih-Min Lin
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Publication number: 20090230546Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.Type: ApplicationFiled: February 28, 2006Publication date: September 17, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventors: Shingo Komatsu, Seiichi Nakatani, Seiji Karashima, Toshiyuki Kojima, Takashi Kitae, Yoshihisa Yamashita
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Publication number: 20090224026Abstract: An electronic component mounting method that is to mount on a board 3 an electronic component 11 formed with solder bumps 16 on a lower surface thereof Solder paste 19 is printed onto the electrodes 3a of the board 3 and further provided onto the solder bumps 16 by transfer. Thereafter, the solder bumps 16 are put on the electrodes 3a through the solder paste 19. Due to this, even where there is a gap between the solder bump 16 and the electrode 3a, the fused portion of solder is increased in amount by the solder ingredient of the solder paste 19 wherein the fused portion of solder is ensured to wettably spread. This can prevent a poor junction when to mount a thin semiconductor package by soldering.Type: ApplicationFiled: August 16, 2006Publication date: September 10, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Yuusuke Yamamoto
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Patent number: 7578057Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.Type: GrantFiled: June 27, 2006Date of Patent: August 25, 2009Assignee: FormFactor, Inc.Inventors: Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
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Patent number: 7575148Abstract: A plurality of anode foils (7) and a plurality of cathode foils (8) respectively having connecting portions (12a, 12b) are alternately arranged with insulating separators (9) interposed therebetween. The connecting portions (12a, 12b) of the stacked electrode foils (7, 8) are respectively connected and united electrically and mechanically by friction stir welding, thereby forming a capacitor element (5). The capacitor element (5) is housed in a case (2), and the connecting portions (12a, 12b) are respectively connected to a positive electrode external terminal (4) and a negative electrode external terminal (4).Type: GrantFiled: March 19, 2004Date of Patent: August 18, 2009Assignee: Nippon Chemi-Con CorporationInventors: Tatsuo Kubouchi, Hitoshi Iwasaki, Makoto Shimizu
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Publication number: 20090200362Abstract: In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package.Type: ApplicationFiled: February 11, 2009Publication date: August 13, 2009Inventors: Ky-Hyun JUNG, Jae-Yong Park, Heui-Seog Kim, Wha-Su Sin, Jung-Hyeon Kim
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Publication number: 20090185096Abstract: A printed circuit board includes; first and second pads spaced apart from each other; and a dielectric region which surrounds the first and second pads, wherein each of the first and second pads includes a main region and an expansion region which extends from the main region, and wherein the main regions of the first and second pads are configured to have a first surface mount device mounted thereon, wherein the expansion regions and portions of the main regions which directly adjoin the expansion regions of the first and second pads are configured to have a second surface mount device mounted thereon, and wherein the first and second surface mount devices have different sizes.Type: ApplicationFiled: August 22, 2008Publication date: July 23, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yong-Eun PARK
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Patent number: 7559455Abstract: A titanium alloy strip which has a reduced cross section in the central region of the strip. By concentrating heat in this central region the process of bonding laser devices to a substrate is greatly improved. Furthermore, the titanium alloy strip allows for the possibility of removing the laser device from the substrate without destroying the laser device.Type: GrantFiled: July 18, 2006Date of Patent: July 14, 2009Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.Inventors: Maheshchandr Mistry, Christopher Main
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Publication number: 20090166339Abstract: The invention relates to a method for producing an electronic module (2) comprising a printed circuit (4) board (3), at least one first type of component (5), and a second type of component (6), said method comprising the following steps: solder is placed on the board; the first type of component is positioned; the solder is melted in order to solder the first type of component; the second type of component is positioned in such a way that it extends above the first type of component and has tongues (7) supported on the board by means of solder; and the solder is melted in order to solder the second type of component.Type: ApplicationFiled: February 15, 2007Publication date: July 2, 2009Applicant: VALEO SYSTEMES DE CONTROLE MOTEURInventors: Bruno Lefevre, Christian Schwartz, Jean-Yves Moreno
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Publication number: 20090166396Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Lakshmi SUPRIYA, Ravi NALLA
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Publication number: 20090152329Abstract: Provided is a method and apparatus for mounting a plurality of electronic components. The method comprises mounting a first electronic component on a substrate; forming a mask on the substrate to expose the first electronic component and a region of the substrate on which a solder paste is to be applied; forming a guide on a portion of the mask disposed around the first electronic component; applying the solder paste onto the substrate by using a squeezer contacting a portion of the mask disposed around the region of the substrate on which the solder paste is to be applied; removing the guide and the mask; and mounting a second electronic component on the solder paste.Type: ApplicationFiled: December 2, 2008Publication date: June 18, 2009Applicant: Samsung Techwin Co., Ltd.Inventors: Kyeong-heon Kim, Tae-hun Kim, Dong-hee Kim
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Patent number: 7543376Abstract: Provided is an FPC, which comprises an insulating layer 2, wiring layers 3 and 4 laminated above and under the insulating layer 2, and a layer connection for connecting the wiring layers 3 and 4 electrically. The layer connection is constituted to comprise: a conductor press-fit hole 5 of a cone shape extending through the insulating layer 2 and the upper and lower wiring layers 3 and 4 and expanded to the side of one wiring layer 3; and a conductor 6 filled and press-fitted without any clearance in the conductor press-fit hole such that it is jointed to the wiring upper layer 3 deformed into the cone shape of the conductor press-fit hole 5, and is protruded from the other wiring lower layer 4 to have its surface partially coated and jointed.Type: GrantFiled: January 12, 2007Date of Patent: June 9, 2009Assignee: Panasonic CorporationInventors: Toyokazu Yoshino, Katsuya Okamoto, Shigeki Ogata, Shinji Morimoto, Kouji Nakashima
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Publication number: 20090134204Abstract: A soldering method for soldering a semiconductor element to each of bonding portions defined at a plurality of locations on a circuit board is disclosed. The soldering method includes laying out the bonding portions in a non-linear manner in at least three locations on the circuit board, placing the semiconductor elements on the bonding portions with solder in between, placing a weight on the at least three semiconductor elements, which are laid out in a non-linear manner, so that the weight extends over the semiconductor elements, and soldering the semiconductor elements to the bonding portions by melting the solder while pressurizing the semiconductor elements with the weight. This reduces variations in thickness of the solder at the plurality of bonding portions when soldering the plurality of semiconductor elements to the circuit board.Type: ApplicationFiled: November 21, 2006Publication date: May 28, 2009Inventor: Masahiko Kimbara
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Publication number: 20090120680Abstract: A method of manufacturing a printed wiring board having at least one solder bump includes forming a solder resist layer on a conductor layer. The solder resist layer has at least one opening that exposes a connection pad of the conductor layer, and the at least one opening in the solder resist layer has a depth D, from the solder resist layer to the exposed connection pad, of from 3 ?m to 18 ?m. The method also includes loading a solder ball into each of the at least one opening in the solder resist layer, and forming a bump on the exposed connection pad by heating the solder ball to a reflow temperature.Type: ApplicationFiled: May 12, 2008Publication date: May 14, 2009Applicant: IBIDEN CO., LTDInventors: Katsuhiko Tanno, Youichirou KAWAMURA