Simultaneous Bonding Of Multiple Joints (e.g., Dip Soldering Of Printed Circuit Boards) Patents (Class 228/180.1)
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Patent number: 6457233Abstract: A solder bonding method comprises the step of solder bonding a first electrode 30 to a second electrode 16 having a solder bump 18 of mainly Sn formed on the upper surface thereof. The first electrode 30 and/or the second electrode 16 includes metal layers 14, 26 formed of an alloy layer containing Ni and P, an alloy layer containing Ni and B, or an alloy layer containing N, W and P. The metal layer of the alloy layer containing impurities, such as P, etc. can prevent the Ni of the metal layer from combining with the Sn in the solder bump. Accordingly, good bonded states can be obtained.Type: GrantFiled: December 3, 1999Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventor: Kozo Shimizu
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Patent number: 6449836Abstract: In interconnecting printed circuit boards: preparing a first and second printed circuit board is accomplished with the first having an insulating substrate of thermoplastic resin and a conductive pattern with a land, while the second has a conductive pattern with a land; overlapping the land of the first with the land of the second is done to form an interconnection portion; and heating the interconnection portion at a temperature approximately higher than a glass transition temperature of the thermoplastic resin while applying pressure to the interconnection portion to create an electrical interconnection sealed with a part of the thermoplastic resin constituting the insulating substrate of the first board is accomplished. The insulating substrate of the first board is overlapped with an insulating substrate of the second printed board to interpose a film, the film including material to reduce a modulus of elasticity of the insulating substrate of the first board.Type: GrantFiled: July 26, 2000Date of Patent: September 17, 2002Assignee: Denso CorporationInventors: Toshihiro Miyake, Katsuaki Kojima, Hiroyasu Iwama, Makoto Totani, Yoshitaro Yazaki, Takehito Teramae, Tomohiro Yokochi, Kenzo Hirano, Tomoyuki Nanami
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Patent number: 6448640Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.Type: GrantFiled: June 18, 2001Date of Patent: September 10, 2002Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 6443355Abstract: A soldering method and apparatus in which there is provided a tight contact cover tightly contacting a portion (unused portion) of a re-flow panel other than its portion facing a substrate to be soldered in such a manner as to suppress a hot wind tending to turn around to a part setting surface to diminish the thermal energy loss as well as to prevent the circuit quality from being lowered by the solder.Type: GrantFiled: November 9, 2000Date of Patent: September 3, 2002Assignee: Sony CorporationInventor: Arata Tsurusaki
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Patent number: 6421248Abstract: A chip card module contains, in addition to conductor tracks and a chip carrier, one or more semiconductor chips and, if necessary, a stiffening frame. The semiconductor chip(s) and/or stiffening frame are attached with the aid of an adhesive, with which particles of a defined size are admixed as spacers. The adhesive in preferably a flexible adhesive, and the particles preferably are formed of a deformable material. The invention has the effect that the semiconductor chip(s) and/or stiffening frame are adhesively attached to the underlying surface at a defined, uniform distance. The flexible adhesive and the deformable particles adapt to deformations of the chip card module and thus prevent damage to the adhesively bonded mating surfaces.Type: GrantFiled: July 15, 1999Date of Patent: July 16, 2002Assignee: Infineon Technologies AGInventors: Hans-Georg Mensch, Stefan Emmert, Detlef Houdeau
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Publication number: 20020084312Abstract: An apparatus, comprising a substrate having a surface, comprising one or more solder pads, each having a center and connected to a via, each via having a center; positioned relative to the surface such that at least one of the one or more solder pad centers is offset from the connecting via center and an area of the at least one of the one or more solder pads overlaps an area of the connecting via.Type: ApplicationFiled: December 29, 2000Publication date: July 4, 2002Inventors: Daniel E. Shier, Phil Geng, Scott N. Dixon
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Patent number: 6412165Abstract: A method of increasing the cycle life of a thermostatic disc element for use in a disc assembly used in thermostatic switches in which a weld slug is used to weld the disc element to the disc assembly thereby causing a heat affected zone of the disc element comprising the step of engaging the surface of the disc element opposite the surface adjacent the weld slug with a fulcrum member at a location spaced from the heat affected zone so that upon reversal of the curvature of the disc element, the disc element will bend about the fulcrum member at a location removed from the heat affected zone.Type: GrantFiled: April 23, 1998Date of Patent: July 2, 2002Assignee: Texas Instruments IncorporatedInventor: Sheldon S. White
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Patent number: 6402011Abstract: For reflow soldering, radiant heating is applied to one surface of a printed circuit board on which electronic components are placed and onto which cream solder is supplied and at the same time hot air is blown locally and roughly perpendicular to to-be-connected points on said one surface of the printed circuit board. This reflow method permits secure soldering even if the hot air is set at a temperature not exceeding the heat resistance of the electronic components, which is possilbe because of its combination with the radiant heat. Moreover, this reflow method can permit soldering in such a manner that only the to-be-connected points are heated selectively, because the hot air is blown locally and roughly perpendicular to the points to be connected. Thus, this reflow method prevents heat damage to other sections than the to-be-connected points and ensures that the solder at the to-be-connected points is melted.Type: GrantFiled: August 4, 2000Date of Patent: June 11, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Taniguchi, Kazumi Ishimoto, Koichi Nagai, Osamu Yamazaki, Tatsuaki Kitagawa, Osamu Matsushima, Kazuhiro Uji, Seizo Nemoto
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Patent number: 6396706Abstract: Separate heating elements are embedded in a printed circuit board near integrated circuit (IC) packages or other parts mounted on the circuit board. Each heating element supplies heat to the part residing near it in response to an input voltage pulse. The heating elements are used to selectively melt solder or adhesives attaching the parts to the circuit board so that they can be easily removed or to temporarily melt solder or cure adhesive when the parts are mounted on the circuit board. The heating elements are also used to supply heat to IC packages for regulating their operating temperatures.Type: GrantFiled: July 30, 1999Date of Patent: May 28, 2002Assignee: Credence Systems CorporationInventor: Paul D. Wohlfarth
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Publication number: 20020061490Abstract: The present invention relates to a reflow furnace for heating a carried circuit module to perform reflow soldering. The reflow furnace has a nozzle 60 for performing an operation of spraying the inert gas on a soldering portion for the circuit module carried into the furnace while the nozzle is moved, maintaining high mounting reliability and high productivity, even if apertures of the carrying inlet and the carrying outlet are large.Type: ApplicationFiled: January 17, 2002Publication date: May 23, 2002Applicant: FUJITSU LIMITEDInventors: Nobuyoshi Yamaoka, Kouichi Shimizu
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Patent number: 6392897Abstract: A circuit module includes a connector terminal (4A) provided on a front surface of a printed wiring board (2) and connected to a data pin (DQt) of a memory IC (3) through an interconnect line (5a). A conductive connector terminal (4c) corresponds to the connector terminal (4a) and is provided on a back surface of the printed wiring board (2). A through hole (16) extends between part of the front surface of the printed wiring board (2) where the connector terminal (4a) is formed and part of the back surface thereof where the conductive connector terminal (4c) is formed. A conductor fills the through hole (16), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.Type: GrantFiled: August 10, 1998Date of Patent: May 21, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasunobu Nakase, Tsutomu Yoshimura, Yoshikazu Morooka, Naoya Watanabe
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Patent number: 6391468Abstract: Solder paste is deposited using a solder stencil with an aperture having a concave edge in order to reduce the formation of solder balls. The solder deposit may be formed on a pad such that the paste has a concave edge. Solder paste deposits may be made on adjacent pads with the concave surfaces facing one another.Type: GrantFiled: March 30, 2001Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: Richard Regner, Scott Butler, Carey Blue
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Patent number: 6386429Abstract: The printed circuit board (PCB) header attachment station mounts a header (PCB) onto a PCB having preexisting solder joints, such as underneath a direct mount IC chip. The apparatus applies a soldering paste to PCB lands configured to receive the pins of the header; nests the header component in stacked alignment with the PCB in order to bring the header pins into contact with the respective PCB lands; heats the PCB to a temperature approaching the reflow temperature of the solder in the pre-existing PCB solder joints; and actuates a compliant heating block or bar to heat the header pins to an extent sufficient for the pins to conduct enough heat to locally reflow the solder on the corresponding PCB lands without reflowing the solder in the pre-existing solder joints. The local reflow of the solder precludes solder reflow in the surrounding pre-existing joints which may coalesce under the direct mount IC chip and render the PCB defective.Type: GrantFiled: September 18, 2000Date of Patent: May 14, 2002Assignee: Calestica International Inc.Inventors: Paymon Sani-Bakhtiari, David Lekx
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Patent number: 6382500Abstract: When soldering semiconductor devices in a solder reflow furnace flux is vaporized and carried to the furnace exhaust pipe. The flux condenses on the walls of the exhaust pipe and drips back into the furnace contaminating production parts. A solder reflow furnace with a flux effluent collector prevents flux drip-back. The flux effluent collector has an exhaust gas heater that maintains flux effluent in a gaseous state, a flux cooler, to subsequently condense flux, and a flux condensation region where the flux condenses. The flux condensation region is offset from the furnace's exhaust opening so that condensed flux cannot drip back into the furnace.Type: GrantFiled: August 22, 2000Date of Patent: May 7, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Raj N. Master, Mohammad Zubair Khan, Maria Guardado, Sp Lee, Sofi Mohd
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Patent number: 6380060Abstract: A method of placing solder balls on a connection component includes providing a dielectric element having first conductive elements on a first surface, second conductive elements on a second surface, and conductive vias electrically interconnecting one or more of the first conductive elements and one or more of the second conductive elements. The first conductive elements may include conductive pads overlying the first surface of the dielectric element and the second conductive elements may include conductive leads or traces overlying the second surface of the dielectric element. Each via may have an opening at the first surface of the dielectric element. One or more of the vias may also have a closed end adjacent the second surface of the dielectric element. The via openings preferably extend through the first conductive elements.Type: GrantFiled: August 31, 2000Date of Patent: April 30, 2002Assignee: Tessera, Inc.Inventor: Wael Zohni
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Patent number: 6378762Abstract: A cream solder printing apparatus is disclosed which includes a positioning unit for positioning a workpiece 1, a mask 9 having a plurality of opening portions 31, a filling unit for filling cream solder 11 in the opening positions, a pressurizing unit composed of a pressure head 12 having a pressure container 13 and a gas charge/discharge pipe 14, a position registration unit for aligning the workpiece, the mask and the pressure head, and a moving means for peeling the mask away from the workpiece. A lower surface 27 of said pressure head has holes at positions corresponding to the opening portions.Type: GrantFiled: June 22, 2000Date of Patent: April 30, 2002Assignee: Athlete FA CorporationInventors: Masao Takeuchi, Yoshiharu Fujimori, Chuji Tomita
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Patent number: 6378758Abstract: A microelectronic connection component is provided with leads having a surface wettable by a bonding material such as a solder at the tips of the leads which are intended to be bonded with microelectronic devices. The leads have non-wettable surfaces bounding the wettable surfaces. During bonding, the non-wettable surfaces confine liquid bonding material such as liquid solder and prevent the liquid bonding material from spreading along the leads.Type: GrantFiled: January 19, 1999Date of Patent: April 30, 2002Assignee: Tessera, Inc.Inventor: Belgacem Haba
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Publication number: 20020047038Abstract: A circuit assembly having a thin and large-area dielectric substrate and an improved earthing condition. To make the assembly, a circuit board comprising the substrate, and a circuit pattern and a metal layer that are formed on respective sides of the substrate. A bath of conductive bonding material (e.g., a low melting point solder) is made inside a tray-like metal chassis of the assembly. The circuit board is floated on the bath and excessive portion of the conductive material is absorbed. A branch circuit for branching a first path into at least two second paths is provided by mainly using impedance transformers but by using fewest possible stub(s). Also, the elements are arranged in symmetry around the axis through the first path. This yields a wide operating frequency band. A waveguide-microstrip line transition that is easy to work and low in transition loss is provided by shaping the wider walls of the ridge waveguide so as to spread out toward the end.Type: ApplicationFiled: November 15, 2001Publication date: April 25, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Ushio Sangawa, Suguru Fujita
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Patent number: 6375064Abstract: A conductive paste is loaded in circular holes made in a reinforcing film of a carrier tape which includes a film substrate and the reinforcing film, followed by applying a heat treatment to the conductive paste to form projecting electrodes consisting of solder. Then, the reinforcing film is peeled off to permit the projecting electrode to project from the film substrate.Type: GrantFiled: March 15, 2000Date of Patent: April 23, 2002Assignee: Casio Computer Co., Ltd.Inventors: Kenji Edasawa, Shiro Ozaki, Kazuhiro Sugiyama, Isao Kurashima
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Patent number: 6374487Abstract: A connector for microelectronic elements includes a sheetlike dielectric layer having a plurality of through holes desirably arranged in a rectangular grid pattern. Each hole is provided on one major surface with a generally laminar contact having at least one projection extending inwardly over the through hole. Contact pads on the second major surface of the dielectric layer overlie the through holes to provide a blind end which is electrically connected to the other contact by means of a metal layer lining the through hole. The resulting connectors provide low or zero insertion force sockets for mounting microelectronic elements having bump leads thereto. The bump leads may be received within corresponding sockets without engagement with the contact or projection, and then, by movement in a lateral direction, engaging the contact or projection to provide electrical connection to the socket.Type: GrantFiled: June 8, 2000Date of Patent: April 23, 2002Assignee: Tessera, Inc.Inventors: Belgacem Haba, Anthony B. Faraci
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Patent number: 6367150Abstract: An epoxy-based soldering flux is used to solder a flip-chip IC device to a metallic bond site on a substrate material. The soldering flux is composed of a thermosetting epoxy resin and a cross-linking agent with inherent flux activity. When heated the cross-linking agent cleans the metal oxides from the metal surfaces on the chip and then reacts with the epoxy resin to form a thermosetting epoxy residue. The flux residue left on the board after soldering does not inhibit the flow of an underfill encapsulant. The underfill binds to the thermosetting residue of the flux which increases adhesion strength preventing delamination of the chip during thermal cycling.Type: GrantFiled: September 4, 1998Date of Patent: April 9, 2002Assignee: Northrop Grumman CorporationInventor: Kenneth J. Kirsten
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Patent number: 6352192Abstract: A system (5) and method are used for predicting and controlling the temperature of a semiconductor wafer (10) during a solder reflow process by controlling the operating profile of a solder reflow furnace (14). The emissivity of the surface of the wafer (10) is measured using an infrared device (11) prior to the solder reflow process. Using the measured emissivity value of the wafer (10), the peak temperature of the wafer (10) is predicted, and the operating profile of the solder reflow furnace (14) is adjusted accordingly to achieve a desired temperature profile of the wafer (10). A process for reflowing solder on a semiconductor wafer calculates a predicted peak temperature of a semiconductor wafer (10) and controls the actual temperature of the wafer (10) during a solder reflow process by controlling the operating profile of a solder reflow furnace (14).Type: GrantFiled: February 29, 2000Date of Patent: March 5, 2002Assignee: Motorola, Inc.Inventors: Tien-Yu Tom Lee, James Vernon Hause, Li Li
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Patent number: 6347039Abstract: A memory module includes a plurality of semiconductor memory devices mounted on a printed wiring board (PWB); longitudinal contact terminals that are for connection to a computer mother board and are arranged along at least one longitudinal edge of the PWB; and transverse contact terminals that are for connection to the computer mother board and are arranged along at least one transverse edge of the PWB. A socket for the module includes at least one longitudinal part into which the longitudinal contact terminals are inserted and at least one transverse part into which the transverse contact terminals are inserted. Each transverse socket part can be mounted on a pivot attached to the longitudinal part and rotated to engage a PWB inserted in the longitudinal part. Alternatively, each transverse part can be a flexible circuit carrier.Type: GrantFiled: July 30, 1999Date of Patent: February 12, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Jung Joon Lee
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Publication number: 20020014518Abstract: Lands formed on a flexible printed circuit board are electrically connected with lands formed on a rigid printed circuit board through solder. At this point, solder resist is formed between neighboring two lands on the rigid printed circuit board, and is terminated with an end portion that is interposed between the rigid printed circuit board and the flexible printed circuit board. Accordingly, even when surplus solder is extruded onto the rigid printed circuit board, the solder resist can prevent solder bridges from being formed between the lands.Type: ApplicationFiled: July 19, 2001Publication date: February 7, 2002Inventors: Makoto Totani, Toshihiro Miyake, Tomohiro Yokochi, Takehito Teramae, Yoshitaro Yazaki, Kazuyuki Deguchi, Hajime Nakagawa
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Publication number: 20020003160Abstract: A method of fabricating solder assemblies for forming solder connections that include a dielectric base having a non solder-wettable surface, a plurality of solderwettable pads exposed to said surface, and an electrically conductive potential plane element having a non solderwettable surface overlying the surface of the base in proximity to the pads but spaced from said pads. The nonwettable surface of the potential plane element may include a metal such as nickel or a metal oxide. The potential plane element thus performs the functions of a solder mask to prevent solder from forming short circuits between adjacent pads, and may also act as a ground plane, power plane or shielding element.Type: ApplicationFiled: August 30, 2001Publication date: January 10, 2002Inventors: Masud Beroz, Belgacem Haba
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Publication number: 20020001787Abstract: A facility for the thermal treatment of workpieces has a processing or heating chamber and at least one transport device, extending essentially completely through the processing or heating chamber, with which the workpieces to be treated can be transported through the processing or heating chamber. At least two processing or heating levels are hereby located on top of one another in the processing or heating chamber, with each processing or heating level having at least one separate transport device. This type of facility can preferably be used as a soldering facility, particularly a reflow soldering facility, or as a facility for the hardening or drying of plastics or adhesives.Type: ApplicationFiled: June 28, 2001Publication date: January 3, 2002Inventors: Rainer Kurtz, Bernd Schenker, Richard Kressmann
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Patent number: 6334569Abstract: A reflow soldering apparatus for soldering a first component mounted on a substrate with a first solder having a first melting point and soldering a second component mounted on the substrate with a second solder having a second melting point higher than the first melting point. The reflow soldering apparatus includes a heat source for substantially uniformly heating the substrate, a capsule for enclosing the second component, and a vacuum pump for decreasing the pressure in the capsule. The melting point of the second solder can be lowered by operating the vacuum pump to decrease the pressure in the capsule by a given amount, so that the first component and the second component can be reflow-soldered at substantially the same temperature.Type: GrantFiled: March 31, 2000Date of Patent: January 1, 2002Assignee: Fujitsu LimitedInventor: Hideaki Yoshimura
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Patent number: 6332568Abstract: A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.Type: GrantFiled: January 16, 2001Date of Patent: December 25, 2001Assignee: Sandia CorporationInventor: Todd R. Christenson
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Publication number: 20010042775Abstract: A soldering flux includes a non-acidic resin in an aqueous composition. The flux can also include an activating agent and a surface-active agent that promotes surface wetting.Type: ApplicationFiled: December 1, 2000Publication date: November 22, 2001Inventors: Sanyogita Arora, Alvin F. Schneider, Karen A. Tellefsen
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Patent number: 6315189Abstract: A method and apparatus for uniformly solder plating leads on semiconductor packages wherein the leads are rotated during the solder plating process and the solder on the leads in planarized and solder between and bridging the leads is removed by the application of a hot gas to the device having the leads. The hot gas is preferably N2 which is inert to the process flow at the point in the process when it is utilized.Type: GrantFiled: October 13, 1999Date of Patent: November 13, 2001Assignee: Texas Instruments IncorporatedInventor: Charles E. Williams
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Patent number: 6305596Abstract: A method for breaking off solder bridges between pins of a through-hole component on a printed circuit board, comprises the following steps: (1) providing a soldering apparatus, the apparatus having an opening corresponding to the through-hole component, the opening defining an opening wall surface, providing a slit at a predetermined position of the opening wall surface; and (2) blowing a gas of a predetermined temperature and a predetermined pressure at a predetermined time to the position of the solder bridges through the slit for removing the solder bridges from the through-hole component.Type: GrantFiled: December 23, 1998Date of Patent: October 23, 2001Assignee: Asustek Computer Inc.Inventors: Shui-Town Lin, Shih-Ren Chuang
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Publication number: 20010022316Abstract: In order to solder a lead wire of an electronic device to a wiring pattern formed on a printed circuit board, the electronic device is first placed on a first face of the printed circuit board such that the lead wire thereof are protruded from a second face of the printed circuit board, on which the wiring pattern is formed. Then cream solder is coated on the protruded lead wire. On the other hand, there is provided a liquefied heat medium having a temperature higher than a melting temperature of the cream solder. The second face of the printed board is immersed in the liquefied heat medium in a predetermined time period, to melt the cream solder. Finally, the printed board is lifted from the liquefied heat medium.Type: ApplicationFiled: March 13, 2001Publication date: September 20, 2001Inventor: Takatsugu Matsudome
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Patent number: 6292372Abstract: An improved robber or solder thieving pad, parallelogram shaped, significantly reduces solder bridging in wave soldered multi leaded through hole or surface mounted components in a printed circuit board for different wave settings. The component leads are either parallel or perpendicular to the solder wave during the soldering process. In one embodiment, the parallelogram shaped solder thieving pad is disposed contiguous or adjacent to the through hole. In another embodiment, the parallelogram shaped solder thieving pad is spaced from a thin annular ring surrounding the through-hole. In still another embodiment, the pad may be linked to the ring by a thin connecting bridge. Dimensions of the solder thieving pad vary according to the component lead size, spacing, and number of rows.Type: GrantFiled: July 15, 1999Date of Patent: September 18, 2001Assignee: Lucent Technologies, Inc.Inventors: Kon M. Lin, Quentin D. Groves, Albert W. Robinson
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Patent number: 6279814Abstract: A punching pin of a soldering apparatus cuts out a solder piece from a solder plate onto a feeder pin, and the feeder pin presses the solder piece against a predetermined junction of a conductive wiring pattern incorporated in a printed circuit board; then, an electric circuit component is mounted on the printed circuit board, and is strongly soldered to the conductive wiring pattern, because the punching pin and the feeder pin supply a fixed amount of solder to the predetermined junction.Type: GrantFiled: June 23, 1999Date of Patent: August 28, 2001Assignee: Yamaha CorporationInventors: Akifumi Inoue, Koshiro Takeda
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Publication number: 20010015373Abstract: A connector for use with a circuit substrate having a plurality of elongated conductors. A solder ball is fused to the end of the conductors for connection of the connector to a circuit substrate. Method for attaching the solder ball to the end of the conductors using a solder paste with or without a preformed solder ball. The conductors are fitted into passages of an interface member. A tail end of each conductor terminates in a well in a surface of the interface member that facilitates the attachment of solder ball to the end of the conductors. The passages in the interface member hold the conductor tail ends in place while providing a clearance around the conductor to accommodate the effects of thermal expansion and contraction.Type: ApplicationFiled: April 30, 2001Publication date: August 23, 2001Inventor: Stanley W. Olson
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Publication number: 20010013535Abstract: The present invention provides a circuit board connecting method that includes an alkane application step and a heat-press-bonding step. The alkane application step is a preliminary step which applies an alkane group to a printed circuit board. The heat-press-bonding step heat-press-bonds a flexible circuit board to the printed circuit board by positioning their printed wire terminals and conductive thick-film terminals to face one another. In the heat-press-bonding step, the alkane group boils and cleans the surface of the printed wire terminals and conductive thick-film terminals, thereby removing the oxide film to expose the metallic portion of the terminals. The alkane group soaks into a thermoplastic film or base plate, causing it to swell and thereby bond the flexible circuit board to the printed circuit board tightly. Accordingly, both electrical and mechanical firm bonding is accomplished at a very low cost and short time.Type: ApplicationFiled: December 20, 2000Publication date: August 16, 2001Inventors: Toshihiro Miyake, Koichi Shigematsu, Kazuya Sanada, Hideharu Ishihara, Yoshitaro Yazaki
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Patent number: 6273327Abstract: A stencil (34) facilitates application of solder material (48) to a circuit board (10) carrying a through-hole component (14, 16, 18, 20, 22) and to which a surface mount component is to be mounted. The stencil (34) has a first surface (38) and a second surface (40). The second surface (40) is engageable to a surface (28) of the circuit board (10) having a plurality of electrically conductive pads (30, 32). At least one first aperture (42) is formed between the first and second surfaces (38, 40)of the stencil (34). The stencil (34) has a first thickness (T1) adjacent the first aperture (42) for depositing a first amount of solder material (48) within the first aperture (42) and around a component lead (24) extending from the through-hole component (14, 16, 18, 20, 22) into the first aperture (42). At least one second aperture (44) is formed between the first and second surfaces (38, 40) of the stencil (34).Type: GrantFiled: June 16, 1999Date of Patent: August 14, 2001Assignee: TRW Inc.Inventors: Neil Gordon Murray, Jr., Geoffrey A. Wright
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Patent number: 6270000Abstract: In a wire bonding method for connecting first and second bonding points, after bonding a primary ball to a first bonding point and then the wire to the second bonding point, a secondary ball is formed by electrical charge on a tail end of a wire that extends out of the tip end of a capillary, this secondary ball is ball-bonded to an arbitrary point near the second bonding point, and then the wire is cut so as to leave a tail of wire out of the tip end of the capillary. A primary ball is formed at the end of the tail by electrical discharge and is bonded to a next first bonding point.Type: GrantFiled: March 2, 2000Date of Patent: August 7, 2001Assignee: Kabushiki Kaisha ShinkawaInventor: Shinichi Nishiura
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Patent number: 6264094Abstract: A method and apparatus for desoldering electronic components from a substrate. A vacuum is used to enhance the flow of a hot gas under an electronic component to reflow the solder connections attaching the electronic component to a substrate. Water vapor is added to the hot gas to increase the heat capacity of the hot gas. A system for periodically changing the direction of flow of the hot gas and vacuum under the electronic component is used to uniformly heat the solder connections. A method and apparatus for depositing underfill material between an electronic component and the substrate on which the electronic component is mounted. A vacuum is applied to enhance the flow of underfill material into the space between the electronic component and the substrate.Type: GrantFiled: February 23, 2000Date of Patent: July 24, 2001Assignee: International Business Machines CorporationInventors: Wilton L. Cox, Joseph D. Poole, Kris A. Slesinger
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Patent number: 6264093Abstract: The present invention provides a method for soldering components to a printed wiring board. In one embodiment, the method comprises applying a substantially lead-free solder to the printed wiring board, placing an electronic component having lead-free terminals on the solder, and heating the printed wiring board in a substantially oxygen-free atmosphere to a temperature sufficient to reflow the solder. In an alternative embodiment, the method may further comprise applying a tin-based solder. In a particularly advantageous embodiment, the method includes applying a solder alloy of tin and a metal selected from the group consisting of: silver, antimony, copper, and gold.Type: GrantFiled: November 2, 1998Date of Patent: July 24, 2001Inventors: Raymond W. Pilukaitis, Yi T. Shih, Thang D. Truong, William L. Woods
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Publication number: 20010007330Abstract: In a ball mount apparatus for mounting balls on a work by means of a mount head, the work is disposed under the mount head and the mount head is provided with a Z-axis driving mechanism for driving the mount head only in an up/down direction. A ball tray for storing the balls is disposed at a height between the mount head and the work and provided with a driving mechanism for reciprocating between a ball sucking position under the mount head and a stand by position.Type: ApplicationFiled: October 12, 1999Publication date: July 12, 2001Inventor: YOSHIHISA KAJII
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Patent number: 6250539Abstract: A method, which is for forming accurate low wire loop shapes or short wire loop shapes which are stable and which have a high shape retention force in devices in which height differences between first and second bonding points are small and the wiring distance is short, including the steps of bonding a ball formed at the end of the wire extending out of the capillary to the first bonding point, raising the capillary while delivering the wire, moving the capillary toward the second bonding point, and then raising the capillary diagonally upward.Type: GrantFiled: September 29, 1999Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ShinkawaInventors: Shinichi Nishiura, Tooru Mochida
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Patent number: 6248452Abstract: Solder paste is deposited using a solder stencil with an aperture having a concave edge in order to reduce the formation of solder balls. The solder deposit may be formed on a pad such that the paste has a concave edge. Solder paste deposits may be made on adjacent pads with the concave surfaces facing one another.Type: GrantFiled: April 17, 2000Date of Patent: June 19, 2001Assignee: Micron Technology, Inc.Inventors: Richard Regner, Scott Butler, Carey Blue
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Patent number: 6249047Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.Type: GrantFiled: September 2, 1999Date of Patent: June 19, 2001Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Publication number: 20010001889Abstract: An alignment weight is provided. The alignment weight includes a body of material having first and second opposing surfaces. A number of depressions are formed in the first surface. The depressions receive pins of a floating pin field when placed on a floating pin field during connection of the floating pin field to a printed circuit board.Type: ApplicationFiled: January 4, 2001Publication date: May 31, 2001Applicant: Intel Corporation.Inventors: Cheryl M. Waldron-Floyde, Brad C. Irwin
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Patent number: 6234380Abstract: Apparatus for inerting a wave soldering installation having a solder bath and a conveying system for producing one or more solder waves, in particular for soldering electric printed circuit boards, having an immersion box which is closed on all sides, shaped like a frame, can be immersed in the solder bath and which has porous pipes to distribute nitrogen, the pipes being arranged inside the immersion box in cage-like housings with outlet openings, the cage-like housings being designed such that the porous pipes are arranged therein in such a way that the porous pipes essentially cannot be struck by solder splashes produced during the operation of the wave soldering installation.Type: GrantFiled: February 12, 1999Date of Patent: May 22, 2001Assignee: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventor: Fernand Heine
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Patent number: 6229124Abstract: A new apparatus for inductively soldering surface-mount, straddle-mount and through-hole type electronic components into a self-soldering PCB (printed circuit board) in an automated fashion utilizing localized Electromagnetic Induction Heating (E.I.H.). Current manufacture technology for packaging electronic components depends on the reflow and wave soldering processes. Both processes heat up to relatively high temperatures the entire assembly, namely its PCB and all the electronic components being soldered into it. Such harsh high-temperature environment frequently causes components damage resulting in rejects and/or demanding rework. With this invention reflow oven and/or wave soldering equipment is not required. During a soldering operation only the leads and pads being soldered are heated but neither the body of said electronic components nor the dielectric material forming said self-soldering PCB and its interconnecting traces are heated.Type: GrantFiled: February 10, 2000Date of Patent: May 8, 2001Inventor: Horacio Andrés Trucco
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Patent number: 6223973Abstract: An apparatus and method for connecting together first and second printed circuit boards 10/20 (PCBs), wherein one or both of the PCBs is a flex circuit. The method includes overlapping the two PCBs such that their respective matching circuit trace arrays 12/22 face each other and are separated by a small predetermined distance K, and then introducing molten solder 30 proximate an overlapping PCB edge 18, such as by wave soldering, so as to urge capillation of the molten solder between the two PCBs, thereby forming solder joints operatively connecting together the two circuit trace arrays.Type: GrantFiled: November 16, 1999Date of Patent: May 1, 2001Assignee: Visteon Global Technologies, Inc.Inventors: Stephen H. P. Wong, Billy Kiang
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Patent number: 6202299Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.Type: GrantFiled: December 11, 1998Date of Patent: March 20, 2001Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
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Patent number: 6202917Abstract: An electronic assembly is fabricated by tinning a solder to the electrical bonding pads of a printed circuit board, and applying an adhesive, preferably a filled polyurethane adhesive, to the component that is to be bonded to the printed circuit board. The component is contacted to its bonding location on the printed circuit board, and the electrical contact on the component is contacted to the tinned bonding pads. The assembly is heated in a single solder temperature/time reflow cycle to simultaneously cure the adhesive and solder the electrical contacts to the bonding pads.Type: GrantFiled: August 19, 1998Date of Patent: March 20, 2001Assignee: Hughes Electronics CorporationInventors: Mark A. Weaver, Lynn E. Long, Thomas Martinez, Eric J. Shinaver