Simultaneous Bonding Of Multiple Joints (e.g., Dip Soldering Of Printed Circuit Boards) Patents (Class 228/180.1)
  • Patent number: 7357288
    Abstract: When a component, that has a connection portion to be connected to an electrode of a board and a weak heat-resistant portion of a lower heat-resisting property than a fusing point of a connection material for connecting the electrode of the board with the connection portion, is connected to the board with interposition of connection material between the electrode of the board and the connection portion, a cooling member is brought into contact with the weak heat-resistant portion or its neighborhood while heating the connection material by heating the board brought in contact with a placement member, and a quantity of heat conducted to the weak heat-resistant portion via the board is reduced by being conducted to the cooling member, thereby performing fusing of the connection material while preventing occurrence of thermal damage to the weak heat-resistant portion.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: April 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoto Hosotani, Kazuki Fukada, Keiichi Iwata, Daido Komyoji
  • Patent number: 7345361
    Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Kinya Ichikawa, Terry L. Sterrett, Johanna Swan
  • Patent number: 7311241
    Abstract: A printed board is arranged above solder blowing nozzles of a spot flow soldering apparatus with first terminal groups facing upward, second terminal groups projected toward the solder blowing nozzles are shielded by shield jigs, solder jetted from the solder blowing nozzles solders soldered portion of the first terminal groups to a first conductor on a back side of the printed board, then the printed board is turned upside down to put the second terminal groups in an upward facing state and to use a jig to shield the first terminal groups facing downward, and solder jetted from the solder blowing nozzles solders soldered portion of the second terminal groups to a second conductor on a front side of the printed board.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: December 25, 2007
    Assignees: Sumitomo Wiring Systems, Ltd., Daihatsu Motor Co., Ltd.
    Inventors: Shunji Taga, Kazuhiro Nakanishi
  • Patent number: 7311240
    Abstract: Exemplary methods for making a solder joint between two articles are disclosed. The method includes the steps of positioning a first article and a second article to be soldered together. At least one of the first article and the second article has at least one button attached to it. The button has a desired height above a surface of the article to which it is attached. The second article has a quantity of solder located in a position where the solder joint is to be formed. A heat source is applied until the quantity of solder liquefies. The heat source is removed until the solder solidifies with a uniform thickness approximately equal to the height of the button.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 25, 2007
    Assignee: Finisar Corporation
    Inventors: Kinya Nippa, Wei Hong Soh
  • Patent number: 7308129
    Abstract: A characteristic amount calculating device for soldering inspection. The characteristic amount calculating device includes a design information inputting section for inputting design information of an inspection object, an inspection standard inputting section for inputting an inspection standard, a solder shape calculating section for calculating shape information of a solder fillet according to the design information, and an inspection image calculating section for calculating an inspection image according to the shape information.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: December 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatomo Maida, Shuzo Igarashi
  • Patent number: 7263769
    Abstract: A multi-layered flexible print circuit board comprising an insulating layer, a circuit layer formed on the front and back surfaces of the insulating layer and a hole connecting between the circuit layers via the insulating layer, wherein there is provided an electrically-conductive member having a metal layer formed thereon at least on the surface thereof which is press-fitted into the hole to electrically conduct the circuit layer.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: September 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Morimoto, Kouji Nakashima, Toyokazu Yoshino, Katsuya Okamoto
  • Patent number: 7260890
    Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided liquid crystalline polymer LCP where both the high and low temperature LCP are drilled to form a z-axis connection. The single sided conductive layer is a bus layer to form z axis conductive stud within the high and low temperature LCP, followed by a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis connection. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: August 28, 2007
    Assignee: Georgia Tech Research Corporation
    Inventors: George E. White, Madhavan Swaminathan, Venkatesh Sundaram, Sidharth Dalmia
  • Patent number: 7251880
    Abstract: A method and apparatus are provided for determining whether solder used during assembly of a printed circuit board is lead-free or not. This may include providing a pad on the printed circuit board and placing solder on the pad in a predetermined pattern. The solder may be heated so as to create reflow. The solder may later be examined to determine if the solder is lead-free.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar
  • Patent number: 7216794
    Abstract: A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an ultrasonic bond capillary (102) and clamping the ribbon wire against an engagement surface (120) of the bond capillary via a clamping jaw (118) operably coupled to the bond capillary. The ribbon wire (104) is bonded to the workpiece (106) along a bonding surface (112) of the bond capillary (102) and penetrated, at least partially, between the bonding surface and the engagement surface (120) of the bond capillary by a cutting tool (124). The cutting tool (124) may comprise an elongate member (126) positioned between the bonding surface (112) and engagement surface (120), and may have a cutting blade (128) positioned at a distal end (130) thereof. The cutting tool (124) may further comprise a ring cutter (132), wherein the ribbon wire passes through a ring (134) having a cutting surface (138) defined about an inner diameter thereof.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: May 15, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard P. Lange, Steven Alfred Kummerl
  • Patent number: 7197819
    Abstract: A method of assembling and providing an electric power apparatus. The method uses a heat resistant housing having a structure adapted to accommodate and retain a power circuit card and also including a bracket adapted to accommodate and constrain a rigid conductive member. A power circuit card having an electrical terminal is placed into the housing and a rigid conductive member into the bracket. The rigid conductive member is flow soldered to the electrical terminal, thereby exposing the heat resistant housing to heat and creating a solder bond. Finally, the rigid conductive member is affirmatively connected to the housing. The bracket constrains the rigid conductive member so that the act of affirmatively connecting does not weaken the solder bond.
    Type: Grant
    Filed: December 18, 2004
    Date of Patent: April 3, 2007
    Assignee: Rinehart Motion Systems, LLC
    Inventors: Lawrence E. Rinehart, Guillermo L. Romero
  • Patent number: 7094993
    Abstract: An apparatus for heating and cooling an article is provided. The apparatus comprises an enclosure having top, bottom, and side walls and an entrance and an exit. A first belt system comprising one or more belts extends from a loading position through a portion of the enclosure. The first belt system has a loading end and an unloading end. A second belt system comprising one or more belts extends from the unloading end of the first belt system to an unloading position. The second belt system has a loading end and an unloading end. The enclosure includes one or more heating sources positioned adjacent the first belt system for heating the first belt system.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: August 22, 2006
    Assignee: Radiant Technology Corp.
    Inventors: Carson T. Richert, Luis Alejandro Rey Garcia, Dienhung D. Phan, Selina De Rose-Juarez, Andrei Szilagyi
  • Patent number: 7070084
    Abstract: An electrical circuit apparatus (300) that includes: a substrate (330) having a ground layer (336), at least one thermal aperture (332), and at least one solder aperture (334); a heat sink (310); and an adhesive layer (320) for mechanically coupling the heat sink to the ground layer of the substrate such that at least a portion of the at least one substrate thermal aperture overlaps the heat sink, the adhesive layer having at least one thermal aperture (322) and at least one solder aperture (324), wherein aligning the at least one substrate solder aperture with the at least one adhesive layer solder aperture and aligning the at least one substrate thermal aperture with the at least one adhesive layer thermal aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: July 4, 2006
    Assignee: Motorola, Inc.
    Inventors: John M. Waldvogel, Brian R. Bielick, Herman J. Miller, Billy J. Van Cannon
  • Patent number: 7063249
    Abstract: An electrical circuit apparatus (300) that includes: a substrate (330) having a ground layer (336), at least one device aperture (332), and at least one solder aperture (334); a heat sink (310); and an adhesive layer (320) for mechanically coupling the heat sink to the ground layer of the substrate such that at least a portion of the substrate device aperture overlaps the heat sink, the adhesive layer having at least one device aperture and at least one solder aperture, wherein aligning the at least one substrate solder aperture with the at least one adhesive layer solder aperture and aligning the at least one substrate device aperture with the at least one adhesive layer device aperture enables solder wetting in a predetermined area between the heat sink and the ground layer of the substrate.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: June 20, 2006
    Assignee: Motorola, Inc.
    Inventors: John M. Waldvogel, Brian R. Bielick, Herman J. Miller, Billy J. Van Cannon
  • Patent number: 7036217
    Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
  • Patent number: 6995342
    Abstract: Disclosed are an apparatus and a method for bonding electronic components, a circuit board, and an electronic component mounting apparatus, whereby various kinds of circuit boards can be manufactured, each by a small amount, with high productivity as compared with the conventional art. There are provided a stage member and a heating device, so that a circuit board is heated by the heating device while held in contact with the stage member, which stage member has a size almost equal to that of one circuit board. Generation of losses can be reduced for compact circuit boards, and heating can be performed individually, correspondingly, for each kind of circuit board. Manufacturing various kinds of circuit boards, each by a small amount, with high productivity as compared with the conventional art is enabled accordingly.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: February 7, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Yamauchi, Naoto Hosotani, Kazuki Fukada, Katsuhiko Watanabe
  • Patent number: 6928727
    Abstract: A method and apparatus for manufacturing an electrical connection unit and connector array is provided. Such arrays may be used to solder together traces from opposed circuit boards, in which the array is fitted between, and soldered to the boards to complete a circuit. The method of manufacturing a connection unit includes providing a first insulative base with one or more contacts or contact groups extending from the first side towards the second side of the base. Solder portions or solder balls may be reflowed to contacts at their termination points. An apparatus and method may provide a solder positioning device or means on top of or adjacent to the first insulative base, so that solder portions or solder balls are placed within cavities in the positioning device, in alignment with apertures of the first insulative base. The connection unit may be heated to reflow and fuse the solder portions to the contact termination, thereby constructing an array.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 16, 2005
    Assignee: AVX Corporation
    Inventors: John J. Ashman, Monroe Waymer, Jennifer Hammond
  • Patent number: 6929169
    Abstract: A method for soldering an electronic component is provided. A first solder land containing copper and a second solder land are formed on a surface of a circuit board. A first solder section composed of a Sn—Ag—Cu solder material is formed on each of the first and the second solder lands, and a terminal of an electronic component chip is mounted on the first solder land. The first solder land and the terminal are fusion-bonded. A second solder section composed of a Sn—Zn solder material is formed on the first solder section disposed on the second solder land. A lead terminal of another electronic component is inserted into a terminal hole formed near the second solder land; and the second solder section and the lead terminal are heated at a temperature lower than the previous temperature to connect the lead terminal to the second solder section by fusion bonding.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: August 16, 2005
    Assignee: Alps Electric Co., Ltd.
    Inventors: Teruyoshi Kubokawa, Kunio Kosaka, Takafumi Nomura
  • Patent number: 6927346
    Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Carolyn R. McCormick, Terrance J. Dishongh
  • Patent number: 6915941
    Abstract: A method for locally applying solder to a set of preselected conductor areas on a printed circuit board without causing thermal damage to adjacent sensitive surface mounted devices and connectors. Before solder is applied, molten solder within a solder reservoir is pumped upwardly through a set of solder wave nozzles so as to clean and preheat the nozzles. The preselected conductor areas on the board are then aligned with the nozzles. At this time, the board is maintained at a height slightly above the nozzles to the extent that the molten solder is prevented from escaping from between the board and the nozzles. A relatively low wave of solder is produced through the nozzles to cause the low wave of solder to contact and preheat the preselected conductor areas on the board. A relatively high wave of solder is then produced through the nozzles to locally solder the preselected conductor areas on the printed circuit board.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 12, 2005
    Assignees: Senju Metal Industry Co., Ltd., KTT Co., Ltd.
    Inventors: Akira Takaguchi, Masaki Wata, Chikara Numata
  • Patent number: 6915945
    Abstract: For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining temperature is chosen in such a way that the substrate, with a pressure being exerted on the electrical component, experiences a plastic deformation, with the result that the electrical component is pressed together with the conductor structure into the substrate in a positively locking manner. In order to produce the connection between the component and the substrate, use is preferably made of a thin diffusion solder layer which can be processed at temperatures lying below the melting point of the substrate.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: July 12, 2005
    Assignee: Infineon Technologies AG
    Inventor: Holger Hübner
  • Patent number: 6913183
    Abstract: Selective gas knives for wave soldering provide for targeted gas flow at a particular location on a substrate, such as a printed circuit board. Both the temperature and flow rate of gas through a segment of a gas knife can be independently controlled.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 5, 2005
    Assignee: Speedline Technologies, Inc.
    Inventors: Eric Wayne Becker, Kenneth Kirby
  • Patent number: 6914326
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: July 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Patrick W. Tandy, Willam J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Patent number: 6902097
    Abstract: A method of soldering comprises disposing first and second balls of solder adjacent one another on a wire; disposing flux on the wire between and in contact with both of the first and second balls and so as to substantially fill a space between the first and second balls; disposing the wire on a substrate so that the first and second balls of solder contact a single conductor on the substrate; and melting the first and second balls of solder and flux and soldering the wire to the conductor.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: June 7, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Eddy W. Vanhoutte, Gilbert De Clercq
  • Patent number: 6902102
    Abstract: In a soldering method for soldering an electronic component including a palladium or palladium alloy layer formed on a surface of the electronic component and also including a soldering lead terminal onto a printed wiring board including a soldering land and plated through hole, a solder layer containing tin and zinc as main components is formed on the surfaces of the land through hole by a HAL treatment. The lead terminal is inserted and mounted in the through hole. The printed wiring board is brought into contact with jet flows of a solder containing tin and zinc as the main components to thereby supply a solder to the land and through hole.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: June 7, 2005
    Assignees: NEC Infrontia Corporation, NEC Toppan Circuit Solutions Toyama, Inc., Soldercoast Co., Ltd., Maruya Seisakusho Co., Ltd., Nihon Den-netsu Keiki Co., Ltd.
    Inventors: Kazuhiko Tanabe, Hiroaki Terada, Masahiro Sugiura, Tetsuharu Mizutani, Keiichiro Imamura, Takashi Tanaka
  • Patent number: 6898847
    Abstract: A method is described for producing an electrical connection between a plug element and a printed circuit board. A plug end of the at least one plug element is inserted in an opening extending through the printed circuit board. A solder, preferably in the form of solder paste, is applied essentially from above to at least parts of the opening or the area surrounding the opening. The connection between the board and the plug end is achieved by melting the solder. Prior to melting of the solder and/or application of the solder, the plug end is introduced into the opening in the printed circuit board essentially from below, and is held therein by a retaining arrangement such that during melting the solder enters the opening from above and contacts the plug end.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 31, 2005
    Assignee: Hella KG Hueck & Co.
    Inventors: André Koerner, Ralf Schulze
  • Patent number: 6896172
    Abstract: A lead-free solder paste suitable for reflow soldering includes a plurality of different types of metal powder mixed with a flux. One of the metal powders is a Sn alloy powder. Another of the metal powders is selected from a Sn alloy powder, elemental Ag powder, elemental Cu powder, and elemental Sn powder. Each Sn alloy powder includes 0-8 mass % of Ag, 0-5 mass % of Cu, and at least 80 mass % of Sn. The plurality of metal powders have a composition when melted of 1-5 mass % Ag, 0.5-3 mass % Cu, and a remainder of Sn.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 24, 2005
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Toshihiko Taguchi, Satoru Akita, Masato Shimamura, Ryoichi Suzuki, Tetsuya Okuno
  • Patent number: 6885613
    Abstract: There is disclosed apparatus for monitoring a solder wave comprising a board of insulating material simulating a printed circuit board, an array of spaced electrical contact elements on the underside of the board across the entire width thereof, means for measuring the dwell time of each contact in the wave as the board is conveyed over the wave, and means for displaying the measured dwell times to show the contact area and time.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: April 26, 2005
    Assignee: Circuitmaster Designs Limited
    Inventors: Andrew Bainbridge, Patrick John McWiggin
  • Patent number: 6851598
    Abstract: An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical strength in the spatial directions x, y and z, which can be electrically connected to corresponding contact terminal areas of a printed circuit board. The semiconductor chip or the wiring layer additionally has at least two spacers for the mechanical connection to a printed circuit board. A method for producing the electronic component is also described.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Uta Gebauer, Harry Hedler, Jürgen Högerl, Volker Strutz
  • Patent number: 6845556
    Abstract: Circuit board reworking techniques involve removing original solder from the metallic pad, removing an outer portion of the metallic pad to expose an inner portion of the metallic pad, and applying new solder to the metallic pad. Removal of the original solder and the outer portion of the metallic pad exposes the inner portion which has non-corroded and non-contaminated metal. The application of new solder to this inner portion of the pad enables wettability of the pad as well as provides a protective coating to prevent corrosion of the inner portion (e.g., oxidation, reaction with contaminants, etc.). Accordingly, circuit board abnormalities such as “Black Pad” defects can be cured.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: January 25, 2005
    Assignee: EMC Corporation
    Inventor: Jin Liang
  • Patent number: 6843862
    Abstract: A substantially lead-free solder with enhanced properties comprises from 88.5% to 93.5% tin; from 3.5% to 4.5% silver; from 2.0% to 6.0% indium; and from 0.3% to 1.0% copper. The solder may also comprise up to 0.5% of an anti-oxidant or anti-skinning additive. A solder embodying the invention finds particular utility in wave-soldering processes where it may be used as a direct replacement for conventional tin/lead solder.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: January 18, 2005
    Assignees: Quantum Chemical Technologies (Singapore) Pte Ltd, Singapore Asahi Chemical and Solder Industries Pte Ltd
    Inventors: Kai Hwa Chew, Wei Chih Pan
  • Patent number: 6839961
    Abstract: Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame and in registered alignment with individual bond pads over a substrate. While the ball portions are within the frame, the balls are exposed to bonding conditions effective to bond the balls with their associated bond pads. In another embodiment, a frame is provided having a plurality of holes sized to receive individual solder balls. Individual balls are delivered into the holes from over the frame. The balls are placed into registered alignment with a plurality of individual bond pads over a substrate while the balls are in the holes. The balls are bonded with the individual associated bond pads.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: January 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 6834791
    Abstract: A method of retaining a solder mass within a solder-bearing component is provided and includes the steps of: (a) forming a plurality of fingers in the solder-bearing component at one edge thereof, with each finger being defined by a pair of slots formed in the solder-bearing component; and (b) interleaving a solder mass between the fingers such that the solder mass is securely held by the fingers. The solder-bearing component includes any number of different types of components where a solder mass is held thereby, e.g., leads, terminals, connectors, electromagnetic shields, etc.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: December 28, 2004
    Assignee: Nas Interplex Inc.
    Inventor: Jack Seidler
  • Patent number: 6827252
    Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: December 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6817091
    Abstract: An electronic assembly is provided having a die, a heat spreader, and a solidified solder material. A die includes a die substrate and an integrated circuit on a bottom surface of the die substrate. The heat spreader is located above the die and has left and right inclined faces. The left inclined face tapers from a point near a center of the die to a point upward and to the left of the upper surface. The right inclined face tapers from a point near the center upward and to the right above the upper surface. A solidified solder material fills regions between the upper surface and the inclined faces of the lower surface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: Thomas J. Fitzgerald, Carl L. Deppisch, Fay Hua
  • Patent number: 6817092
    Abstract: A method allowing for the inexpensive automated construction of interconnections between circuit boards is provided. According to the present invention, printed circuit pins are inserted in a circuit board from the top (component side). Provided the heads of the pins are thin enough to lie beneath a solder stencil, the pins may be pre-installed on the circuit board and solder applied to the pins at the same time solder is applied to other regions of the board. Thus, known surface mount techniques may be employed to form solder connections between the pins and conductive traces on the circuit board, which facilitates the automation of the previously manual operation of soldering the printed circuit pins separately.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 16, 2004
    Assignee: Powerwave Technologies, Inc.
    Inventors: James Keith Custer, James Hiram Roberson, William Kerr Veitschegger
  • Publication number: 20040188498
    Abstract: A method of soldering comprises disposing first and second balls of solder adjacent one another on a wire; disposing flux on the wire between and in contact with both of the first and second balls and so as to substantially fill a space between the first and second balls; disposing the wire on a substrate so that the first and second balls of solder contact a single conductor on the substrate; and melting the first and second balls of solder and flux and soldering the wire to the conductor.
    Type: Application
    Filed: April 6, 2004
    Publication date: September 30, 2004
    Applicant: PHILIPS CORPORATION
    Inventors: Eddy W. Vanhoutte, Gilbert De Clercq
  • Patent number: 6796481
    Abstract: A method for mounting a chip on a substrate includes applying the underfill agent onto at least one of the substrate and the chip and moving the chip to the substrate to bring the bump into contact with the electrode. The method also includes steps to distribute the underfill agent in a space between the chip and the substrate, to around the bump and the electrode, heating the bump or electrode in the state that the bump is buried in the underfill agent to melt the bump or electrode so as to weld the bump to the electrode.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: September 28, 2004
    Assignee: Toray Engineering Co., Ltd.
    Inventor: Akira Yamauchi
  • Patent number: 6796485
    Abstract: An electromagnetic shield is provided and includes a shield body having an upper wall connected to opposing side walls and opposing end walls. At least two opposing walls of the electromagnetic shield each have a plurality of resilient fingers formed at a lower edge thereof. The electromagnetic shield also includes a solder mass securely held by the fingers by being interleaved between the fingers of each of the at least two opposing walls. The interleaving of the solder mass results in the solder mass being securely held by the fingers and ready for mounting to an electronic component for shielding a portion of the electronic component from undesirable and potentially damaging emissions from neighboring components. A method of mounting an electromagnetic shield to an electronic component having a planar surface and a method of interleaving the solder mass are also provided.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 28, 2004
    Assignee: Nas Interplex Inc.
    Inventor: Jack Seidler
  • Patent number: 6797926
    Abstract: Disclosed are an apparatus and a method for bonding electronic components, a circuit board, and an electronic component mounting apparatus, whereby various kinds of circuit boards can be manufactured, each by a small amount, with high productivity as compared with the conventional art. There are provided a stage member and a heating device, so that a circuit board is heated by the heating device while held in contact with the stage member, which stage member has a size almost equal to that of one circuit board. Generation of losses can be reduced for compact circuit boards, and heating can be performed individually, correspondingly, for each kind of circuit board. Manufacturing various kinds of circuit boards, each by a small amount, with high productivity as compared with the conventional art is enabled accordingly.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Yamauchi, Naoto Hosotani, Kazuki Fukada, Katsuhiko Watanabe
  • Patent number: 6794616
    Abstract: A solder flow oven comprises a reflow zone for heating a workpiece using heated air to a temperature effective to reflow solder. The reflow zone comprises a nozzle having divergent vanes that direct shear layers into neighboring zones to extend the distance over which the workpiece is heated to effective solder reflow temperature.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: September 21, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventor: Lakhi Nandlal Goenka
  • Patent number: 6792677
    Abstract: A method of manufacturing an electronic component unit comprises the steps of forming a conductive pattern on a surface of a substrate, roughening a surface of a connecting area of said conductive pattern, printing an adhesive on the connecting area, connecting an electrode of an electronic component to the electroconductive adhesive on the connecting area, and drawing the adhesive at a temperature of 50-120° C.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: September 21, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junji Oishi, Kenichi Nagai
  • Publication number: 20040178250
    Abstract: The invention discloses design concepts and means and methods that can be used for enhancing the reliability and extending the operating life of electronic devices, and assemblies incorporating such devices, and substrates and/or PCBs, especially if such assemblies are exposed to severe environments such as thermal cycling or power cycling. The main thrust of the invention is to provide flexible joints, such as columns, between the attached components, and preferably to orient such joints, so that they would present their softest bending direction towards the thermal center or fixation point of the assemblies. Joints with rectangular or elongated cross-section are preferred, and they should be oriented so that the wide face of each joint would be facing the thermal center, perpendicular to the thermal deformation ray emanating from the thermal center towards the center of each respective joint. The concepts apply equally to leadless packages as well as to leaded packages.
    Type: Application
    Filed: January 26, 2004
    Publication date: September 16, 2004
    Inventor: Gabe Cherian
  • Publication number: 20040173664
    Abstract: A circuit board pallet with an improved securement pin and component positioning arms is disclosed. The improved pin of the present invention is cylindrical pin with an enlarged head. A countersunk hole is drilled in the bottom of the pallet to accommodate the pin. The pin is inserted into the countersunk hole and secured with a high-temperature epoxy resin. The epoxy holds the pin securely in place and keeps the pin from moving up or down.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Inventor: James Gleason
  • Patent number: 6779711
    Abstract: A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: August 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Anthony K. Stamper, Judith M. Rubino, Carlos J. Sambucetti
  • Patent number: 6779710
    Abstract: A method for soldering parts mounted on a print circuit baseboard with Pb-free material. A reflow soldering process is performed to parts mounted on one side surface of the print circuit baseboard. A flow soldering process is then performed to parts mounted on the other side surface of the print circuit baseboard with a jet flow solder process. Either a composition or a melting point of alloys generated when the reflow and flow soldering are performed is differentiated so that the alloy on one side surface does not melt during a flow soldering process to the other side surface.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: August 24, 2004
    Assignee: Ricoh Company, Ltd.
    Inventors: Minoru Igarashi, Katsuhiko Mukai, Masashi Isoda, Takayuki Kobayashi
  • Patent number: 6777105
    Abstract: A part has a body unit; and one or more leg formed on the body unit. One or more slit is formed on the body unit adjacent to the leg. The legs are inserted to insert holes of a printed wiring board or the like and soldered thereto. Since the slit is formed adjacent to the leg, the heat applied to the leg for the soldering is not radiated by the body unit by virtue of the slit. Therefore, the part can be reliably attached to the printed wiring board or the like.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: August 17, 2004
    Assignee: Pioneer Corporation
    Inventor: Kazuto Kadokawa
  • Publication number: 20040144834
    Abstract: An apparatus and method for aligning and attaching a plurality of solder columns to a patterned array of corresponding electrical contacts on a ceramic substrate. The apparatus includes a flat rectangular alignment plate in which a plurality of through holes are defined in a pattern identical to the pattern of the electrical contacts. Four retainers depend from the four sides of the alignment plate. The retainers hold the alignment plate in a fixed position above the ceramic substrate such that the through holes are vertically aligned with the corresponding electrical contacts. The solder columns are inserted through the through holes so that the solder columns are placed in an upright position on the respective contact pads. Solder paste is applied onto the electrical contacts. The alignment plate and the substrate are heated so that the solder paste is reflowed and wetted onto the solder columns and the electrical contacts.
    Type: Application
    Filed: January 14, 2004
    Publication date: July 29, 2004
    Inventors: Shinichi Nomoto, Takashi Nauchi
  • Publication number: 20040142512
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 6763580
    Abstract: A method and module for securing a conductive interconnect (30) through a metallic substrate (36). The method includes the steps of: forming a hole (34) in the metallic substrate (36), the hole (34) defined by an internal surface (46) of the metallic substrate (36); applying an electrically insulating layer (48) to the metallic substrate (36) including the internal surface (46); applying a solderable coating (50) to at least a portion of the electrically insulating layer (48) around the hole (34); applying a solder (52) to at least a portion of the solderable coating (50) at and above the hole (34); inserting the conductive interconnect (30) through the hole (34); and solder bonding the conductive interconnect (30) within the hole (34).
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: July 20, 2004
    Assignee: Motorola, Inc.
    Inventors: Stanton Rak, Ying Wang
  • Publication number: 20040134974
    Abstract: A solder bump structure includes a contact pad, an intermediate layer located over the contact pad, a solder bump located over the intermediate layer, and at least one metal projection extending upwardly from a surface of the intermediate layer and embedded within the solder bump. Any crack in the solder bump will tend to propagate horizontally through the bump material, and in this case, the metal projections act as obstacles to crack propagation. These obstacles have the effect of increasing the crack resistance, and further lengthen the propagation path of any crack as it travels through the solder bump material, thus decreasing the likelihood device failure.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Inventors: Se-Yong Oh, Nam-Seog Kim