Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.

Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Abstract: There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) with buried depletion electrode. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. The IGBT also includes a plurality of deep insulated trenches with a buried depletion electrode and at least one gate electrode disposed therein. In addition, the IGBT includes an active cell including an emitter adjacent the gate electrode, and an implant zone, situated between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type. In one implementation, the IGBT may also include a dummy cell neighboring the active cell.

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

Abstract: A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.

Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.

Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.

Abstract: To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.

Abstract: A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

Abstract: A semiconductor device including a first electrode, a second electrode, and a silicon carbide layer of which at least a portion is provided between the first electrode and the second electrode, the silicon carbide layer including an n-type first silicon carbide region, a plurality of p-type second silicon carbide regions, and a plurality of n-type third silicon carbide regions. The semiconductor device further includes a plurality of first conductive layers each of which is in contact with the n-type first silicon carbide region, a number n, n being 2, 3, 4 or 5, of first gate electrodes that are provided between two adjacent first conductive layers of the plurality of first conductive layers, and extend in the first direction, and a plurality of first gate insulating layers each of which is provided between one of the n first gate electrodes and the n-type first silicon carbide region.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 ?m in regard to the depth direc

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches.

Abstract: A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including the first trenches. In an interlayer insulating film, a contact hole is provided within the first element range, and a wide contact hole is provided within the inactive range. The first metal layer contacts the semiconductor substrate within the contact hole and the wide contact hole. The insulating protective film covers an outer peripheral side portion of a bottom surface of a second recess which is provided in a surface of the first metal layer above the wide contact hole. A side surface of an opening provided in a portion of the insulating protective film that includes the first element range is disposed in the second recess. The second metal layer contacts the first metal layer and the side surface of the opening.

Abstract: The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include backside metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the backside metallization. The integrated RF circuit structure may further include front-side metallization coupled to the backside metallization with a via. The front-side metallization is arranged distal from the backside metallization. The front-side metallization, the via, and the backside metallization may at least partially enclose the active device.

Abstract: A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.

Abstract: Method for manufacturing an insulated gate bipolar transistor, which includes a drift layer of a first conductivity type between an emitter side, at which a gate and emitter electrode are arranged, and a collector side, at which a collector electrode is arranged including steps: providing a substrate of a second conductivity type, applying a dopant of the first conductivity type on the first side, creating a drift layer of the first conductivity type on the first layer, diffusing the ions such that a buffer layer is created, having a higher doping concentration than the drift layer, creating a base layer of the second conductivity type on the drift layer, creating an emitter layer of the first conductivity type on the base layer, thinning the substrate on the second side such that the remaining part of the substrate forms a collector layer.

Abstract: False detection relating to overcurrent is prevented, and it is determined with no dead time whether or not the current of a main element is an overcurrent. By a gate signal indicating conductivity being applied to the gate of a sense element earlier than to a main element when the main element is caused to be conductive, and overshoot caused by a differential circuit of the sense element gate input portion being caused before current flows into the main element, it is possible to prevent false detection relating to overcurrent, and determine with no dead time whether or not the current of the main element is an overcurrent.

Abstract: A semiconductor device has a reduced an on-voltage and uses a gate resistance to improve the trade-off relationship between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability. A floating p+-type region is provided in an n?-type drift layer so as to be spaced from a p-type base region configuring a MOS gate structure. An emitter electrode and the floating p+-type region are electrically connected by an n+-type region provided in the surface layer of a substrate front surface. The n+-type region is covered with a second insulating film which film is covered with an emitter electrode. By an electric field being generated in the n+-type region by the emitter electrode provided on the top of the n+-type region via the second interlayer insulating film, the n+-type region forms a current path which causes holes accumulated in the floating p+-type region to flow to the emitter electrode when turning on.

Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole.

Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

Abstract: A method for cutting a substrate includes: radiating, as part of a first laser radiating process, a laser towards a surface of the substrate to form a first groove in a substrate. Radiating the laser towards the surface includes radiating, in sequence, the laser towards a first outer point (FOP), a second outer point (SOP), a first intermediate point (FIP), a second intermediate point (SIP), and a first cut point (FCP) of the surface, each of the points being spaced apart from one another by one or more distances. The FCP corresponds to a cut line of the substrate. The FOP and the SOP are respectively disposed at lateral sides of the FCP. The FIP is disposed between the FCP and the FOP. The SIP is disposed between the FCP and the SOP. The same kind and intensity of laser is radiated towards each of the points.

Abstract: A semiconductor device includes a first load contact, a second load contact and a semiconductor region positioned between the first and second load contacts. The semiconductor region includes: a first semiconductor contact zone in contact with the first load contact; a second semiconductor contact zone in contact with the second load contact; a first conductivity type semiconductor drift zone between the first and second semiconductor contact zones, wherein the semiconductor drift zone couples the first semiconductor contact zone to the second semiconductor contact zone. The semiconductor device further comprises: a trench comprising a control electrode and an insulator. The control electrode extends for at least 75% of the semiconductor drift zone. A drift zone doping concentration and an extension of the semiconductor drift zone defines a blocking voltage of the semiconductor device. The insulator is configured for insulating a voltage that amounts to at least 50% of said blocking voltage.

Abstract: A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device.

Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.

Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.

Abstract: A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip.

Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.

Abstract: A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).

Abstract: A semiconductor device includes stripe-shaped gate trench formed in one major surface of n-type drift layer, gate trench including gate polysilicon formed therein, and gate polysilicon being connected to a gate electrode; p-type base layer formed selectively in mesa region between adjacent gate trenches, p-type base layer including n-type emitter layer and connected to emitter electrode; one or more dummy trenches formed between p-type base layers adjoining to each other in the extending direction of gate trenches; and electrically conductive dummy polysilicon formed on an inner side wall of dummy trench with gate oxide film interposed between dummy polysilicon and dummy trench, dummy polysilicon being spaced apart from gate polysilicon. Dummy polysilicon may be connected to emitter electrode. The structure according to the invention facilitates providing an insulated-gate semiconductor device, the Miller capacitance of which is small, even when the voltage applied between the collector and emitter is low.

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

Abstract: A semiconductor device is operated by applying a gate voltage with a first value to a gate electrode terminal such that current flows through the IGBT between first and second electrode terminals and current flow through a desaturation channel is substantially blocked. A gate voltage with a second value is applied to the gate electrode terminal the absolute value of which is lower than that of the first value, such that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal. A gate voltage with a third value is applied to the gate electrode terminal, the absolute value of which is lower than that of the first and second values, such that current flow through the IGBT between the first and second electrode terminals is substantially blocked.

Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.

Abstract: Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. One or more heavily doped regions of the second conductivity type are formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the substrate. This abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A power semiconductor device includes a power transistor including a plurality of transistor cells on a semiconductor die. At least some of the transistor cells are inhomogeneous by design so that the number of current filaments in the transistor cells with reduced local current density increases and fewer transient avalanche oscillations occur in the power transistor during operation.

Abstract: A semiconductor device includes: a main switching element, a current-sensing switching element and a surge protection element, which are formed on a single semiconductor substrate, wherein the surge protection element is a bidirectional diode connected between a first main electrode of the main switching element and a first main electrode of the current-sensing switching element. Also, a switching circuit includes the semiconductor device and a detection resistor connected to the first main electrode of the current-sensing switching element; and a driving device that drives the semiconductor device based on a voltage drop occurring in the detection resistor when the semiconductor device is turned on.

Abstract: A semiconductor device includes a semiconductor substrate, a front surface electrode provided on a front surface of the semiconductor substrate, a solder layer, and a metal member fixed to a front surface of the front surface electrode via the solder layer. The solder layer includes an inner solder portion positioned inner than an end portion of the metal member and an outer solder portion positioned outer than the end portion of the metal member, relative to a direction along the front surface of the semiconductor substrate. The semiconductor substrate includes an inner substrate portion positioned below the inner solder portion and an outer substrate portion positioned below the outer solder portion. A density of carriers that flow from the outer substrate portion to the front surface electrode is lower than a density of carriers that flow from the inner substrate portion to the front surface electrode.

Abstract: The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection between the drain of the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which is immune to latch and gives high gain and reliability. The structure can be realized with standard CMOS technology available at foundries.

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

Abstract: A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.