Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Abstract: The present invention provides an insulated-gate bipolar transistor (IGBT) structure and a method for manufacturing the same. The structure is a planar IGBT structure, and is characterized by an ultra-thin channel and buried oxide located below the channel. The structure can provide the theoretically lowest on-state voltage drop.

Abstract: A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.

Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.

Abstract: A rectifier device is described herein. In accordance with one embodiment, the rectifier device includes a semiconductor body doped with dopants of a first doping type and one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type. The rectifier device further includes a controllable resistance circuit that is electrically connected between the semiconductor body and a first well region of one or more well regions and configured to provide a resistive current path between the semiconductor body and the first well region. The resistance of the current path is dependent on an instantaneous level of an alternating input voltage.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: A power semiconductor device having an IGBT-configuration includes at least one power cell. Each power cell includes at least three trenches arranged laterally adjacent to each other. Each trench extends into a semiconductor body along a vertical direction and includes an insulator that insulates a respective electrode from the semiconductor body. The at least three trenches include at least one control trench whose electrode is electrically coupled to a control terminal, and a source trench whose electrode is electrically coupled to a first load terminal. An active mesa for conduction of at least a part of the load current is laterally confined at least by one of the at least one control trench and includes at least a respective section of each of a source region and a channel region. An auxiliary mesa is laterally confined by the source trench and one of the at least one control trench.

Abstract: A power device includes an active area having at least two switchable regions with different threshold voltages.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer po

Abstract: A heater includes an elongated substrate, a heating resistor formed on the substrate, a resistor electrode that is formed and is in contact with the heating resistor, and a heat conducting film. The substrate includes a heat generating section and a non-heat generating section. The heat generating section is a section that is overlapped with, out of the heating resistor and the resistor electrode, only the heating resistor in the lengthwise direction of the substrate. The non-heat generating section is a section that is different from the heat generating section and is adjacent to the heat generating section in the lengthwise direction of the substrate. The heat conducting film is formed so as to extend from the heat generating section into the non-heat generating section on the substrate.

Abstract: The semiconductor substrate may include an emitter region, an upper body region being in direct contact with the gate insulating film below the emitter region, an intermediate region being in direct contact with the gate insulating film below the upper body region, a lower body region being in direct contact with the gate insulating film below the intermediate region, a drift region being in direct contact with the gate insulating film below the lower body region, and a collector region being in direct contact with the drift region from below. The lower body region may include a first range and a second range that has a higher crystal defect density than the first range. The second range may be in direct contact with the gate insulating film. The first range may be in direct contact with the second range on a side opposed to the gate insulating film.

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract: In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source diffusion layer and a base diffusion layer are formed in the active region. The base diffusion layer has a base bottom portion inclined in such a manner that a portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a portion of the base bottom portion adjacent to the gate electrode. A contact portion has a contact bottom portion inclined in such a manner that a portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a portion of the contact bottom portion in contact with the base diffusion layer.

Abstract: A semiconductor device includes: a gate trench portion and a dummy trench portion provided extending in a predetermined direction of extension at the upper surface of the semiconductor substrate; a mesa portion sandwiched by the gate trench portion and the dummy trench portion; an emitter region provided between the upper surface of the semiconductor substrate and the drift region and provided at an upper surface of the mesa portion and adjacent to the gate trench portion; and a contact region provided between the upper surface of the semiconductor substrate and the drift region and provided at the upper surface of the mesa portion and adjacent to the dummy trench portion.

Abstract: In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.

Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface and a back surface, a drift region having a first conductivity type, a body region formed in the drift region and having a second conductivity type, a plurality of grooves passing through the body region from the main surface toward the back surface, a gate electrode formed in the plurality of grooves with a gate insulating film interposed therebetween, and an electric field relaxation layer provided below the plurality of grooves in the drift region and having a second conductivity type. The electric field relaxation layer continuously extends over the entire body region.

Abstract: An IGBT includes current sense cell having a sensing area for sensing a current flowing an active area and an extraction area for extracting a hole current. The extraction area around the sensing area, has a portion in a gate trench is not in contact with the emitter region, and a p-type well region provided deeper than the first trench and having a high impurity concentration. An area of the extraction area is four times or more and 10,000 times or less an area of the sensing area.

Abstract: A front surface element structure is formed on the front surface side of an n?-type semiconductor substrate. Then defects are formed throughout an n?-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n?-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n?-type semiconductor substrate.

Abstract: A semiconductor substrate includes a first-conductivity drift layer, a first-conductivity first impurity layer, a second-conductivity base layer, and a first-conductivity first emitter region. The first impurity layer is provided on the drift layer, and has impurity concentration higher than impurity concentration of the drift layer. The base layer is provided on the first impurity layer. The first emitter region is provided on the base layer. The first impurity layer connects between trenches. The plurality of trenches are formed in the semiconductor substrate covered by a gate insulation film. The gate insulation film has a first thickness between a gate electrode and the drift layer in a side wall surface, and has a second thickness between the gate electrode and the drift layer in a bottom surface. The second thickness is larger than the first thickness.

Abstract: A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region.

Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.

Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor.

Abstract: A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 1×1013 cm?3 and 5×1014 cm?3.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a semiconductor structure, where the semiconductor structure includes an active region and a gate structure located in the active region, the gate structure at least including a gate electrode, and the active region exposing an upper surface of the gate electrode; forming a surface insulator layer on the upper surface of the gate electrode; forming a patterned interlayer dielectric layer on the semiconductor structure, where the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and forming a conductive contact layer passing through the first through hole and contacting with the active region.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

Abstract: Provided is a semiconductor device including: a semiconductor substrate doped with an impurity; a front-surface-side electrode provided at a side of a front surface of the semiconductor substrate; and a back-surface-side electrode provided at a side of a back surface of the semiconductor substrate; wherein the semiconductor substrate includes: a peak region arranged at the side of the back surface of the semiconductor substrate and having one or more peaks of an impurity concentration; a high concentration region arranged closer to the front surface than the peak region and having an impurity concentration more gently sloped than the one or more peaks; and a low concentration region arranged closer to the front surface than the high concentration region and having an impurity concentration lower than the impurity concentration of the high concentration region and a substrate concentration of the semiconductor substrate.

Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces, a drift or base zone in the semiconductor body and an oxygen diffusion barrier in the semiconductor body. The drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier. The semiconductor device further includes first and second load terminal contacts. At least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface.

Abstract: The present disclosure provides a PMIC boot timing circuit and a PMIC boot timing determination method. The circuit includes a PMIC, a first capacitor, a second capacitor, and a triode, wherein the PMIC includes a first buck module, a second buck module, a third buck module and a direct current source; one end of the first capacitor is connected to the direct current source, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to one end of the direct current source, and the other end of the second capacitor is connected to the drain of the triode; the source of the triode is grounded, and the gate of the triode is connected to the PMIC. Compared with the related art, the circuit and the method provided by the present disclosure can achieve different timing generation and normal boot timing.

Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.

Abstract: A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, and a first insulating portion. The first electrode includes first and second electrode regions. The semiconductor layer includes first to third semiconductor regions, and third and fourth partial regions. The first semiconductor region includes first and second partial regions. The first partial region is separated from the first electrode region. The second semiconductor region is separated from the second partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The third partial region is separated from the second electrode region. The fourth partial region is separated from the second electrode region. The first insulating portion is provided between the electrode region and the partial region and between the electrode region and the semiconductor region. The first insulating portion has a first width and a second width.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Abstract: A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.

Abstract: An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.

Abstract: Provided is a semiconductor device including a plurality of dummy trench portions that are provided in a front surface side of a semiconductor substrate and each have provided therein an electrode to which an emitter potential is supplied, and a gate trench portion that is provided in a manner to surround two or more dummy trench portions from among the plurality of dummy trench portions in the front surface side of the semiconductor substrate and has provided therein an electrode to which a gate potential is supplied.

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

Abstract: Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be produced by designing such that the effective base width of the BJT is at least a first threshold value but not more than a second threshold value, or, such that the total of the width of a second depletion region formed by connection with a collector region and the width of a first depletion region formed by connection with an emitter region, within a base region, differs from the width of the base region by a value that is at least the first threshold value but not more than the second threshold value. Whether or not there is a short circuit between the emitter region and the collector region is stochastically generated, and if ordinary turn-on voltage is not applied, whether or not there is a short circuit is identified.

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p+-type semiconductor regions are formed. The p+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

Abstract: A circuit apparatus includes a voltage output circuit that outputs a first output voltage when a first current of first temperature characteristics flows in a resistance element, and a second output voltage when a second current of second temperature characteristics different from the first temperature characteristics flows in the resistance element, an A/D conversion circuit that outputs a first digital value by performing A/D conversion on the first output voltage, and outputs a second digital value by performing A/D conversion on the second output voltage, and a processing unit that obtains temperature data by digital calculation processing of the first digital value and the second digital value.

Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.