Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.

Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.

Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.

Abstract: A structure and method for forming a tungsten region for a replacement metal gate (RMG). The method for forming the tungsten region may include, among other things, forming a first tungsten region i.e., tungsten seed layer, on a liner in a trench of a dielectric layer; removing a portion of the liner and the tungsten seed layer to expose an uppermost surface of a work function metal (WFM) layer wherein an uppermost surface of the liner and tungsten seed layer is positioned below an uppermost surface of the dielectric layer; and forming a second tungsten region from the tungsten seed layer. The tungsten region may be formed to contact the uppermost surface liner, the uppermost surface of WFM layer, and/or the sidewalls of the trench. The tungsten region may include a single crystallographic orientation. The tungsten region may also include an uppermost surface with a substantially arcuate cross-sectional geometry.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract: A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

Abstract: A high electron mobility transistor includes a buffer layer disposed on a substrate. A barrier layer is disposed on the buffer layer. A channel layer is disposed in the buffer layer and is adjacent to the interface between the buffer layer and the barrier layer. A gate electrode is disposed on the barrier layer. A drain electrode is disposed on the barrier layer on a first side of the gate electrode. A source electrode is disposed on the barrier layer on a second side of the gate electrode. A first enhancement layer is disposed on the barrier layer and the channel layer between the gate electrode and the drain electrode and is not in direct contact with the gate electrode, the source electrode, or the drain electrode. The first enhancement layer is an N-type doped III-V semiconductor.

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

Abstract: A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

Abstract: A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain electrode formed on the third semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode formed within an opening penetrating the third and second semiconductor layers and exposing the first semiconductor layer. The source electrode includes a first conductor layer in contact with the first semiconductor layer, and a second conductor layer stacked on the first conductor layer and in contact with the second semiconductor layer. A work function of a material forming the first conductor layer is smaller than that of a material forming the second conductor layer.

Abstract: A semiconductor device, including a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap width larger than or equal to a band gap width of the first nitride semiconductor layer, first, second, and third electrodes provided on the second nitride semiconductor layer, an insulation layer provided on the second nitride semiconductor layer and between the first and second electrodes, and a conductor provided within the insulation layer between the second and third electrodes and connecting the second and third electrodes to each other, or the conductor provided within the insulation layer between the first and second electrodes and connecting the first and second electrodes to each other, the conductor including a plurality of conductive regions arranged in a first direction from the first electrode toward the second electrode, the conductive regions being electrically connected to one another.

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

Abstract: A method of substantially offsetting polarization charges in an electronic device having a heterobarrier comprising providing a substrate; providing at least one pair of stacks of semiconductor materials; one of the pair of stacks having one or more of spontaneous and piezoelectric polarity where the total polarization charge is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced and the pair of stacks operate to store electrical energy.

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

Abstract: A semiconductor device includes a transistor cell region and a transition region. The transistor cell region includes a first portion of a super junction structure and a first contact structure electrically connecting a first load electrode with first source zones of transistor cells. The first source zones are formed on opposite sides of the first contact structure. The transition region directly adjoins to the transistor cell region and includes a second portion of the super junction structure and a second contact structure electrically connecting the first load electrode with a second source zone. The second source zone is formed only at a side of the second contact structure oriented to the transistor cell region.

Abstract: The present disclosure relates to an oxide thin film transistor and a fabricating method thereof. In the oxide thin film transistor, which uses amorphous zinc oxide (ZnO) semiconductor as an active layer, damage to the oxide semiconductor due to dry etching may be minimized by forming source and drain electrodes in a multilayered structure having at least two layers, and improving stability and reliability of a device by employing a dual passivation layer structure, which includes a lower layer for overcoming an oxygen deficiency and an upper layer to minimize effects of an external environment on the multilayered source and drain electrodes.

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Abstract: A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: A resonant body high electron mobility transistor is described with resonance frequencies in gigahertz regime, limited by the cutoff frequency of the readout transistor. Piezoelectric materials form the resonating membrane of the device. Different modes of acoustic resonance, such as a thickness-mode, can be excited and amplified by applying an AC signal to the transducer electrode and proper biasing of all electrodes. The drain electrode reads out the acoustic resonance and amplifies it. The drain electrode is placed at or near where the piezoelectric charge pickup is maximum; whereas, the source electrode is placed at a nodal point with minimum displacement.

Abstract: A semiconductor device comprising at least one active layer on a substrate and a first contact to the at least one active layer, the first contact comprising a metal in contact with the at least one active layer and a capping layer on the metal, the capping layer comprising a diffusion barrier, wherein the capping layer is patterned to form a pattern comprising regions of the contact covered by the capping layer and regions of the contact that are uncovered.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A semiconductor power device includes a substrate, an active region having a recess and disposed on the substrate, a first conductivity type semiconductor layer disposed on the recess and devoid of overlapping with the recess, a gate electrode disposed on the active region wherein a portion of the gate electrode is disposed in the recess, a dielectric layer between the active region and the gate electrode, and a two dimension electron gas formed in the active region.

Abstract: An oxide semiconductor film with a low density of defect states is formed. In addition, an oxide semiconductor film with a low impurity concentration is formed. Electrical characteristics of a semiconductor device or the like using an oxide semiconductor film is improved. A semiconductor device including a capacitor, a resistor, or a transistor having a metal oxide film that includes a region; with a transmission electron diffraction measurement apparatus, a diffraction pattern with luminescent spots indicating alignment is observed in 70% or more and less than 100% of the region when an observation area is changed one-dimensionally within a range of 300 nm.

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Abstract: A nitride semiconductor device includes: an electron transit layer including GaxIn1-xN (0<x?1); an electron supply layer formed on the electron transit layer and including AlyIn1-yN (0<y?1); a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween, wherein, in the electron transit layer, a portion contacting the gate insulating film and a portion contacting the electron transit layer are flush with each other.

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

Abstract: A method of fabricating a polycrystalline silicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer having dopants is formed on the substrate. An amorphous silicon layer is formed on the buffer layer having the dopants. A thermal process is performed to convert the amorphous silicon layer into a polycrystalline silicon layer by means of polycrystalization, and to simultaneously out-diffuse a portion of the dopants in the buffer layer into the polycrystalline silicon layer for adjusting a threshold voltage. The polycrystalline silicon layer is patterned to form an active layer. A gate insulating layer is formed on the active layer. A gate electrode is formed on the gate insulating layer. A source doped region and a drain doped region are formed in the active layer.

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

Abstract: A normally-off transistor with a high operating voltage is provided. The transistor can include a barrier above the channel and an additional barrier layer located below the channel. A source electrode and a drain electrode are connected to the channel and a gate electrode is connected to the additional barrier layer located below the channel. The bandgap for each of the barrier layers can be larger than the bandgap for the channel. A polarization charge induced at the interface between the additional barrier layer below the channel and the channel depletes the channel. A voltage can be applied to the bottom barrier to induce free carriers into the channel and turn the channel on.

Abstract: A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel formed in a first layer made of a first material and at least one p-type channel formed in a second layer made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability.

Abstract: FinFET devices and methods of fabricating a FinFET device are provided. An exemplary method of fabricating a FinFET device includes providing a semiconductor substrate with a plurality of fins and a multi-layered hardmask stack formed thereover. The multi-layered hardmask stack is patterned to form a patterned multi-layered hardmask stack having a tapered fin masking configuration with a shortened region and an elongated region. A region of fins adjacent to the shortened region is masked with a second mask. The region of fins masked with the second mask is free from the patterned multi-layered hardmask stack. Fins in unmasked areas are etched after forming the second mask. The second mask is removed with at least one layer of the patterned multi-layered hardmask stack remaining after etching the fins in the unmasked areas. End portions of the fins adjacent to the shortened region are etched after removing the second mask.

Abstract: A transistor device includes a source region, a drain region and a III-V channel material disposed between the source and drain region. A gate dielectric layer is epitaxially grown on the III-V channel material. The gate dielectric layer includes a (X)Se compound, wherein X includes one or more of Zn, Cd and/or Mg. A gate conductor is formed on the gate dielectric layer.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.