Abstract: A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer serving as an electron transit layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap greater than that of the first nitride semiconductor layer and serving as an electron supply layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer, the third nitride semiconductor layer having a band gap greater than that of the first nitride semiconductor layer and smaller than that of the second nitride semiconductor layer; and a gate part formed on the third nitride semiconductor layer, wherein the gate part has a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and includes an acceptor type impurity, and a gate electrode formed on the fourth nitride semiconductor layer.

Abstract: A nitride semiconductor device is disclosed. The semiconductor device provides the GaN channel layer, the InAlN barrier layer on the GaN channel layer, and the n-type AlGaN layer on the InAlN barrier layer. The source and drain electrodes are formed on the n-type AlGaN layer, while, the gate electrode is formed directly on the InAlN barrier layer. The n-type AlGaN layer has the aluminum (Al) composition greater than 20% at the interface against the InAlN barrier layer, which is greater than the aluminum (Al) composition at the interface against the source electrode.

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

Abstract: A switching device includes first-third semiconductor layers, a gate insulating film, and a gate electrode. The first semiconductor layer is of a first conductivity type. The second semiconductor layer is of a second conductivity type and in contact with the first semiconductor layer. The third semiconductor layer is of the first conductivity type, in contact with the second semiconductor layer. The gate insulating film covers a surface of the second semiconductor layer in a range in which the second semiconductor layer separates the first semiconductor layer from the third semiconductor layer. The gate electrode faces the second semiconductor layer via the gate insulating film. The gate electrode includes a fourth semiconductor layer covering a surface of the gate insulating film; and a fifth semiconductor layer having a bandgap different from a bandgap of the fourth semiconductor layer and covering a surface of the fourth semiconductor layer.

Abstract: A method for forming a hybrid semiconductor device includes growing a stack of layers on a semiconductor substrate. The stack of layers includes a bottom layer in contact with the substrate, a middle layer on the bottom layer and a top layer on the middle layer. First and second transistors are formed on the top layer. A protective dielectric is deposited over the first and second transistors. A trench is formed adjacent to the first transistors to expose the middle layer. The middle layer is removed from below the first transistors to form a cavity. A dielectric material is deposited in the cavity to provide a transistor on insulator structure for the first transistors and a bulk substrate structure for the second transistors.

Abstract: A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

Abstract: A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.

Abstract: In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Abstract: A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 ?m.

Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

Abstract: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

Abstract: A method of fabricating a semiconductor device is provided as follows. An epitaxial layer is formed on an active fin structure. Metal gate electrodes are formed on the active fin structure. Gate electrode caps are formed on upper surfaces of the metal gate electrodes. Metal gate spacers are formed on sidewalls of the metal gate electrodes. A source/drain electrode is formed on the epitaxial layer. An air spacer region is formed by removing the metal gate electrode caps and the metal gate spacers. An air spacer is formed within the air spacer region.

Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract: Methods of passivating light-receiving surfaces of solar cells with high energy gap (Eg) materials, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A Group III-nitride material layer is disposed above the passivating dielectric layer. In another example, a solar cell includes a substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the substrate. A large direct band gap material layer is disposed above the passivating dielectric layer, the large direct band gap material layer having an energy gap (Eg) of at least approximately 3.3. An anti-reflective coating (ARC) layer disposed on the large direct band gap material layer, the ARC layer comprising a material different from the large direct band gap material layer.

Abstract: A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits.

Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Abstract: A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a channel region adjacent to and in contact with one of a source region and a drain region. A tunnel barrier layer may be formed such that the tunnel barrier layer is interposed between, and in contact with, the channel region and one of the source region and the drain region. In some embodiments, a gate stack is then formed over at least the channel region. In various examples, the tunnel barrier layer includes a first material, and the channel region includes a second material different than the first material. In some embodiments, the semiconductor device may be oriented in one of a horizontal or vertical direction, and the semiconductor device may include one of a single-gate or multi-gate device.

Abstract: An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the substrate; fabricating and forming a dielectric layer on the nitride transistor structure, on which a gate region is defined; forming a groove structure on the gate region; depositing a p-type semiconductor material in the groove; removing the p-type semiconductor material outside the gate region on the dielectric layer; etching the dielectric layer in another position than the gate region on the dielectric layer to form two ohmic contact regions; and forming a source electrode and a drain electrode on the two ohmic contact regions, respectively.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage.

Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: A multilayer ceramic capacitor (MLCC) includes: first and second metal frames formed on a mounting surface of a ceramic body to be connected to first and second external electrodes providing voltages having opposing polarities, respectively, wherein the first and second metal frames are positioned inwardly of both end surfaces of the ceramic body in a length direction of the ceramic body to be spaced apart from both end surfaces of the ceramic body, respectively.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Abstract: A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Abstract: A semiconductor device includes a semiconductor stacked structure including at least an electron transit layer and an electron supply layer over a substrate. The electron supply layer includes a first portion and second portions sandwiching the first portion, and the first portion has a higher energy of a conduction band than that of the second portion, and includes a doped portion doped with an n-type impurity and undoped portions that sandwich the doped portion and are not doped with an impurity.

Abstract: Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin.

Abstract: A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: Provided is a method of removing native oxide from a substrate, the method including exposing the substrate to trimethyl aluminum (TMA) or dicyclopentadienyl magnesium (MgCp2) for a predetermined time.

Abstract: A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of Inx1Aly1Ga1?x1?y1N (0?x1<1, 0?y1<1, 0<1?x1?y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of Inx2Aly2Ga1?x2?y2N (0?x2<1, 0?y2<1, 0<1?x2?y2?1) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

Abstract: A semiconductor device can include a substrate and a fin body that protrudes from a surface of the substrate. The fin body can include a lower portion having a first lattice structure and an upper portion, separated from the lower portion by a boundary, the upper portion having a second lattice structure that is different than the first lattice structure. An epitaxially grown epitxial layer can be on the lower and upper portions.

Abstract: A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer.

Abstract: A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

Abstract: An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a two-dimensional (2-D) material, the first layer having a first thickness, and a second active device in a second region of the substrate, the second active device including a second layer of the 2-D material, the second layer having a second thickness, the 2-D material including a transition metal dichalcogenide (TMD), the second thickness being different than the first thickness.

Abstract: A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or InxGa1-xN (0<x?1) and formed on the substrate and a second semiconductor layer containing Al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section.

Abstract: A diamond based oxygen sensor is able to function in harsh environment conditions. The oxygen sensor includes a gateless field effect transistor including a synthetic, quasi-intrinsic, hydrogen-passivated, monocrystalline diamond layer exhibiting a 2-dimension hole gas effect. The oxygen sensor also includes a sensing layer comprising yttrium-stabilized zirconia deposited onto a surface of the gateless field effect transistor.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

Abstract: An organic light emitting diode display device includes a display unit including a plurality of pixels; a data driver applying data voltage to the pixels; and a power supplier including a first power source providing high-level voltage to the anode electrode of organic light emitting diodes and a second power source providing low-level voltage to the cathode electrode of the organic light emitting diodes included in the pixels, in which the power supplier provides the second power source in a sink method at positive voltage, when the threshold voltage of a driving transistor for driving the organic light emitting diodes shifts to a negative. When gate-source voltage of a driving transistor shifts to negative threshold voltage, it is possible to apply the data voltage at positive voltage and to simplify a driving IC, thereby ensuring wide use, by applying voltage of a second power source ELVSS at positive voltage.

Abstract: Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.