Abstract: A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract: In some aspects, methods of forming a metal selenide or metal telluride thin film are provided. According to some methods, a metal selenide or metal telluride thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase selenium or tellurium reactant. In some aspects, methods of forming three-dimensional architectures on a substrate surface are provided. In some embodiments, the method includes forming a metal selenide or metal telluride interface layer between a substrate and a dielectric. In some embodiments, the method includes forming a metal selenide or metal telluride dielectric layer between a substrate and a conductive layer.

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Abstract: A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced apart conductive semiconductor fin portions and a doped epitaxial semiconductor material structure located on exposed surfaces of each conductive semiconductor fin portion of the vertical stack. In the FinFET fuse, a topmost surface of a bottom doped epitaxial semiconductor material structure is merged to a bottommost surface of an overlying doped epitaxial semiconductor material structure.

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract: A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

Abstract: A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode.

Abstract: A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Abstract: The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.

Abstract: A method of forming a high electron mobility transistor (HEMT) that includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are formed on the second III-V compound layer. A p-type layer is deposited on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is formed on a portion of the p-type layer.

Abstract: A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.

Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

Abstract: A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C.

Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.

Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer (1) located over the substrate; a second nitride semiconductor layer (2) located over the first nitride semiconductor layer (1), having a larger band gap than the first nitride semiconductor layer (1), and having a recess (11) penetrating into the first nitride semiconductor layer (1); and a third nitride semiconductor layer (12) continuously covering the second nitride semiconductor layer (2) and the recess (11), and having a larger band gap than the first nitride semiconductor layer (1); a gate electrode (5) located above a portion of the third nitride semiconductor layer (12) over the recess (11); and a first ohmic electrode (4a) and a second ohmic electrode (4b) located on opposite sides of the gate electrode (5).

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: A display device includes a substrate, a first insulating layer having a first side wall, an oxide semiconductor layer on the first side wall, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer, a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the semiconductor substrate, FinFETs on the fins, a common gate for the FinFETs, a dielectric layer on the semiconductor substrate, the dielectric layer surrounding a cavity with the semiconductor substrate providing bottom confinement of the acoustic cavity by total internal reflection, and an interconnect structure above the FinFETs, the interconnect structure including phononic crystal(s) to confine acoustic energy in the cavity including the cavity and metal layer(s) sandwiched between two dielectric layers. The semiconductor structure may be realized, during FEOL fabrication of a FinFET, by forming a cavity on a surface of a semiconductor substrate. Then, after fabrication of the FinFET, forming an interconnect structure for the FinFET.

Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.

Abstract: According to this GaN-based HFET, resistivity ? of a semi-insulating film forming a gate insulating film is 3.9×109?cm. The value of this resistivity ? is a value derived when the current density is 6.25×10?4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity ?=3.9×109?cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 ×1011?cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 ×107?cm.

Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.

Abstract: A method is provided for producing a nitride compound semiconductor device. A growth substrate has a silicon surface. A buffer layer, which comprises AlxInyGa1-x-yN with 0?x?1, 0?y?1 and x+y?1, is grown onto the silicon surface of the substrate. A semiconductor layer sequence is grown onto the buffer layer. The buffer layer includes a material composition that varies in such a way that a lateral lattice constant of the buffer layer increases stepwise or continuously in a first region and decreases stepwise or continuously in a second region, which follows the first region in the growth direction. At an interface with the semiconductor layer sequence, the buffer layer includes a smaller lateral lattice constant than a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer.

Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.

Abstract: A gallium nitride (GaN) substrate, a semiconductor device, and methods for fabricating a GaN substrate and a semiconductor device are provided. The GaN substrate includes: a GaN base; an aluminum gallium nitride (AlGaN) layer, disposed on the GaN base; and a p-type conducting layer disposed on an active area of the AlGaN layer, and used to exhaust surface state negative electrons on the AlGaN layer and neutralize a dangling bond on the AlGaN layer. The p-type conducting layer is formed on the AlGaN layer, and a hole charge carrier in the p-type conducting layer can be used to exhaust the surface state negative electrons on an n-type AlGaN layer, neutralize the dangling bond on a section of the AlGaN layer, and prevent the forming of a virtual gate, so as to suppress a current collapse effect of the semiconductor device fabricated using the GaN substrate.

Abstract: A high voltage semiconductor structure with a field plate comprising a depletable material that increases the breakdown voltage of the semiconductor structure. A depletion region forms within the depletable field plate which redistributes the electric field and preventing electric charges from concentrating at the corners of the field plate. The thickness, doping concentration, doping uniformity, and geometric shape of the field plates may be adjusted to optimize the effect of the charge redistribution.

Abstract: A semiconductor device includes a first compound semiconductor material, a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material having a first doping concentration and including a different material than the first compound semiconductor material, a control electrode, and at least one buried semiconductor material region having a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the second compound semiconductor material in a region other than a region of the second compound semiconductor material being covered by the control electrode.

Abstract: A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.

Abstract: A system to dynamically configure a conductive pathway and a method of forming a dynamically configurable conductive pathway are described. The system includes a substrate to mechanically support a circuit, and a photosensitive layer disposed on at least a portion of at least one side of the substrate. The system also includes a light source to controllably define the conductive pathway in the photosensitive layer based on photoexcitation of an area of the photosensitive layer corresponding with the conductive pathway, a change in the area photoexcited by the light source facilitating a change in the conductive pathway.

Abstract: A III-nitride power semiconductor device that includes a field relaxation feature to relax the electric fields around the gate thereof to improve the breakdown voltage of the device.

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.

Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.

Abstract: A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

Abstract: A predisposed high electron mobility transistor (HEMT) is disclosed. The predisposed HEMT includes a buffer layer, a HEMT channel layer on the buffer layer, a first HEMT barrier layer over the HEMT channel layer, and a HEMT cap layer on the first HEMT barrier layer. The HEMT cap layer has a drain region, a source region, and a gate region. Further, the HEMT cap layer has a continuous surface on the drain region, the source region, and the gate region. When no external voltage is applied between the source region and the gate region, the gate region either depletes carriers from the HEMT channel layer or provides carriers to the HEMT channel layer, thereby selecting a predisposed state of the predisposed HEMT.

Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.

Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time ?1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.

Abstract: The inventive concept shows the embodiment of t-switch which is a MIT 3-terminal device based on a Hole-driven MIT theory and a technology for removing an ESD noise signal which is one of applications of the t-switch. The t-switch includes three terminals of Inlet, Outlet and Control, and a metal-insulator transition (MIT) occurs at an Outlet layer by a current flowing through the Control terminal. In the t-switch, a high resistor is connected to the Control terminal and thereby an ESD noise signal of high voltage flows through the Inlet-Outlet without damaging the device.