With Specified Semiconductor Materials Patents (Class 257/22)
  • Patent number: 5278430
    Abstract: A complementary semiconductor device incorporating semiconductor composed of diamond. Substantially, diamond is insulative. When both III group elementary atoms and V group elementary atoms are doped into diamond, the doped regions respectively turn into p-type and n-type semiconductors. The embodiment discretely dopes both III group elementary atoms and V group elementary atoms into a layer of diamond thin film to eventually form a complementary semiconductor device. The embodiment forms wiring system inside of the diamond thin film by selectively doping either III group elementary atoms or V group elementary atoms therein without forming wiring system only on the inter-layer insulation film.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: January 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Kakumu
  • Patent number: 5278857
    Abstract: In a semiconductor light-emitting element having a double hetero junction structure of an InGaAP system an n-type dopant, which does not change a crystal structure, is doped in an In.sub.1-y (Ga.sub.1-x Al.sub.x).sub.y P(0.ltoreq.x<1, y.perspectiveto.0.5) active layer, so that an n-type active layer (4), is formed between a p-type InGaAlP cladding layer (5), which has band-gap energy that is larger than that of the active layer (4), and an n-type InGaAlP cladding layer (3), thereby preventing the dopant of the P-type InGaAlP cladding layer (3) from being dispersed into the active layer (4). Thus, the oscillation wavelength of the light-emitting element is not shifted to a short wavelength, and the threshold current of the oscillation is not increased thereby providing an element which can improve yield and reliance.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: January 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shozo Yuge, Hideaki Kinoshita
  • Patent number: 5278427
    Abstract: A high-speed semiconductor device which comprises an emitter layer, a base layer, a collector layer, a potential barrier layer disposed between the emitter layer and the base layer, and a superlattice disposed between the base layer and the collector layer. The superlattice provides a multitude of quantum-mechanical transmission coefficients which can be applied to linear analog circuits and high frequency circuit. In addition, the high speed semiconductor device may act as a frequency multiplier, providing an output signal having 2n times as many frequencies as an input signal when n is the number of energy pass bands in said superlattice below a predetermined applied voltage.
    Type: Grant
    Filed: February 4, 1993
    Date of Patent: January 11, 1994
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Kwong-Kit Choi
  • Patent number: 5274248
    Abstract: The present invention provides a p-n junction type blue luminescence device forming a p-type hole injection layer and having high light-emission efficiency. On an n-conduction type ZnS substrate 111, there is formed a multiquantum well structure 112 alternately laminating a p-type ZnTe layer 112a and a non-doped ZnS layer 112b. And, a positive electrode 113 and a negative electrode 114 are provided on the multiquantum well structure 112 and the ZnS crystal, respectively. By applying forward bias voltage on this light-emitting device, electrons are injected from the n-type ZnS substrate to the multiquantum well structure 112. Then, these electrons are recombined with holes in the multiquantum well structure 112, so as to emit blue luminescence light. Thus, it becomes possible to easily and reproducibly obtain a p-conduction type hole injection layer so as to realize highly concentrated carrier injection and obtain high efficiency in emitting blue luminescence light.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: December 28, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Tadashi Narusawa, Minoru Kubo
  • Patent number: 5274247
    Abstract: An optic modulator which employs strained multiple quantum well structures which are fabricated and spaced from one another such that the stress perpendicular to the direction of the spacing is released leaving only a uniaxial stress along the direction parallel to the spacing. The multiple quantum well structures are then sandwiched between two optic polarizers which are aligned perpendicular to one another. At zero electric field, polarized light passing from the first polarizer is further polarized such that the polarization of the light is rotated to pass through the second polarizer. When an electric field is applied across the heterostructure, light passing through the heterostructure is not further polarized and therefore, the optic signal is interrupted. Thus, optic signals may be modulated with the contrast of polarizing modulators at the speed of superlattice heterostructures.
    Type: Grant
    Filed: May 21, 1992
    Date of Patent: December 28, 1993
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Mitra Dutta, Hongen Shen, Jagadeesh Pamulapati
  • Patent number: 5264711
    Abstract: A polar semiconductor quantum wire for use in electronic and opto-electronic devices. The polar semiconductor quantum wire is either completely or partially encapsulated in metal to reduce the strength of the scattering potential associated with interface optical phonons normally established at the lateral boundaries of polar semiconductor quantum wires. Metal alone or metal employed in conjunction with modulation doping enhances the transport of charge carriers within the polar semiconductor quantum wire.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: November 23, 1993
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Mitra Dutta, Harold L. Grubin, Gerald J. Iafrate, Ki Wook Kim, Michael A. Stroscio
  • Patent number: 5235194
    Abstract: A semiconductor light-emitting device comprises a light-emitting layer including a pn junction formed by a plurality of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x, y.ltoreq.1) layers, and a light-emitting-layer holding layer consisting of an indirect transition type Ga.sub.l-w Al.sub.w As (0.ltoreq.w.ltoreq.1) provided on an opposite side to a light-outputting side. The holding layer has a sufficiently small light absorption coefficient for the light from the light-emitting layer although its band gap is small and improves the light emission efficiency of the semiconductor light-emitting device.
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: August 10, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Izumiya, Yasuo Ohba, Ako Hatano
  • Patent number: 5225692
    Abstract: A non-linear semiconductor optical device comprises a first quantum well layer having discrete quantum levels of carriers including a first quantum level for electrons and a second quantum level for holes with an energy gap corresponding to a wavelength of an incident optical beam; a pair of barrier layers provided above and below the first quantum well layer in contact therewith with a thickness that allows a tunneling of the carriers therethrough for defining a potential well in correspondence to the first quantum well layer; and a second quantum well layer provided in contact with the barrier layers for accepting the carriers that have been created in the first quantum well layer upon excitation by the incident optical beam and escaped therefrom by tunneling through the barrier layer. The second quantum well layer comprises a material that has a conduction band including therein a .GAMMA. valley and an X valley, wherein said .GAMMA.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: July 6, 1993
    Assignee: Fujitsu Limited
    Inventors: Atsushi Takeuchi, Hideaki Ishikawa, Shunichi Muto
  • Patent number: 5216262
    Abstract: A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: June 1, 1993
    Inventor: Raphael Tsu
  • Patent number: 5216261
    Abstract: A non-linear optical device having the TBQ structure comprises an active layer forming a quantum well for interacting with an incident optical beam, an electron removal layer provided adjacent to the active layer at a first side thereof with a first barrier layer intervening therebetween for removing the electrons from the active layer; and a hole removal layer provided adjacent to the active layer at a second, opposite side of the active layer with a second barrier layer intervening therebetween for removing the holes from the active layer; wherein the first and second barrier layers have respective thicknesses determined such that the probability of tunneling of the electrons through the first barrier layer and the probability of tunneling of the holes through the second barrier layer are substantially equal with each other.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: June 1, 1993
    Assignee: Fujitsu Limited
    Inventors: Tsuguo Inata, Shunichi Muto
  • Patent number: 5210428
    Abstract: Carriers are permitted escape from quantum wells within a semiconductor device in the minimum amount of time by utilizing semiconductor material in the barrier layers around the quantum well wherein the barrier layers exhibit an effective bandgap energy less than the sum of the longitudinal optical phonon energy and the exciton absorption energy.
    Type: Grant
    Filed: November 1, 1991
    Date of Patent: May 11, 1993
    Assignee: AT&T Bell Laboratories
    Inventor: Keith W. Goossen
  • Patent number: 5182670
    Abstract: The invention is a filter device of at least two layers, the first layer of Al.sub.x Ga.sub.(1-x) N and the second layer of Al.sub.y Ga.sub.(1-y) N wherein x and y may have any value from 0 to 1. The invention may be used as a fixed wavelength or tunable wavelength filter or in ultraviolet detectors and laser devices, among other systems. Applications for the invention include detection of UV radiation in environments having a high level of incident infrared and visible radiation, as well as applications requiring detection of UV emission when no other radiation is present.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: January 26, 1993
    Assignee: APA Optics, Inc.
    Inventors: Muhammad A. Khan, Jonathon N. Kuznia, James M. Van Hove
  • Patent number: 5181086
    Abstract: A semiconductor structure for a light-interactive semiconductor device includes first and second crystalline semiconductor cladding layers having a first lattice constant and a strained superlattice structure disposed in contact with and between the first and second cladding layers and including alternating first crystalline semiconductor quantum barrier layers having a first and second crystalline semiconductor quantum well layers having a second energy band gap less than the first energy band gap and a third lattice constant wherein the first lattice constant is approximately equal to the average of the second and third lattice constants and the second lattice constant differs from the third lattice constant by at least 0.5 percent of the second lattice constant.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: January 19, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naohito Yoshida
  • Patent number: 5173761
    Abstract: A method and apparatus for contructing diamond semiconductor structures made of polycrystalline diamond thin films is disclosed. The use of a polycrystalline diamond deposition on a substrate material provides an advantage that any substrate material may be used and the ability to use polycrystalline diamond as a material is brought about through the use of an undoped diamond layer acting as an insulating layer which is formed on a boron-doped layer. Because of the structure, ion implantation can be employed to reduce the ohmic contact resistance. The ion implantation also provides that the entire structure can be made using a deep implant to form a channel layer which allows the insulating gate structure to be formed as an integral part of the device. The buried channel can be doped through the use of several implantation steps through the insulating undoped layer.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: December 22, 1992
    Assignee: Kobe Steel USA Inc., Electronic Materials Center
    Inventors: David L. Dreifus, Kumar Das, Koichi Miyata, Koji Kobashi
  • Patent number: 5170226
    Abstract: Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: December 8, 1992
    Assignee: International Business Machines Corporation
    Inventors: Tadashi Fukuzawa, Hiro Munekata
  • Patent number: 5166766
    Abstract: A one-dimensional or two-dimensional transmission mode spatial light modulator (SLM) includes one or more heterojunction acoustic charge transport (HACT) channels 18 with surrounding layers 16,20 vertically adjacent to a multiple quantum well (MQW) region 14, grown above a thick semiconductor substrate 10 thick enough to allow a surface acoustic wave (SAW) to propagate and transparent to the incident light 40. The SAW is injected by a transducer 24, charge is carried to and from the HACT channel 18 by electrodes 32,34,36, and light 40 is applied to a surface 44 perpendicular to the MQW region 14. Each charge packet 19 in the HACT channel 18 invokes an electric field 52 within the MQW region 14 which determines the optical absorption and index-of-refraction thereof, thereby determining the intensity and/or phase of each output light beam 45. Light modulation is achieved by modulating the amount of charge injected.
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: November 24, 1992
    Assignee: United Technologies Corporation
    Inventors: Thomas W. Grudkowski, Robert N. Sacks
  • Patent number: 4835586
    Abstract: A dual-gate vertical field effect transistor comprises an N+ substrate (102) which serves as a drain, and N-epitaxial layer (104) formed on the N+ substrate, and an N+ layer (106) formed at the surface of the epitaxial layer which serves as a source. A plurality of grooves (108a, 108b) extends through the N+ region and a portion of the N-layer. The grooves are lined with an insulating layer (110a, 110b) and filled with a conductive polysilicon gate (112a, 112b). Underneath each of the grooves is a P+ region (116a, 116b) which serves as a second gate. Thus, the transistor in accordance with the present invention includes a set of polysilicon gates and a set of P+ gates for independently modulating the current permitted to flow between the transistor source and drain.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: May 30, 1989
    Assignee: Siliconix Incorporated
    Inventors: Adrian I. Cogan, Richard A. Blanchard
  • Patent number: 4641174
    Abstract: A high speed semiconductor pinch rectifier attains low forward voltage drop and low reverse leakage current by utilizing depletion region pinch-off of conduction channels in a high-resistivity region. In a preferred form, the pinch rectifier additionally utilizes a Schottky barrier contact so as to facilitate device fabrication.
    Type: Grant
    Filed: August 8, 1983
    Date of Patent: February 3, 1987
    Assignee: General Electric Company
    Inventor: Bantval J. Baliga