With Specified Semiconductor Materials Patents (Class 257/22)
  • Patent number: 5479027
    Abstract: An undoped GaAs layer is epitaxially grown on a substrate in a crystal growth device. An undoped Al.sub.x Ga.sub.1-x As layer is then epitaxially grown to form an undoped hetero-junction structure. After this, a sample is transferred to a focused ion beam (FIB) apparatus. A dopant ion beam is focused and implanted into the Al.sub.x Ga .sub.1-x As layer in a dot-like or wire-like pattern so that it does not extend to the undoped GaAs layer or channel layer, and a zero- or one-dimensional carrier gas 8 is generated in the channel layer. The invention allows maskless ion implantation, and makes the fabrication process much easier because quantum wires and dots are drawn, patterned or formed directly by ion implantation. In addition, no etching process is required, so quantum wires and quantum dots can be fabricated precisely.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: December 26, 1995
    Assignee: International Business Machines Corporation
    Inventor: Yoshimine Kato
  • Patent number: 5477377
    Abstract: The present invention relates to novel optical devices operating in the infrared, based on indirect narrow-gap superlattices (INGS) as the active optical materials. The novel optical devices include (1) wideband all-optical switches, which combine small insertion loss at low light intensities with efficient optical switching and optical limiting at high intensities, and (2) wideband infrared detectors with high collection efficiency and low tunneling noise currents, suitable for use in longwave infrared focal plane arrays. INGS comprise multiple semimetal/semiconductor layers having compatible crystal symmetry across each heterojunction between a given semimetal and the adjoining semiconductor, wherein each semimetal layer sandwiched between semiconductor layers is grown thin enough that each semimetal layer becomes a semiconductor, and wherein each semiconductor layer is thin enough that there is coupling between adjacent semiconductor layers.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: December 19, 1995
    Assignees: University of Houston, The United States of America as represented by the Secretary of the Navy
    Inventors: Terry D. Golding, John H. Miller, Jr., Jerry R. Meyer, Eric R. Youngdale, Filbert J. Bartoli, Craig A. Hoffman
  • Patent number: 5475237
    Abstract: A light emitting device is formed of a substrate, a first cladding layer on the substrate, an active layer on the first cladding layer, and a second cladding layer on the active layer. A carrier blocking layer also serving as an etching stopping layer during formation of the second cladding layer is provided between the active layer and the second cladding layer. Both sides of the second cladding layer are filled by a semiconductor layer having a resistance substantially higher than the other layers which the filler layer is in contact with. The first and second cladding layers, active layer, carrier blocking layer, and semiconductor layer of higher resistance comprise a II-VI compound semiconductor.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: December 12, 1995
    Assignee: Sony Corporation
    Inventors: Fumiyo Narui, Masafumi Ozawa
  • Patent number: 5466949
    Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: November 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Yasutoshi Okuno
  • Patent number: 5459332
    Abstract: A semiconductor photodetector employs a multilayer structure for controlling speed, efficiency and noise. A light-absorbing low band gap semiconductor emitter layer produces photogenerated charge upon absorption of light. A semiconductor collector layer collects the photogenerated charge. A semiconductor barrier layer between the light absorbing layer and the collector layer selectively blocks substantially all but photogenerated charge. A base layer may be optionally employed between the barrier layer and the collector layer for gating the current flow and controlling wavelength sensitivity.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: October 17, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas F. Carruthers
  • Patent number: 5453629
    Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A scanning device scans the electrical signals generated by the electric conversion units, and a reading device reads out electrical signals generated by the photoelectric conversion units. Each of the photoelectric conversion units includes a light absorption layer and a multiplication layer. The multiplication layer includes at least one step-back structure which multiplies carriers produced by absorption of light, and in which a forbidden band width changes continuously from a minimum to a maximum width.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: September 26, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ihachiro Gofuku, Masato Yamanobe, Izumi Tabata, Hiraku Kozuka
  • Patent number: 5449922
    Abstract: A bipolar heterojunction diode has an anode (11, 41), a blocking layer (12, 42) and a junction region (13, 14, 43). a heterojunction (32, 58) in the junction region (13, 14, 43) is utilized to create a misalignment between the band gap of the anode (11, 41) and a band gap of the heterojunction (13, 14, 43). The misalignment prevents a depletion region from extending into the heterojunction (13, 14, 43).
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: September 12, 1995
    Assignee: Motorola, Inc.
    Inventors: Jun Shen, Herbert Goronkin, Saied N. Tehrani
  • Patent number: 5449561
    Abstract: The present invention provides for the fabrication of single layer semimetal/semiconductor heterostructures and multilayer semimetal/semiconductor structures. Each semimetal/semiconductor layer fabricated in accordance with the present invention has compatible crystal symmetry across the heterojunction between a semimetal and a semiconductor. A single layer semimetal/semiconductor structure is fabricated by growing a rhombohedral semimetal in a [111] direction on a substrate material having a (111) orientation, and then growing a zincblende semiconductor in a [111] direction on the semimetal. A multilayer semimetal/semiconductor structure may be grown from the single layer semimetal/semiconductor structure by growing an additional rhombohedral semimetal layer in a [111] direction on the preceding semiconductor grown, then growing an additional zincblende semiconductor layer in a [111] direction on the additional semimetal layer, and then repeating this process as many times as desired.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: September 12, 1995
    Assignee: University of Houston
    Inventors: Terry D. Golding, John H. Miller, Jr.
  • Patent number: 5448080
    Abstract: Disclosed is an ultrafast optical switching device having two types of multiple quantum well structures to be connected with each other, the device comprising a semi-insulating substrate; and a first and a second multiple quantum well structure formed sequentially on the substrate and united with each other to produce a double-junction multiple quantum well structure. Each of the multiple quantum well structures has nonlinear optical effects and two life time constants present while switching off in the device. One of the life time constants corresponds to a short life time constant to be determined dependent on electrons in the double-junction multiple quantum well structure and the other of the life time constants corresponds to a long life time constant to be determined dependent on holes and lattices therein.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: September 5, 1995
    Assignee: Electronics and Telecommuncations Research Institute
    Inventors: Seon-Gyu Han, Jong-Tai Lee, Byueng-Su Yoo, Tae-Hyung Zyung, Young-Wan Choi, Pyong-Woon Park, El-Hang Lee
  • Patent number: 5442205
    Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: August 15, 1995
    Assignee: AT&T Corp.
    Inventors: Daniel Brasen, Eugene A. Fitzgerald, Jr., Martin L. Green, Donald P. Monroe, Paul J. Silverman, Ya-Hong Xie
  • Patent number: 5440148
    Abstract: A quantum operational device includes a plurality of quantum boxes arranged in a plurality of stages isolated by a distance which permits tunnelling of electrons or holes through the distance, uses as bit information the presence or absence of an electron or a hole in each of the quantum boxes, and prohibits tunnelling of an electron or a hole from a quantum box in a stage to another quantum box in an adjacent stage when an electron or a hole exists in the quantum box in the adjacent stage. The device only needs quite low power, performs operation at a high speed, and can be fabricated by a simple manufacturing process.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: August 8, 1995
    Assignee: Sony Corporation
    Inventor: Kazumasa Nomoto
  • Patent number: 5436468
    Abstract: On a substrate having a surface slightly tilted by an angle .alpha. within the range of from 0.5 to 10 degrees from the (110) plane in the <00-1> direction, a superlattice structure having a periodicity in both <110> and <001> directions is formed. Various band structures are possible by selecting an appropriate constituent material and periodicity for the superlattice structure. When current flows in a direction without periodicity, a very high mobility is obtained as a result of suppressed alloy scattering. If current is caused to flow in a direction with periodicity, and the periodicity is properly selected, optical phonon scattering can also be suppressed.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: July 25, 1995
    Assignee: Fujitsu Limited
    Inventors: Yoshiaki Nakata, Osamu Ueda, Satoshi Nakamura
  • Patent number: 5436469
    Abstract: A room temperature high speed transistor that does not suffer deleterious effects from plasmon scattering. The transistor of the present invention comprises a semiconducting base region having a type of majority carriers and sub-band ordering associated with the majority carriers. The transistor further comprises a semiconducting collector region contacting the base region at a collector-base heterojunction, the semiconducting collector region having the same type of majority carriers as the semiconducting base region and having a sub-band ordering different than that of the base region. The transistor further comprises a semiconducting emitter region contacting the base region at an emitter-base heterojunction, the semiconducting emitter region having the same type of majority carriers as the semiconducting base region. In active operation of the transistor of the present invention, carriers are injected from a main sub-band in the emitter region into a satellite sub-band the base region.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: July 25, 1995
    Inventor: Nicolas J. Moll
  • Patent number: 5420442
    Abstract: High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al.sub.x Ga.sub.1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al.sub.y Ga.sub.1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: May 30, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Thomas C. Hasenberg, April S. Brown, Lawrence E. Larson
  • Patent number: 5416337
    Abstract: The present invention is a hetero superlattice pn junction. In particular, the invention combines n and p type superlattices into a single pn junction having a bandgap sufficient to create high frequency (i.e. blue or higher) light emission. Individual superlattices are formed using a molecular beam epitaxy process. This process creates thin layers of well material separated by thin layers of barrier material. The well material is doped to create carrier concentrations and the barrier materials are chosen in combination with the thickness of the well materials to adjust the effective bandgap of the superlattice in order to create an effective wide bandgap material. The barrier material for the n and p type superlattices is different from the material used to form either of the two types of well layers.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: May 16, 1995
    Assignee: International Business Machines Corporation
    Inventors: Leroy L. Chang, Supratik Guha, Hiroo Munekata
  • Patent number: 5415699
    Abstract: A superlattice comprising alternating layers of (PbTeSe).sub.m and (BiSb).sub.n (where m and n are the number of PbTeSe and BiSb monolayers per superlattice period, respectively) having engineered electronic structures for improved thermoelectric cooling materials (and other uses) may be grown by molecular beam epitaxial growth. Preferably, for short periods, n+m<50. However, superlattice films with 10,000 or more such small periods may be grown. For example, the superlattice may comprise alternating layers of (PbTe.sub.1-z Se.sub.z).sub.m and (Bi.sub.x Sb.sub.1-x).sub.n. According to a preferred embodiment, the superlattice comprises a plurality of layers comprising m layers of PbTe.sub.0.8 Se.sub.0.2 and n layers of Bi.sub.0.9 Sb.sub.0.1, where m and n are preferably between 2 and 20.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: May 16, 1995
    Assignee: Massachusetts Institute of Technology
    Inventor: Theodore Harman
  • Patent number: 5414274
    Abstract: A quantum multifunction transistor including a plurality of conduction layers of semiconductor material with a tunnel barrier layer sandwiched therebetween. The conduction layers each being very thin to form discrete energy levels, and the material being chosen so that discrete energy levels therein are not aligned across the tunnel barrier layer in an equilibrium state. A gate coupled to a portion of one of the conduction layers for aligning, in response to a voltage applied thereto, discrete energy levels in the conduction layers across the tunnel barrier layer, whereby majority carrier current flows through the transistor. Application of a higher voltage to the gate results in minority carrier current flow through the transistor.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: May 9, 1995
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Saied N. Tehrani, Jun Shen, Xiaodong T. Zhu
  • Patent number: 5412232
    Abstract: In a semiconductor device having quantum wire structure formed by first and second semiconductor layers, the first and the second semiconductor layers are used as quantum well and quantum barrier layers, respectively. The quantum well layer has a first conduction band having a first .GAMMA.-valley and a first L-valley. The first .GAMMA.-valley has a first .GAMMA.-valley energy level. The first L-valley has a first L-valley energy level which is not lower than the first .GAMMA.-valley energy level. The quantum barrier layer has a second conduction band having a second energy level which is higher than the first L-valley energy level. The quantum wire structure is extended towards a predetermined direction. More particularly, the predetermined direction is parallel to a crystal orientation of (100).
    Type: Grant
    Filed: March 11, 1993
    Date of Patent: May 2, 1995
    Assignee: NEC Corporation
    Inventor: Yuji Ando
  • Patent number: 5408120
    Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density i.sub.H -layer. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: April 18, 1995
    Assignees: Toyoda Gosei Co., Ltd., Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Katsuhide Manabe, Masahiro Kotaki, Makoto Tamaki, Masafumi Hashimoto
  • Patent number: 5408107
    Abstract: Heterostructure barrier quantum well device with a super-lattice structure of alternating lightly doped and heavily doped spacer layers having multiple, stable current-voltage curves extending continuously through zero bias at ambient temperature. The device can be repetitively switched between the multiple current-voltage curves. Once placed on a particular curve, the device retains memory of the curve it has been set on, even if held at zero bias for extended periods of time. The device can be switched between current-voltage curve settings at higher positive or negative voltages and can be read at lower voltages. Switching between current-voltage curve settings can also be effected by additional terminal connection(s) to the spacer layer(s).
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: April 18, 1995
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Dean P. Neikirk, Kiran K. Gullapalli
  • Patent number: 5404027
    Abstract: A buried-ridge or buried-heterostructure II-VI laser diode. Polycrystalline II-VI semiconductor such as ZnS, ZnSSe, ZnSe or CdS deposited by vacuum evaporation buries the etched ridge.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: April 4, 1995
    Assignee: Minnesota Mining & Manufacturing Compay
    Inventors: Michael A. Haase, Jun Qiu, Hwa Cheng, James M. DePuydt
  • Patent number: 5399880
    Abstract: A long wavelength (6 to 20 .mu.m) phototransistor is described which has n-doped silicon as emitter and collector regions bracketing a base region having a quantum well structure made up of alternating layers of p-doped silicon germanium and undoped silicon, The silicon germanium layer adjacent to the emitter region is thicker and has a higher percentage of germanium in order to provide a quantum well that is wider and deeper than the other quantum wells in the base region thereby resulting in a larger current and optical gain. The silicon barrier layer of the quantum well closest to the collector region is p-doped in order to reduce the leakage current of the base-collector junction.
    Type: Grant
    Filed: August 10, 1993
    Date of Patent: March 21, 1995
    Assignee: AT&T Corp.
    Inventor: Naresh Chand
  • Patent number: 5377214
    Abstract: There is disclosed a tensile strained blue-green II-VI quantum well laser. The tensile strained blue-green II-VI quantum well laser comprises of a semiconductor substrate; a buffer layer formed on the semiconductor substrate; a first ZnSe cladding layer formed on the buffer layer; a multi-quantum well layer formed on the first ZnSe cladding layer, consisting of a ZnS.sub.y Se.sub.1-y active region and a Mg.sub.z Zn.sub.1-z S.sub.w Se.sub.1-w barrier region; a current-restricting layer formed on the multi-quantum well layer; a second ZnSe cladding layer formed on the current-restricting layer; and a cap layer formed on the second ZnSe cladding layer. The inventive tensile strained blue-green II-VI quantum well laser is capable of reducing the oscillation wavelength into not more than 500 nm at room temperature and of lowering the threshold current density to as low as 1,000 A/cm.sup.2.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: December 27, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Do Y. Ahn
  • Patent number: 5373167
    Abstract: An opto-electronic device with the physical and chemical characteristics at the junction thereof being well matched is disclosed. The opto-etectronic device includes a wafer, a first layer grown on the wafer, and a second layer grown on the first layer, wherein one of the first and second layers is an ordered structure while the other is a disordered structure.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: December 13, 1994
    Assignee: National Science Counsel
    Inventors: Ming-Kwei Lee, Ray-Hwa Horng, Lin-Hung Haung
  • Patent number: 5371756
    Abstract: A semiconductor blue-green light emitting device in a double heterostructure configuration includes a light emitting layer, a p-type clad layer and an n-type clad layer sandwiching the light emitting layer, a cap layer and a contact layer in this sequence formed on the clad layer. The light emitting layer contains at least one of CdZnSe, ZnSSe, and ZnSe, each of the p-type clad layer and the n-type clad layer contains at least one of ZnSSe, ZnSe and ZnMgSSe, the cap layer is of (Al.sub.X Ga.sub.1-X).sub.0.5 In.sub.0.5 P (0.ltoreq.X.ltoreq.1), and the contact layer is of Al.sub.X Ga.sub.1-X As (0.ltoreq.X.ltoreq.1). The diode provided is with improved ohmic characteristics.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: December 6, 1994
    Assignee: NEC Corporation
    Inventor: Hiroaki Fujii
  • Patent number: 5362972
    Abstract: A field effect transistor and a ballistic transistor using semiconductor whiskers each having a desired diameter and formed at s desired location, a semiconductor vacuum microelectronic device using the same as electron emitting materials, a light emitting device using the same as quantum wires and the like are disclosed.
    Type: Grant
    Filed: April 17, 1991
    Date of Patent: November 8, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Masamitsu Yazawa, Kenji Hiruma, Toshio Katsuyama, Nobutaka Futigami, Hidetoshi Matsumoto, Hiroshi Kakibayashi, Masanari Koguchi, Gerard P. Morgan, Kensuke Ogawa
  • Patent number: 5359256
    Abstract: A non-power generating current limiting device such as a field effect transistor is provided to output a regulated current in dependence upon a control voltage. An electron field emitter is connected to a drain or output of the non-power generating current limiting device to receive the regulated current. A tip of the electron field emitter emits electrons towards a collector anode. An extractor gate can be provided between the electron field emitter and the collector anode to control the rate of electron emission from the electron field emitter. Because the non-power generating current limiting device regulates the current to the electron field emitter, a maximum current output of the electron field emitter is limited to the regulated current from the voltage controlled current source. The electron field emitter is thus protected from destruction due to excess current. The non-power generating current limiting device can also be used to modulate electron emission from the field emitter.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: October 25, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Henry F. Gray
  • Patent number: 5349201
    Abstract: A heterojunction bipolar transistor (HBT) (10,30) includes an indium-gallium-arsenide (InGaAs), indium-phosphide (InP) or aluminum-indium-arsenide (AlInAs) collector layer (14) formed over an indium-phosphide (InP) substrate (12). A base layer (16,32) including gallium (Ga), arsenic (As) and antimony (Sb) is formed over the collector layer (14), and an AlInAs or InP emitter layer (18) is formed over the base layer (16,32). The base layer may be ternary gallium-arsenide-antimonide (GaAsSb) doped with beryllium (Be) (16), or a strained-layer-superlattice (SLS) structure (32) including alternating superlattice (32b,32a) layers of undoped gallium-arsenide (GaAs) and P-doped gallium-antimonide (GaSb). The GaSb superlattice layers (32a) are preferably doped with silicon (Si), which is much less diffusive than Be.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: September 20, 1994
    Assignee: Hughes Aircraft Company
    Inventors: William E. Stanchina, Thomas C. Hasenberg
  • Patent number: 5349202
    Abstract: A tunneling transistor comprising an emitter layer, a barrier layer having a conduction band higher in energy than a conduction band of said emitter layer and a valence band lower in energy than a valence band of said emitter layer, and further having a thickness with which electrons can substantially tunnel the barrier layer, a collector layer having a conduction band lower in energy than the valence band of said emitter layer and a conductivity type opposite to said emitter layer, and further having a thickness with which quantum levels are substantially formed, a gate layer having a conduction band higher in energy than the conduction band of said layer and a valence band of said emitter layer, and further having a thickness with which the probability of electron tunneling is substantially greatly reduced, said layers been laminated in this order, and electrodes which form ohmic junctions on said emitter layer and said collector layer and an electrode which forms a Schottky junction on said gate layer.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: September 20, 1994
    Assignee: NEC Corporation
    Inventor: Tetsuya Uemura
  • Patent number: 5343056
    Abstract: A compound semiconductor device includes an undoped semiconductor layer; a doped semiconductor layer formed on the undoped semiconductor layer and having smaller electron affinity than the undoped semiconductor layer, impurities being doped in the doped semiconductor layer; a gate electrode formed on the doped semiconductor layer; and a source electrode and a drain electrode respectively formed at both sides of the gate electrode, wherein an impurity concentration of the doped semiconductor layer is selected such that a portion of the doped semiconductor layer located immediately below the gate electrode is not completely depleted in a state in which a gate voltage is not applied to the gate electrode, and is completely depleted in a state in which a negative voltage for minimizing a noise figure is applied to the gate electrode.
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: August 30, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshikazu Nakagawa
  • Patent number: 5343057
    Abstract: This transistor incorporates at least one first stack of semi-conductor conduction layers and at least one second stack of semiconductor layers with a single, highly doped thin film within the second stack giving it the character of a mobile electric charge donor, superimposed and supported by a substrate as well as at least two potential barriers located in the second stack on either side of the doped thin film in order to reduce the concentration of carriers in said second stack a metal gate resting on the second stack for modifying the concentration of carriers of the charges in the first stack, two ohmic contacts being placed on one of the stacks, on either side of the gate and serving as the source and drain.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: August 30, 1994
    Assignee: France Telecom Establissement Autonome de Droit Public
    Inventors: Jean-Michel Gerard, Jacques Favre
  • Patent number: 5336901
    Abstract: A semiconductor structure comprises a first material layer of a homopolar material having a conduction band that includes an L valley and a .GAMMA. valley such that the L valley has an energy level lower than the .GAMMA. valley when in a bulk crystal state, and a second material layer of a polar compound formed with an epitaxial relationship with respect to the first material layer; wherein the first material layer has a thickness such that there is formed first and second quantum levels respectively in correspondence to the .GAMMA. valley and the L valley such that: the second quantum level has an energy level higher than the first quantum level.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: August 9, 1994
    Assignee: Fujitsu Limited
    Inventor: Takuma Tsuchiya
  • Patent number: 5332910
    Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: July 26, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Haraguchi, Kenji Hiruma, Kensuke Ogawa, Toshio Katsuyama, Ken Yamaguchi, Toshiyuki Usagawa, Masamits Yazawa, Toshiaki Masuhara, Gerard P. Morgan, Hiroshi Kakibayashi
  • Patent number: 5331180
    Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layer. Without drying the porous semiconductor layer, it is then dipped in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: July 19, 1994
    Assignee: Fujitsu Limited
    Inventors: Masao Yamada, Motoo Nakano, George J. Collins, Tetsuro Tamura, Akira Takazawa
  • Patent number: 5329136
    Abstract: A tunable monolithic integrated photodetector (10) detects a selected wavelength of incident light within a wavelength range. The photodetector comprises a multiple quantum well (MQW) filter means for receiving and filtering the incident light, and an MQW detector means for receiving light from the MQW filter means and for detecting the selected wavelength. A fixed voltage bias V.sub..DELTA. is disposed between the filter means and the detector means for causing the filter means to absorb light wavelengths around the selected wavelength to thereby enhance the detectability of the selected wavelength. Further, a variable voltage bias V.sub.P is selectively and proportionally imposed on both the filter means and the detector means for permitting tuning of the photodetector. A fixed filter may also be employed for filtering the incident light so that light wavelengths which are outside the range of the photodetector are eliminated.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: July 12, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Keith W. Goossen
  • Patent number: 5326985
    Abstract: A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: July 5, 1994
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Jun Shen, Saied N. Tehrani
  • Patent number: 5324959
    Abstract: A semiconductor device includes a region in which carriers are transferred in the lamination direction of a multiple quantum well, such as a multiple quantum well multiplication layer of a superlattice APD. A superlattice structure with a varying well width is introduced to a hetero-interface present in the transfer region, thereby preventing pile-up of the carriers.
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: June 28, 1994
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hitoshi Nakamura, Shoichi Hanatani, Chiaki Notsu, Tsukuru Ohtoshi, Koji Ishida
  • Patent number: 5323019
    Abstract: A multiple quantum well optical modulator comprising a multiple quantum well structure embedded in the intrinsic region of an s-i-n+ semiconductor. The s-i-n+ structure causes an electric field to be applied to the multiple quantum well structure which causes uncoupling of the el energy confined level of one layer and the x level of the adjacent layer, thereby changing the absorption of the light and causing modulation thereof.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: June 21, 1994
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Mitra Dutta, Hongen Shen
  • Patent number: 5323020
    Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: June 21, 1994
    Assignee: International Business Machines Corporation
    Inventors: S. Noor Mohammad, Robert B. Renbeck
  • Patent number: 5315128
    Abstract: Described is a resonant-cavity p-i-n photodetector based on the reflection or transmission through a Fabry-Perot cavity incorporating non-epitaxial, amorphous layers with alternating refractive index difference which layers are electron-beam deposited on a light-gathering side of a commercially available photodetector. The materials of the Fabry-Perot cavity are selectable from materials, refractive indices of which fall within a large range (from n=1.26 for CaF.sub.2 to n=3.5 for Si) preferably from materials which are depositable in an amorphous state. The material combinations are selected so that only wavelengths resonant with the cavity mode will be detected. The microcavity of the RC-PIN design can also be deposited on any existing detector structure, without modification of semiconductor growth. Such a photodetector would be useful for wavelength de-multiplexing applications.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: May 24, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Neil E. J. Hunt, Erdmann F. Schubert, George J. Zydzik
  • Patent number: 5302847
    Abstract: A III-V semiconductor heterojunction in which a capping layer (14) is formed between the two layers (10, 16) of the heterojunction to prevent any deleterious effects due to As-P exchange. When InAlAs is grown on InP, the capping layer is AlP. When GaAs is grown on GaInP, the capping layer is GaP.
    Type: Grant
    Filed: June 4, 1993
    Date of Patent: April 12, 1994
    Assignee: Bell Communications Research, Inc.
    Inventors: Rajaram Bhat, Maria J. S. P. Brasil, Robert E. Nahory, William E. Quinn, Maria C. Tamargo
  • Patent number: 5298763
    Abstract: A semiconductor structure that provides intrinsic doping from native defects is provided. A quantum well including a narrow bandgap material (11, 14) having a low concentration of native defects is sandwiched between two wide bandgap spacer layers (12, 20, 17, 15). The spacer layers (12, 20, 17, 15) have a low concentration of native defects. At least one doping region (13, 16) having a high concentration of native defects positioned adjacent to one of the undoped spacer layers (12, 17).
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: March 29, 1994
    Assignee: Motorola, Inc.
    Inventors: Jun Shen, Saied Tehrani, Herbert Goronkin
  • Patent number: 5298767
    Abstract: A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.
    Type: Grant
    Filed: October 6, 1992
    Date of Patent: March 29, 1994
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Joseph S. Shor, Anthony D. Kurtz
  • Patent number: 5296718
    Abstract: ZnSSE mixed crystal semiconductors and ZnCdSe mixed crystal semiconductors are alternately laminated on a single crystal substrate composed of a III-V or II-VI compound to form a light emitting semiconductor device of a multilayer structure so that electrons and holes are efficiently confined therein. This increases the carrier recombination probability and emission efficiency. A device may be arranged where mixed crystal semiconductors of two types respectively having different component compositions of Zn.sub.1-x1 Cd.sub.x1 S.sub.y1 Se.sub.1-y1 and Zn.sub.1-x2 Cd.sub.x2 S.sub.y2 Se .sub.1-y2 are alternately laminated on a single crystal substrate composed of a III-V or II-VI compound such that the ratio of components of the mixed crystal semiconductors of two types satisfies the relationship that x.sub.1 is smaller than x.sub.2 and y.sub.1 is greater than y.sub.2. Alternately, a device may be arranged where a Zn.sub.1-x Cd.sub.x S.sub.y Se.sub.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: March 22, 1994
    Assignee: Seiwa Electric Mfg. Co., Ltd.
    Inventors: Shigeo Fujita, Shizuo Fujita
  • Patent number: 5296721
    Abstract: A double barrier tunnel diode (10) has a quantum well (12), a pair of electron injection layers (16) on either side of the quantum well (12), and a barrier layer (14) between each of the electron injection layers (16) and the quantum well (12), in a strained biaxial epitaxial relationship with the quantum well (12). The material of the quantum well (12) is chosen such that the biaxial strain is sufficient to reduce the energy of heavy holes in the quantum well (12) to less than the energy of the conduction band minimum energy of the electron injection layers (16). Preferably the quantum well (12) is made of gallium antimonide with from about 1 to about 40 atomic percent arsenic alloyed therein, the electron injection layers (16) are made of indium arsenide, and the barrier layers (14) are made of aluminum antimonide.
    Type: Grant
    Filed: July 31, 1992
    Date of Patent: March 22, 1994
    Assignee: Hughes Aircraft Company
    Inventors: Joel N. Schulman, David H. Chow
  • Patent number: 5294809
    Abstract: A resonant tunneling diode having a quantum well sandwiched between first and second tunnel barrier layers and the quantum well and tunnel barrier layers sandwiched between an injection layer and a collector layer. The improvement includes a relatively thin layer of semiconductor material sandwiched between either the first tunnel barrier layer and the injection layer or the first tunnel barrier layer and the quantum well. The thin semiconductor layer has a valence band with an energy level lower than the valence band of the first tunnel barrier layer so as to prevent minority carriers from travelling toward the injection layer.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: March 15, 1994
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Saied N. Tehrani, Jun Shen, Xiaodong T. Zhu
  • Patent number: 5289014
    Abstract: A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: February 22, 1994
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Jun Shen, Saied Tehrani, X. Theodore Zhu
  • Patent number: 5283444
    Abstract: A heterojunction acoustic charge transport device (HACT) having a charge transport channel 39 which is sandwiched between upper and lower charge confinement layers, 14,20, has the charge transport channel 39 made of a Strained Layer Superlattice (SLS) comprising alternating deep-well semiconductor layers 40, that provide a deep quantum well depth, and strain relief layers 42 that provide strain relief to prevent dislocations from occurring due to lattice mismatches between the InGaAs layers within the channel 39 and the charge confinement layers 14,20, thereby allowing the overall thickness of the channel 39 to be at least as wide as conventional HACT devices that use a GaAs channel. The strain relief layers 42 may be narrowly sized to allow tunneling of electrons across the entire channel 39 thereby allowing the charge to move as a single group, or alternatively, widely sized to provide separate isolated channels thereby allowing the charge to move in separate groups.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: February 1, 1994
    Assignee: United Technologies Corporation
    Inventors: Robert N. Sacks, Thomas W. Grudkowski, Donald E. Cullen, William J. Tanski
  • Patent number: 5281543
    Abstract: Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted.
    Type: Grant
    Filed: July 13, 1992
    Date of Patent: January 25, 1994
    Assignee: International Business Machines Corporation
    Inventors: Tadashi Fukuzawa, Hiro Munekata
  • Patent number: 5280180
    Abstract: A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.
    Type: Grant
    Filed: August 19, 1992
    Date of Patent: January 18, 1994
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Jun Shen, Saied Tehrani, Raymond K. Tsui, X. Theodore Zhu