With Specified Semiconductor Materials Patents (Class 257/22)
  • Publication number: 20020047115
    Abstract: A charge storing layer of a photodiode having an N-type conductivity includes an N30 -type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.
    Type: Application
    Filed: December 21, 2001
    Publication date: April 25, 2002
    Applicant: NEC CORPORATION
    Inventors: Yukiya Kawakami, Akihito Tanabe, Nobuhiko Mutoh
  • Patent number: 6376858
    Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: April 23, 2002
    Assignee: Hughes Electronics Corp.
    Inventor: Joel N. Schulman
  • Patent number: 6372980
    Abstract: A two-terminal tandem solar cell is provided. The inclusion of thin (few nm-thick) narrow band-gap InGaAs quantum wells in the intrinsic (i) region of the conventional p-i-n GaAs solar cell extends the photo-absorption of the conventional GaInP/GaAs tandem cell toward the infrared. Beginning-of-Life efficiencies in excess of 30% are predicted. Modeling data indicate end-of-life efficiency of these cells will exceed 25% AM0.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: April 16, 2002
    Assignee: University of Houston
    Inventor: Alexandre Freundlich
  • Publication number: 20020038866
    Abstract: A light-emitting diode having an excellent high-speed response characteristic and capable of giving a large light output with a small variation of the light output during the operation is provided. In the light-emitting diode, an active layer comprising a single quantum well layer of p-type Ga0.51In0.49P, a lower barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P and an upper barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P is highly doped with p-type dopant (Zn, Mg, Be, C) or n-type dopant (Si, Se, Te) to produce non-radiative recombination level in the upper and lower barrier layers. Carriers injected into the quantum well layer not only recombine radiatively therein and also recombine nonradiatively at boundaries of the upper barrier layer and the lower barrier layer, remarkably increasing recombination velocity of carriers and dramatically improving the response characteristic.
    Type: Application
    Filed: September 10, 2001
    Publication date: April 4, 2002
    Inventors: Hiroshi Nakatsu, Takahisa Kurahashi, Tetsurou Murakami, Shouichi Ohyama
  • Patent number: 6348698
    Abstract: A light emitting device is provided, which comprises a III-V semiconductor alloy layered structure as an active layer thereof, including N and at least one other group-V element, and at least one group-III element. The light emitting device is in use for red wavelength laser diodes having excellent temperature characteristics, visible wavelength laser diodes which may achieve emissions shorter wavelengths than 600 nm, visible region light emitting diodes having a high intensity, laser diodes for optical communication having excellent temperature characteristics, and similar light emitting devices. The III-V semiconductor alloy layered structure is provided to be used as an active layer for forming the light emitting device, which comprises first and second monatomic layers.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: February 19, 2002
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato
  • Patent number: 6342411
    Abstract: A high voltage microwave field effect transistor (FET) and method for its manufacture. The FET (10) includes a channel layer (18) formed of compressively strained GaInP. Carrier confinement layers (16), (20) formed of tensile strained (AlGa)InP are formed both above (20) and below (16) the channel layer (20) to confine the carriers to the channel layer (20) and to provide a high breakdown voltage.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: January 29, 2002
    Assignee: Motorola Inc.
    Inventor: Bobby L. Pitts, Jr.
  • Patent number: 6333516
    Abstract: An inverter comprising four quantum dot cells. When the quantum dot cells are arranged in 9 o'clock direction, 12 o'clock direction and 3 o'clock direction, the quantum dot cell is arranged in 6 o'clock direction.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riichi Katoh, Tetsufumi Tanamoto, Francis Minoru Saba, Yujiro Naruse, Shigeki Takahashi, Masao Mashita
  • Patent number: 6329667
    Abstract: A nitride semiconductor light emitting device having preferable light emitting characteristics even if dense threading dislocations extend through single crystal layers. The nitride semiconductor light emitting device includes an active layer obtained by depositing group-3 nitride semiconductors, and a barrier layer disposed adjacent to the active layer and having a greater bandgap than that of the active layer, the active layer having barrier portions which surround the threading dislocations and are defined by interfaces enclosing the threading dislocation and which are made of the same material as that of the barrier layer.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: December 11, 2001
    Assignee: Pioneer Corporation
    Inventors: Hiroyuki Ota, Mitsuru Nishitsuka, Hirokazu Takahashi
  • Patent number: 6326650
    Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brillouin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: December 4, 2001
    Inventor: Jeremy Allam
  • Patent number: 6326639
    Abstract: The present invention relates to a semiconductor hetereostructure radiation detector for wavelengths in the infrared spectral range. The semiconductor heterostructure radiation detector is provided with an active layer composed of a multiplicity of periodically recurring single-layer systems each provided with a potential well structure having at least one quantum well with subbands (quantum well), the so-called excitation zone, which is connected on one side to a tunnel barrier zone, whose potential adjacent to the excitation zone is higher than the band-edge energy of a drift zone adjoining on the other side of the potential-well structure.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: December 4, 2001
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Harald Schneider, Martin Walter
  • Patent number: 6310373
    Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: October 30, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo
  • Publication number: 20010032977
    Abstract: A stacked material free from a degraded quality of crystal, formed with a precise periodicity, and fabricated without relying on the vapor phase growth method is provided. An optical function device using the stacked material is also provided. A starting stacked material composed of two alternate layers (A), (B) having different refractive indexes is stacked over two periods or more by a substrate bonding method to provide a multi-periodic stacked structure.
    Type: Application
    Filed: April 26, 1999
    Publication date: October 25, 2001
    Inventors: TAKAO ABE, HIROJI AGA
  • Patent number: 6303941
    Abstract: Presented is an integrated asymmetric resonant tunneling diode pair circuit exhibiting current-voltage characteristics providing multistable states which may be tailored for multistable solutions. Also presented are apparatus incorporating the invention therein, for which the invention provides a simple, integrated design that greatly reduces circuit complexity and size. The present invention is useful in all applications utilizing multiple peak characteristics of the current-voltage curve, such as multiple-valued logic analog-to-digital quantizers, frequency multiplication devices, waveform scrambling devices, memory operations, and parity-bit generation, among others.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: October 16, 2001
    Assignee: HRL Laboratories
    Inventors: Yi-Ming Xie, Joel N. Schulman, David H. Chow
  • Patent number: 6292089
    Abstract: A structure for temperature sensors and infrared detectors. The structure is built-up on a substrate that includes a thermistor layer, wherein the resistance of the thermistor layer is temperature dependent. The substrate also includes an electric contact layer on both sides of the thermistor layer, and the resistance of the thermistor layer is measured between the contact layers. The thermistor layer includes a monocrystalline quantum well structure that includes alternating quantum well layers and barrier layers. One or more of the bandedge energy of the barrier layers, the quantum well layer doping level, the quantum well layer thickness, and the barrier layer thickness is adapted to obtain a temperature coefficient predetermined for the structure.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: September 18, 2001
    Assignee: IMC Industriellt Mikroelektronikcentrum AB
    Inventor: Jan Andersson
  • Patent number: 6291832
    Abstract: A method/system for forming a resonant tunneling diode latch is disclosed. The method/system comprises the steps of forming a gate on a silicon substrate, the silicon substrate having at least one SOI layer disposed therein, providing an oxide spacer over the gate, providing a first ion implant in a first region of the silicon substrate, and then providing an oxide layer. The method further comprises polishing the oxide back to the gate, removing the gate, providing a second ion implant in a second region of the silicon substrate wherein the first and second regions have an undoped portion of silicon there between. According to the present invention, the method/system for forming a resonant tunneling diode latch in an SOI substrate that is easily implemented and results in an increased throughput of resonant tunneling diode devices.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: September 18, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Patent number: 6288410
    Abstract: An optical semiconductor device includes a substrate and an active region formed on the substrate. The active region includes a plurality of quantum well layers containing at least one tensile-strained well layer, and the plurality of quantum well layers include a plurality of quantum well layers whose band gaps are different from each other. Such an active region makes it possible to expand a wavelength range over which TE-mode and TM-mode gains balance with each other or are approximately equal to each other.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: September 11, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventor: Seiichi Miyazawa
  • Patent number: 6281518
    Abstract: A layered structure of a III-V semiconductor alloy is disclosed, including N and at least one of the other group-V elements and a plurality of the group-III elements, capable of having an improved crystallinity, and of being grown with an arbitrary elemental composition together with a higher N content. The III-V semiconductor alloy is composed of GaxIn1−xNyAs1−y (0<x<1 and 0<y<1) and the layered structure includes at least two kinds of monoatomic layers. The monoatomic layers each have a composition of Gax1In1−x1Ny1As1−y1, (0<x1≦1 and 0<y1<1) with either none or a first minimal In content, and of Gax2In1−x2Ny2As1−y2 (0≦x2<x1≦1 and 0<y2<1) with either a second In content larger than the first In content, or none of Al or Ga content, respectively, and are deposited in a predetermined order, to thereby result in a superlattice structure which is considered to be a a semiconductor alloy layer having a deduced average composition.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: August 28, 2001
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato
  • Patent number: 6278820
    Abstract: A traveling-wave photodetector (10, 22, 30) having a waveguide layer (12) separated, such as by an intermediate layer (24), from an absorbing layer (14). Absorbed power is spread out, minimizing thermal heating of the photodetector (10, 22, 30). Light travels through a weakly absorbing optical waveguide (12) and the electrical current generated by the absorbed light is collected by electrodes (18, 36). The juxtaposition of the waveguide layer (12) and the absorbing layer (14) eliminates electron and hole trapping allowing high-power and large bandwidth operation of the traveling-wave photodetector (10, 22, 30).
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: August 21, 2001
    Assignee: The Boeing Company
    Inventor: Robert R. Hayes
  • Patent number: 6274882
    Abstract: The alloy is for making an infrared transducer. It is constituted by (In1−xTlx) (As1−ySby) in which 0≦x<1 and 0<y<1 (where x and y are less than ½). On a GaSb or AlSb substrate, the transducer comprises an active layer of the alloy having a composition such that its lattice is of a size that is equal to that of the substrate material.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 14, 2001
    Assignee: Sagem SA
    Inventors: Christian Verie, Dominique Lorans, Michel Poirier
  • Patent number: 6265823
    Abstract: The light emitter is fabricated from a silicon substrate (2) that has a layer of porous silicon (3) on its upper surface. A hole transporter (4) is applied to the upper surface of the porous silicon (2) and penetrates the channels (3′) formed within the porous silicon. An upper semitransparent p-type material such as NiO is used as the upper contact (5) to the hole transporter and a further contact is formed on the base of the silicon wafer (2). The penetration of the hole transporter into the interstices between the silicon particles significantly improves the efficiency of the light emitter by up to two orders of magnitude. The light emitter is particularly suited to use in VLSI and display applications.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: July 24, 2001
    Assignee: Isis Innovation Limited
    Inventors: Peter James Dobson, Gareth Wakefield
  • Patent number: 6252262
    Abstract: A passivating layer is provided for a III-V semiconductor. The passivating layer is preferably made of Fe and is used with III-V (especially GaAs) devices. At least one full monolayer of the passivating layer is formed, so that one full monolayer of the passivating layer bonds with one full monolayer of the atomic species of the semiconductor.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: June 26, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: B. T. Jonker, O. J. Glembocki, R. T. Holm
  • Patent number: 6239450
    Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: May 29, 2001
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: James F. Harvey, Robert A. Lux, Raphael Tsu
  • Patent number: 6239449
    Abstract: A photodetector capable of normal incidence detection over a broad range of long wavelength light signals to efficiently convert infrared light into electrical signals. It is capable of converting long wavelength light signals into electrical signals with direct normal incidence sensitivity without the assistance of light coupling devices or schemes. In the apparatus, stored charged carriers are ejected by photons from quantum dots, then flow over the other barrier and quantum dot layers with the help of an electric field produced with a voltage applied to the device, producing a detectable photovoltage and photocurrent. The photodetector has multiple layers of materials including at least one quantum dot layer between an emitter layer and a collector layer, with a barrier layer between the quantum dot layer and the emitter layer, and another barrier layer between the quantum dot layer and the collector.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: May 29, 2001
    Assignee: National Research Council of Canada
    Inventors: Simon Fafard, Hui Chun Liu
  • Patent number: 6229151
    Abstract: An optical semiconductor device having a plurality of GaN-based semiconductor layers containing a strained quantum well layer in which the strained quantum well layer has a piezoelectric field that depends on the orientation of the strained quantum well layer when the quantum layer is grown. In the present invention, the strained quantum well layer is grown with an orientation at which the piezoelectric field is less than the maximum value of the piezoelectric field strength as a function of the orientation. In devices having GaN-based semiconductor layers with a wurtzite crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {0001} direction of the wurtzite crystal structure. In devices having GaN-based semiconductor layers with a zincblende crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {111} direction of the zincblende crystal structure.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: May 8, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Tetsuya Takeuchi, Norihide Yamada, Hiroshi Amano, Isamu Akasaki
  • Patent number: 6229150
    Abstract: A group III-nitride quatenary material system and method is disclosed for use in semiconductor structures, including laser diodes, transistors, and photodetectors, which reduces or eliminates phase separation and provides increased emission efficiency and reliability. In an exemplary embodiment the semiconductor structure includes first GaAINAs layer of a first conduction type formed substantially without phase separation, an GaAINAs active layer substantially without phase separation, and a third GaAINAs layer of an opposite conduction type formed substantially without phase separation.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 8, 2001
    Assignee: Matsushita Electronics Corp.
    Inventors: Toru Takayama, Takaaki Baba, James S. Harris, Jr.
  • Patent number: 6225647
    Abstract: A method for substantially improving the photoluminescent performance of a porous semiconductor, involving the steps of providing a bulk semiconductor substrate wafer of a given conductivity, wherein the substrate wafer has a porous semiconductor layer of the same conductivity as the bulk semiconductor substrate wafer, and the porous semiconductor layer is made up of a plurality of pores interspersed within a plurality of nanocrystallites, wherein each of the pores is defined by a pore wall and each of the nanocrystallites has a given thickness. Next, in the method, at least one monolayer layer of passivating material is generated on the pore wall of each of the pores, to passivate the porous semiconductor layer. The one layer of passivating material substantially eliminates dangling bonds and surface states which are associated with the porous semiconductor layer. The resulting passivated porous semiconductor layer exhibits a quantum efficiency of approximately 5 percent.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: May 1, 2001
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Jonathan E. Spanier
  • Patent number: 6222200
    Abstract: A photodetector has an extended wavelength range combined with high responsivity and reliability. It includes an active region having alternating compressive and tensile strain layers arranged so that the total effective strain of the active region is balanced. The thickness of each layer is limited so that a product of a thickness by strain is not exceeding about 20% nm to avoid formation of crystalline defects. The layers with higher optical absorption constant are made thicker than the layers with lower absorption constant to provide the required responsivity of the detector. In one embodiment, the active region is formed on InP substrate and includes alternating 0.25% compressive strain and 1.03% tensile strain layers of InGaAs composition, the compressive strain layers being approximately four times thicker. In another embodiment interfaces between the layers are compositionally graded. The described structure of the active region may be used in various types of photodetectors, e.g.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: April 24, 2001
    Assignee: Nortel Networks Limited
    Inventor: Mikelis Nils Svilans
  • Patent number: 6218677
    Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: April 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Tom P. E. Broekaert
  • Patent number: 6211529
    Abstract: An AlxGa1−xAs/GaAs/AlxGa1−xAs quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the “top” (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: April 3, 2001
    Assignee: California Institute of Technology
    Inventors: Sarath Gunapala, John K. Liu, Jin S. Park, True-Lon Lin, Mani Sundaram
  • Patent number: 6207973
    Abstract: A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: March 27, 2001
    Assignee: Ricoh Company, Ltd.
    Inventors: Shunichi Sato, Takashi Takahashi, Naoto Jikutani
  • Patent number: 6177686
    Abstract: A photodiode for an input light signal comprising an absorption layer having an absorption coefficient which is less than the absorption coefficient of InGaAs when measured at a wavelength of 1.55 &mgr;m. First and a second cladding layer are disposed on opposite sides of the absorption layer leaving exposed a side of the absorption layer. Positively and negatively polarized contact layers are disposed on the first and second cladding layers respectively. The input light signal is directed into the exposed side of the absorption layer and the absorption layer absorbs the input light signal and photo-generates therefrom carriers. The contact layers collect the carriers and generate therefrom photocurrent.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: January 23, 2001
    Assignee: TRW Inc.
    Inventor: Augusto L. Gutierrez-Aitken
  • Patent number: 6157043
    Abstract: A compound nanotube (17) is made of carbon nitride (CN). Another compound nanotube (19) is made of boron carbide (BC.sub.3) with alkali metal doped. Each of the nanotubes has a distorted configuration of atoms in a predetermined direction with a lower symmetry than that of an undistorted configuration. A solenoid element comprises the compound nanotube. A magnetic generating apparatus comprises a compound nanotube, means for applying a tensile to the compound nanotube in a longitudinal direction of said compound nanotube, and means for flowing current at both ends of the compound nanotube. Each of the nanotubes is applied with mechanical stress to controllably vary a current flow direction. Specifically, tensile stress is applied in a longitudinal direction (21) of the nanotube so that an electric current spirally flows around a surface of the nanotube along a spiral path having a diameter of several nanometers, as shown in arrows (23).
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: December 5, 2000
    Assignee: NEC Corporation
    Inventor: Yoshiyuki Miyamoto
  • Patent number: 6150672
    Abstract: A Group III-nitride semiconductor device that has a low voltage-drop p-contact and comprises a substrate layer, a metal electrode and an intermediate layer sandwiched between the substrate layer and the metal electrode. The substrate layer is a layer of a p-type Group III-nitride semiconductor, and the intermediate layer includes a Group III-nitride semiconductor in which atoms of a Group V element other than nitrogen have been substituted for a fraction of nitrogen atoms. The Group III-nitride semiconductor device is made by providing a substrate including a p-type Group III-nitride semiconductor having an exposed surface. Atoms of a Group V element other than nitrogen are substituted for a fraction of the nitrogen atoms of the p-type Group III-nitride semiconductor to form an intermediate layer extending into the p-type Group III-nitride semiconductor from the exposed surface. Metal is then deposited on the exposed surface to form an electrode in electrical contact with the intermediate layer.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: November 21, 2000
    Assignee: Agilent Technologies
    Inventor: Yawara Kaneko
  • Patent number: 6150604
    Abstract: A thermophotovoltaic cell is provided containing strained or lattice-matched quantum wells that have a bandgap smaller than the bandgap of the InGaAs alloy. The alloy is lattice-matched to the substrate. These narrow bandgap quantum wells provide more efficient conversion of IR emission from a black body or other emitter by converting energy from a wider range of wavelengths than a conventional single junction cell. The thickness of the quantum well region and the individual thickness of the individual quantum wells are chosen to avoid lattice mismatch defects which cause degradation of thick conventional lattice mismatched devices.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: November 21, 2000
    Assignee: University of Houston
    Inventors: Alex Freundlich, Alex Ignatiev
  • Patent number: 6147296
    Abstract: A two-terminal tandem solar cell is provided. The inclusion of thin (few nm-thick) narrow band-gap InGaAs quantum wells in the intrinsic (i) region of the conventional p-i-n GaAs solar cell extends the photo-absorption of the conventional GaInP/GaAs tandem cell toward the infrared. Beginning-of-Life efficiencies in excess of 30% are predicted. Modeling data indicate end-of-life efficiency of these cells will exceed 25% AM0.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: November 14, 2000
    Assignee: University of Houston
    Inventor: Alexandre Freundlich
  • Patent number: 6148015
    Abstract: A common InP semiconductor substrate device includes a laser emitter H1 for emitting waves having a first wavelength such as 1,300 nm, a photodiode H2 for receiving and detecting waves having a second wavelength such as 1,550 nm, and a separator G absorbing the waves having the first wavelength, the separator being interposed between the laser emitter H1 and the photodiode G for protecting the photodiode against the waves having the first wavelength. An absorption measurement mechanism Q delivers a signal iG representative of the power of the waves absorbed by the separator G, to make it possible to regulate operation of the laser emitter H1. The semiconductor substrate device is particularly applicable to implementing end devices to be installed on subscriber premises for subscribers to optical fiber interactive local area networks.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: November 14, 2000
    Assignee: Alcatel
    Inventors: Joel Jacquet, Salim Gurib, Francis Doukhan, Hugues Le Quellec
  • Patent number: 6140148
    Abstract: The invention provides a method of making an ohmic contact to a n-type diamond or an injecting contact to a p-type diamond. The method includes the steps of implanting a surface of the diamond with a n-type dopant atom at a dose just below the amorphisation threshold of the diamond to create an implanted region below the surface and extending from the surface, annealing the implanted region to allow tunnelling of electrons into the diamond in the case of a n-type diamond and allow electrons to be injected into the diamond in the case of a p-type diamond, and metallising at least a portion of the surface through which implantation occurred.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: October 31, 2000
    Inventor: Johan Frans Prins
  • Patent number: 6130441
    Abstract: By using wafer fusion, various structures for photodetectors and photodetectors integrated with other electronics can be achieved. The use of silicon as a multiplication region and III-V compounds as an absorption region create photodetectors that are highly efficient and tailored to specific applications. Devices responsive to different regions of the optical spectrum, or that have higher efficiencies are created.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: October 10, 2000
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, Aaron R. Hawkins
  • Patent number: 6127691
    Abstract: A semiconductor laser device comprises a GaAs substrate, a first cladding layer having either one of p-type electrical conductivity and n-type electrical conductivity, a first optical waveguide layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 first barrier layer, an In.sub.x3 Ga.sub.1-x3 As.sub.1-y3 P.sub.y3 quantum well active layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 second barrier layer, a second optical waveguide layer, and a second cladding layer having the other electrical conductivity, the layers being overlaid in this order on the substrate. Each cladding layer and each optical waveguide layer have compositions, which are lattice matched with the substrate. Each of the first and second barrier layers has a tensile strain with respect to the substrate and is set such that a total layer thickness of the barrier layers may be 10 nm to 30 nm, and a product of a strain quantity of the tensile strain and the total layer thickness may be 0.05 nm to 0.2 nm.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: October 3, 2000
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Toshiaki Fukunaga, Mitsugu Wada
  • Patent number: 6118136
    Abstract: The invention is to develop a high-speed low power consumption resonant tunneling element--a superlatticed negative-differential-resistance (NDR) functional transistor. The proposed element exhibits amplification and obvious NDR phenomena simultaneously. In this element, the emitter region includes 5-period GaInAs/AlInAs super lattice resonant tunneling and emitter layers. Since the emitter--base interface is of homojunction, the collector--emitter offset voltage (V.sub.CE, offset) may be lowered down significantly. In addition, the produced infinitesimal potential (.DELTA.Ev) at GaInAs/AlInAs interface due to heterojunction in discrete valence bands may be applied as barriers to prohibit holes flow from base towards emitter. By doing so, the base current is remarkably depressed so as to elevate efficiency of emitter injection as well as current gain.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: September 12, 2000
    Assignee: National Science Council of Republic of China
    Inventors: Wen-Chau Liu, Shiou-Ying Cheng
  • Patent number: 6111266
    Abstract: A semiconductor substrate, suitable for epitaxial growth thereon, comprising a plurality of layers of material. The interfaces between layers act as reflectors of electromagnetic radiation. The reflectors may be used in, for example, resonant cavities in which may be located, for example, multi-quantum well detectors, the efficiency of said detectors being increased by virtue of the enhanced electric field associated with resonance in the cavity.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: August 29, 2000
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Roger T Carline, David J Robbins
  • Patent number: 6104039
    Abstract: A plurality of first layers made of AlGaN mixed crystal each having a thickness of the order of 1 to 100 nm and a plurality of second layers of p-type GaN with Mg each having a thickness of the order of 1 to 100 nm are alternately stacked. Since each of the first and second layers is thin, the stacked layers as a whole have properties of p-type AlGaN mixed crystal although the first layers do not include Mg and the second layers do not include Al. An Al source and a Mg source are temporally separated to be introduced in a stacking process. A reaction between the Al source and Mg source which may interfere desirable crystal growth is thereby prevented. Crystals of good quality are thus grown and electrical conductivity is thereby improved.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: August 15, 2000
    Assignee: Sony Corporation
    Inventors: Tsunenori Asatsuma, Katsunori Yanashima, Takao Miyajima
  • Patent number: 6104049
    Abstract: A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300.degree. C. for five minutes, then RTP annealed at 675.degree. C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700.degree. C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 90 nm. A second electrode is applied to form a capacitor, and a post-anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0.ltoreq.v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: August 15, 2000
    Assignee: Symetrix Corporation
    Inventors: Narayan Solayappan, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan, Shinichiro Hayashi, Tatsuo Otsuki
  • Patent number: 6100543
    Abstract: Disclosed is an electro-absorption type semiconductor optical modulator utilizing the Quantum Confinement Stark Effect, in which a quantum well structure introduced in its optical absorption layer is arranged to have a potential structure such that one of the electron affinity and the energy of the top of the valence band increases in the laminating direction, while the other decreases, thereby canceling the built-in field. It is intended to lower the drive voltage and to enhance an on/off ratio (extinction ratio). Thus, the absorption peak becomes narrow at a no bias state to attain a low drive voltage and an enhanced extinction ratio.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Yasutaka Sakata
  • Patent number: 6075253
    Abstract: A semiconductor photodetector having a planar structure, including a first silicon layer having a first conductivity and formed with a recess, a silicon dioxide film covering a sidewall of the recess therewith, a germanium monocrystal layer formed in the recess, a first germanium layer having a first conductivity and sandwiched between the germanium monocrystal layer and the first silicon layer in the recess, a second germanium layer having a second conductivity and formed on the germanium monocrystal layer, and a second silicon layer having a second conductivity and formed on the second germanium layer. The first and second germanium layers prevent a depletion layer, which are generated in the germanium monocrystal layer when a voltage is applied to the semiconductor photodetector, from reaching the first and second silicon layers, respectively.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventors: Mitsuhiro Sugiyama, Toru Tatsumi
  • Patent number: 6069367
    Abstract: The purpose of the present invention is to provide a semiconductor light-emitting element that can reduce an operational voltage by improving a contact construction with a p-side electrode. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a ZnSSe cap layer, a ZnSe cap layer, a compositional gradient super-lattice layer, and a low defect contact layer are sequentially laminated on an n-type substrate. The compositional gradient super-lattice layer is formed by alternately laminating p-type ZnTe layers and p-type ZnSe layers. The p-type ZnTe layers are formed to be thickened toward the side of the low defect contact layer. The thickness of the low defect contact layer must be 5 nm or less. Relaxing lattice distortion reduces defect density of the low defect contact layer. Accordingly, the increase in the operational voltage immediately after energization is suppressed, and the operational voltage becomes lower.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Shigetaka Tomiya, Satoru Kijima, Hiroyuki Okuyama, Satoshi Taniguchi, Hironori Tsukamoto
  • Patent number: 6066859
    Abstract: An opto-electronic component with two MQW structures having different functions, wherein the layer sequences that form these MQW structures are grown in a single epitaxy process of uniform layers in every layer plane. In an embodiment, a laser diode-modulator combination is provided wherein the MQW layer sequence of the laser is preferably arranged within the MQW layer sequence of the modulator.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: May 23, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Bernhard Stegmueller
  • Patent number: 6064076
    Abstract: A light-emitting diode having a transparent substrate contains a transparent GaP substrate having a first lattice constant, a first ohmic contact to the GaP substrate, a buffer layer having a graded lattice constant which gradually changes from a first lattice constant to a second lattice constant, a light generating region formed on the buffer layer and having the second lattice constant, and a second ohmic contact formed on the light generating region. In the present invention, light emitted to the substrate is not absorbed by the transparent substrate. Therefore, the brightness of the LED is increased and the V.sub.f value is not increased.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: May 16, 2000
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Lung-Chien Chen, Kun-Chuan Lin
  • Patent number: 6057563
    Abstract: Disclosed is a light transparent window layer for light transmitting diodes. The light transparent window layer is formed by growing a plurality of AlGaInP superlattice layers such that the uniformity of current distribution within LED chip can be enhanced, and the size of light-emitting area can be increased. The manufacturing process is also simplified.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: May 2, 2000
    Assignee: Lite-on Electonics, Inc.
    Inventors: Hsi-Ming Chen, Szutsun S. Ou
  • Patent number: RE36747
    Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density .[.i.sub.H -layer.]. .Iadd.H-layer.Iaddend.. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: June 27, 2000
    Assignees: Toyoda Gosei Co., Ltd, Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Katsuhide Manabe, Masahiro Kotaki, Makoto Tamaki, Masafumi Hashimoto