Field Effect Device Patents (Class 257/24)
  • Publication number: 20100127241
    Abstract: An electronic device has a source electrode, a drain electrode spaced apart from said source electrode, and at least one of a conducting material, dielectric material and a semiconductor material disposed between said source electrode and said drain electrode. At least one of the source electrode, the drain electrode and the semiconductor material includes at least one nanowire.
    Type: Application
    Filed: February 27, 2006
    Publication date: May 27, 2010
    Applicant: The Regents of the University of California
    Inventors: George Gruner, Erika K. Artukovic, David S. Hecht
  • Patent number: 7718498
    Abstract: A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source/drain regions having a first conductivity type impurity concentration lower than that in the first source/drain regions and formed adjoining the gate insulation film and the first source/drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 18, 2010
    Assignee: Sony Corporation
    Inventor: Kazuichiro Itonaga
  • Patent number: 7718995
    Abstract: A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the surface of the nanowire body. The surface of the nanowire body is smooth.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Kenji Harada
  • Publication number: 20100117062
    Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 13, 2010
    Inventors: Mantu Hudait, Robert S. Chau, Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey
  • Publication number: 20100108988
    Abstract: Nanotube-based structure and method of forming the same are disclosed. A structure having two tips is provided for defining a location for forming a nanotube connection. The nanotube connection, which can be coated with an electrically conductive polymer for enhanced conductivity, can be used in forming nanotube-based devices for various applications.
    Type: Application
    Filed: August 29, 2008
    Publication date: May 6, 2010
    Applicant: New Jersey Institute of Technology
    Inventors: Haim Grebel, David Katz, Seon Woo Lee
  • Publication number: 20100109645
    Abstract: Embodiments feature a sensor including a nanostructure and methods for manufacturing the same. In some embodiments, a sensor includes a substrate, a first electrode disposed on the substrate, and a second electrode disposed on the substrate. The second electrode is spaced apart from the first electrode and surrounding the first electrode. The sensor includes at least one nanostructure contacting the first electrode and the second electrode, in which the nanostructure is configured to vary an electrical characteristic according to an object to be sensed.
    Type: Application
    Filed: August 6, 2007
    Publication date: May 6, 2010
    Applicant: Seoul National University Industry Foundation
    Inventors: Young June Park, Jun Ho Cheon, Sung Min Seo
  • Patent number: 7709828
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 4, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew Currie
  • Patent number: 7709827
    Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 4, 2010
    Assignee: Qimonda, AG
    Inventors: Andrew Graham, Franz Hofmann, Wolfgang Hönlein, Johannes Kretz, Franz Kreupl, Erhard Landgraf, Johannes Richard Luyken, Wolfgang Rösner, Thomas Schulz, Michael Specht
  • Publication number: 20100096704
    Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.
    Type: Application
    Filed: December 17, 2008
    Publication date: April 22, 2010
    Inventors: Horng-Chin Lin, Chun-Jung Su, Hsing-Hui Hsu, Guan-Jang Li
  • Publication number: 20100090198
    Abstract: A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 15, 2010
    Inventors: Qiliang Li, Dimitris E. Ioannou, Yang Yang, Xiaoxiao Zhu
  • Publication number: 20100093140
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: August 17, 2009
    Publication date: April 15, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Publication number: 20100090759
    Abstract: A quantum interference transistor may include a source; a drain; N channels (N?2), between the source and the drain, and having N?1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.
    Type: Application
    Filed: September 23, 2009
    Publication date: April 15, 2010
    Inventors: Jai-kwang Shin, Sun-ae Seo, Jong-seob Kim, Ki-ha Hong, Hyun-jong Chung
  • Patent number: 7696512
    Abstract: The electron device of the present invention has a carbon-based linear structural body including at least one conductive particle, a first electrode and a second electrode disposed at both end of the carbon-based linear structural body, so as to subject the carbon-based linear structural body including at least one conductive particle to connect between the first electrode and the second electrode. A process of manufacturing the electron device includes steps of: forming a carbon-based linear structural body including at least one conductive particle, using a catalyst of a first island and a second island selected from two or more of islands of the catalyst on a substrate; and forming a first electrode and a second electrode so as to connect the first electrode with the first island and one end of the carbon-based linear structural body, and the second electrode with the second island and the other end of the carbon-based linear structural body.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: April 13, 2010
    Assignees: Fujitsu Limited, National Institute of Advanced Industrial Science and Technology
    Inventors: Yuji Awano, Kazuhiko Matsumoto
  • Publication number: 20100084632
    Abstract: A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering).
    Type: Application
    Filed: October 6, 2008
    Publication date: April 8, 2010
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: Bart Soree, Wim Magnus
  • Publication number: 20100084633
    Abstract: A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.
    Type: Application
    Filed: December 23, 2008
    Publication date: April 8, 2010
    Inventors: Hyung Jun Kim, Hyun Cheol Koo, Joon Yeon Chang, Suk Hee Han, Kyung Ho Kim
  • Publication number: 20100087013
    Abstract: The present invention generally relates to nanotechnology and sub-microelectronic circuitry, as well as associated methods and devices, for example, nanoscale wire devices and methods for use in determining nucleic acids or other analytes suspected to be present in a sample (for example, their presence and/or dynamical information), e.g., at the single molecule level. For example, a nanoscale wire device can be used in some cases to detect single base mismatches within a nucleic acid (e.g., by determining association and/or dissociation rates). In one aspect, dynamical information such as a binding constant, an association rate, and/or a dissociation rate, can be determined between a nucleic acid or other analyte, and a binding partner immobilized relative to a nanoscale wire. In some cases, the nanoscale wire includes a first portion comprising a metal-semiconductor compound, and a second portion that does not include a metal-semiconductor compound.
    Type: Application
    Filed: June 11, 2007
    Publication date: April 8, 2010
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Ying Fang, Fernando Patolsky
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Publication number: 20100072459
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Application
    Filed: August 6, 2009
    Publication date: March 25, 2010
    Applicant: NANTERO, INC.
    Inventors: Claude L. BERTIN, Thomas RUECKES, H. M. MANNING
  • Publication number: 20100072458
    Abstract: The present teachings provide methods for sorting nanotubes according to their wall number, and optionally further in terms of their diameter, electronic type, and/or chirality. Also provided are highly enriched nanotube populations provided thereby and articles of manufacture including such populations.
    Type: Application
    Filed: August 5, 2009
    Publication date: March 25, 2010
    Inventors: Alexander A. Green, Mark C. Hersam
  • Publication number: 20100072460
    Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.
    Type: Application
    Filed: September 22, 2009
    Publication date: March 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mikael T. Bjoerk, Joachim Knoch, Heike E. Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 7683400
    Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: March 23, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, Brian P. Wagner, David J. Knuteson, Michael E. Aumer, Andre Berghmans, Darren Thomson, David Kahler
  • Patent number: 7683364
    Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee
  • Publication number: 20100065820
    Abstract: A carbon nanotube of a nanotube device has at least two segments with different characteristics. The segments meet at a junction and a diameter of the carbon nanotube on either side of the junction is about the same. One segment may be doped differently from another segment. One segment may be p doped and another segment n doped. One segment may be doped with a different carrier concentration from another segment. The nanotube device may be used in power semiconductor devices including power diodes and power transistors. These power devices will be very power efficient, wasting significantly less energy than similar manufactured using silicon technology.
    Type: Application
    Filed: February 13, 2006
    Publication date: March 18, 2010
    Applicant: ATOMATE CORPORATION
    Inventor: Thomas W. Tombler, JR.
  • Publication number: 20100065899
    Abstract: A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Application
    Filed: August 20, 2009
    Publication date: March 18, 2010
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Publication number: 20100065823
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: August 17, 2009
    Publication date: March 18, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Publication number: 20100065824
    Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 18, 2010
    Applicant: IMEC
    Inventors: Wei-E Wang, Han Chung Lin, Marc Meuris
  • Publication number: 20100065822
    Abstract: A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or nanowire operatively connected to the gate electrode, the source electrode, and the drain electrode; a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer.
    Type: Application
    Filed: February 10, 2009
    Publication date: March 18, 2010
    Inventors: Aleksandr Noy, Olgica Bakajin, Sonia Letant, Michael Stadermann, Alexander B. Artyukhin
  • Publication number: 20100065821
    Abstract: A molecular quantum interference device is provided. A method for the design of such devices is also provided, the method including modelling of device performance.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Inventors: John Boland, Stefano Sanvito, Zekan Qian, Rui Li, Shimin Hou
  • Patent number: 7679079
    Abstract: Organic thin film transistor and related composite and device structures comprising an organic dielectric medium comprising, for instance, a non-linear optical chromophoric moiety.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: March 16, 2010
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Myung-Han Yoon
  • Publication number: 20100052654
    Abstract: The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer.
    Type: Application
    Filed: June 15, 2009
    Publication date: March 4, 2010
    Inventors: Kung-Hwa WEI, Jeng-Tzong SHEU, Chen-Chia CHEN, Mao-Yuan CHIU
  • Publication number: 20100045365
    Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
    Type: Application
    Filed: August 20, 2009
    Publication date: February 25, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata CHATTERJEE, Henry Litzmann EDWARDS, Chris BOWEN
  • Publication number: 20100044678
    Abstract: A method of placing a functionalized semiconducting nanostructure, includes functionalizing a semiconducting nanostructure including one of a nanowire and a nanocrystal, with an organic functionality including a functional group for bonding to a bonding surface, dispersing the functionalized semiconducting nanostructure in a solvent to form a dispersion, and depositing the dispersion onto the bonding surface.
    Type: Application
    Filed: August 21, 2008
    Publication date: February 25, 2010
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Supratik Guha, Cherie R. Kagan, George S. Tulevski, Emanuel Tutuc
  • Publication number: 20100044679
    Abstract: The present invention relates to a method of manufacturing a carbon nanotube transistor in which a carbon nanotube channel is formed between a source electrode and a drain electrode and a gate electrode is formed at one side of the carbon nanotube channel, the method comprising the steps of: (a) forming the carbon nanotube channel on a substrate; (b) electrically connecting the source electrode and the drain electrode to both ends of the carbon nanotube channel, respectively; and (c) applying a stress voltage across the source electrode and the drain electrode to remove metallicity of the carbon nanotube channel. According to the method of manufacturing a carbon nanotube transistor of the present invention, a metallic part can be selectively removed from a carbon nanotube which is used as a channel of a transistor and has metallic properties and semiconductor properties mixed with each other.
    Type: Application
    Filed: December 11, 2008
    Publication date: February 25, 2010
    Applicant: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Gyoung-Ho Buh, Jeong-O Lee, Hyunju Chang, Ki-jeong Kong, Hye-Mi So, Jae ho Hwang
  • Publication number: 20100038628
    Abstract: A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant.
    Type: Application
    Filed: August 31, 2009
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Jia Chen, Christian Klinke, Christopher B. Murray, Dmitri V. Talapin
  • Publication number: 20100038627
    Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Inventors: Ashesh Parikh, Andrew Marshall
  • Publication number: 20100035375
    Abstract: The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.
    Type: Application
    Filed: June 29, 2006
    Publication date: February 11, 2010
    Applicants: The Regents of the University of California
    Inventors: Constantine P. Grigoropoulos, Seung-Hwan Ko, Jaewon Chung, Dimos Poulikakos, Heng Pan
  • Publication number: 20100032653
    Abstract: This invention provides a process for producing a carbon nanotube electric field effect transistor that can improve yield in channel preparation. Carbon nanotubes dispersed in a mixed acid composed of sulfuric acid and nitric acid are subjected to radical treatment with aqueous hydrogen peroxide to cut the carbon nanotubes and thus to provide carboxyl-introduced carbon nanotube fragments. The carbon nanotube fragments are attached, through a covalent bond and/or an electrostatic bond, to a site, where a source electrode is to be formed, and a site where a drain electrode is to be formed, in a substrate with a functional group, to be attached to a carboxyl group, introduced thereinto. The carbon nanotube fragments attached to the substrate are attached to carbon nanotubes as channels through n-n interaction to fix the carbon nanotubes as channels to the substrate.
    Type: Application
    Filed: March 28, 2007
    Publication date: February 11, 2010
    Applicant: National University Corpration Hokkaido University
    Inventors: Seiji Takeda, Koichi Mukasa, Atsushi Ishii, Hiroichi Ozaki, Makoto Sawamura, Hirotaka Hosoi, Satoshi Hattori, Yoshiki Yamada, Kazuhisa Sueoka
  • Patent number: 7659537
    Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: February 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
  • Patent number: 7659538
    Abstract: Quantum dots are positioned within a layered composite film to produce one-dimensional and multi-dimensional shift registers within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge carriers form artificial atoms, which serve as dopants for the surrounding materials. The atomic number of each artificial atom is adjusted through precise variations in the voltage across the quantum dot that confines it. The position of the artificial atom in the film is moved by varying the location of confinement and thus operates as a shift register.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: February 9, 2010
    Assignee: RavenBrick, LLC
    Inventors: Gary E. Snyder, Wil McCarthy
  • Publication number: 20100025658
    Abstract: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 4, 2010
    Inventor: Alan Colli
  • Publication number: 20100025660
    Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: UNIVERSITY OF CONNECTICUT
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos
  • Publication number: 20100025659
    Abstract: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, a field effect device includes a gate having a corresponding gate terminal; a source having a corresponding source terminal; a drain having a corresponding drain terminal; a control terminal; and a nanotube switching element positioned between one of the gate, source, and drain and its corresponding terminal and switchable, in response to electrical stimuli at the control terminal and at least one of the gate, source, and drain terminals, between a first non-volatile state that enables current flow between the source and the drain and a second non-volatile state that disables current flow between the source and the drain.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 4, 2010
    Applicant: Nantero, Inc.
    Inventors: CLAUDE L. BERTIN, THOMAS RUECKES, BRENT M. SEGAL, BERNHARD VOGELI, DARREN K. BROCK, VENKATACHALAM C. JAIPRAKASH
  • Publication number: 20100019227
    Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 28, 2010
    Applicant: Texas Instruments Incorporated
    Inventor: Christoph Wasshuber
  • Publication number: 20100019226
    Abstract: The invention relates to a semiconductor sensor device (10) for sensing a substance comprising at least one nanowire (11) which is formed on a surface of a semiconductor body (12) and which is connected at a first end to a first electrically conducting connection region (13) and at a second end to’ a second electrically conducting connection region (14) while a fluid (20) comprising a substance (30) to be sensed can flow along the nanowire (11) and the substance (30) to be sensed can influence’ the electrical properties of the nanowire (11), wherein the nanowire (11) comprises viewed in a longitudinal direction subsequently a first semiconductor subregion (1) comprising a first semiconductor material and a second semiconductor subregion (2) comprising a second semiconductor material different from the first semiconductor material. According to the invention’ the first semiconductor material comprises a IV element material and the second semiconductor material comprises a III-V compound.
    Type: Application
    Filed: September 17, 2007
    Publication date: January 28, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Meriman Nicoletta Kahya, Erik Petrus Antonius Maria Bakkers
  • Publication number: 20100012925
    Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 21, 2010
    Applicant: NANTERO, INC.
    Inventors: Claude L. BERTIN, Mitchell MEINHOLD, Steven L. KONSEK, Thomas RUECKES, Frank GUO
  • Publication number: 20100012924
    Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 21, 2010
    Inventor: Nobuaki Teraguchi
  • Publication number: 20100012923
    Abstract: It is to provide a thermodynamically and chemically stable dopant material which can achieve controls of the pn conduction types, carrier density, and threshold value of gate voltage, and a manufacturing method thereof. Further, it is to provide an actually operable semiconductor device such as a transistor with an excellent high-speed operability and high-integration characteristic. Provided is a dopant material obtained by depositing, on a carbon nanotube, a donor with a smaller ionization potential than an intrinsic work function of the carbon nanotube or an acceptor with a larger electron affinity than the intrinsic work function of the carbon nanotube. The ionization potential of the donor in vacuum is desired to be 6.4 eV or less, and the electron affinity of the acceptor in vacuum to be 2.3 eV or more.
    Type: Application
    Filed: January 5, 2006
    Publication date: January 21, 2010
    Inventors: Hidefumi Hiura, Tetsuya Tada, Toshihiko Kanayama
  • Publication number: 20100006824
    Abstract: An organic nanofiber including a gelled organic semiconductor compound. Also disclosed is an organic semiconductor transistor and a method of manufacturing an organic semiconductor transistor.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 14, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-in HONG, Myoung-chul UM, Jung-pyo HONG, Seong-hoon LEE
  • Publication number: 20100006823
    Abstract: The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20100001260
    Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
    Type: Application
    Filed: August 20, 2009
    Publication date: January 7, 2010
    Inventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong