Field Effect Device Patents (Class 257/24)
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Publication number: 20110147715Abstract: The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.Type: ApplicationFiled: June 16, 2009Publication date: June 23, 2011Applicant: PURDUE RESEARCH FOUNDATIONInventors: John A. Rogers, Qing Cao, Muhammad Alam, Ninad Pimparkar
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Publication number: 20110147709Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: An Chen, Zoran Krivokapic
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Publication number: 20110147711Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
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Publication number: 20110147697Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Uday Shah, Benjamin Chu-Kung, Been-Yih Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
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Publication number: 20110147712Abstract: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: MARKO RADOSAVLJEVIC, GILBERT DEWEY, NILOY MUKHERJEE, RAVI PILLARISETTY
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Publication number: 20110147710Abstract: Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau
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Patent number: 7964489Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.Type: GrantFiled: June 25, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
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Publication number: 20110140086Abstract: The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centres (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centres (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centres (10) alters the conductivity of the nanowire (3).Type: ApplicationFiled: July 2, 2009Publication date: June 16, 2011Applicant: QuNano ABInventors: Lars Samuelson, Claes Thelander, Jonas Ohlsson, Anders Mikkelsen
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Publication number: 20110140087Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.Type: ApplicationFiled: February 24, 2011Publication date: June 16, 2011Applicants: IMEC, Katholieke Universiteit LeuvenInventors: Geert Hellings, Geert Eneman, Marc Meuris
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Publication number: 20110140085Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.Type: ApplicationFiled: November 18, 2010Publication date: June 16, 2011Inventors: Andrew P. Homyk, Michael D. Henry, Axel Scherer, Sameer Walavalkar
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Publication number: 20110133163Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy M. Cohen, Conal E. Murray, Jeffrey W. Sleight
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Publication number: 20110133164Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Josephine B. Chang, Guy M. Cohen, Jeffrey W. Sleight
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Publication number: 20110133165Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
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Publication number: 20110133168Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.Type: ApplicationFiled: December 7, 2009Publication date: June 9, 2011Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
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Publication number: 20110133167Abstract: A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
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Publication number: 20110133162Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Josephine B. Chang, Guy M. Cohen, Jeffrey W. Sleight
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Publication number: 20110133166Abstract: A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Guy M. Cohen, Conal E. Murray, Jeffrey W. Sleight
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Publication number: 20110133161Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 7955881Abstract: In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer.Type: GrantFiled: July 9, 2009Date of Patent: June 7, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Takamichi Sumitomo, Yohei Enya, Takashi Kyono, Masaki Ueno
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Patent number: 7955932Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.Type: GrantFiled: October 3, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
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Publication number: 20110127492Abstract: A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Eric A. Joseph
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Publication number: 20110127493Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Josephine B. Chang, Alfred Grill, Michael A. Guillorn, Christian Lavoie, Eugene J. O'Sullivan
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Patent number: 7952088Abstract: The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.Type: GrantFiled: July 11, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Publication number: 20110121266Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Inventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Patent number: 7947971Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: GrantFiled: April 8, 2010Date of Patent: May 24, 2011Assignee: Intel CorporationInventors: Prashant Majhi, Mantu Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Publication number: 20110114918Abstract: A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yu-Ming Lin, Jeng-Bang Yau
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Publication number: 20110108803Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.Type: ApplicationFiled: January 5, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
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Publication number: 20110108802Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yu-Ming Lin, Jeng-Bang Yau
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Publication number: 20110108804Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Jeffrey W. Sleight
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Publication number: 20110101302Abstract: Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes.Type: ApplicationFiled: November 5, 2010Publication date: May 5, 2011Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Chongwu Zhou, Chuan Wang, Jialu Zhang, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco
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Publication number: 20110095267Abstract: Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: International Business Machines CorporationInventors: Andres Bryant, Oki Gunawan, Shih-Hsien Lo, Jeffrey W. Sleight
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Patent number: 7928426Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2007Date of Patent: April 19, 2011Assignee: Intel CorporationInventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
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Patent number: 7928427Abstract: The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.Type: GrantFiled: April 7, 2010Date of Patent: April 19, 2011Assignee: National Chiao Tung UniversityInventor: Chun-Yen Chang
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Patent number: 7923753Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.Type: GrantFiled: August 17, 2006Date of Patent: April 12, 2011Assignee: Oki Electric Industry Co., Ltd.Inventors: Juro Mita, Katsuaki Kaifu
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Publication number: 20110079770Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.Type: ApplicationFiled: September 14, 2010Publication date: April 7, 2011Applicant: William Marsh Rice UniversityInventors: Gyou-Jin Cho, Min Hun Jung, Jared L. Hudson, James M. Tour
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Publication number: 20110079769Abstract: A MOS transistor having a gate length shorter than twice the de Broglie wavelength of the charge carriers in the channel material, wherein the cross-sectional area of the channel region is decreased in the vicinity of the drain region along at least one dimension to a value smaller than half said wavelength.Type: ApplicationFiled: March 7, 2006Publication date: April 7, 2011Inventor: Nicolas Cavassilas
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Publication number: 20110079771Abstract: An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.Type: ApplicationFiled: September 21, 2010Publication date: April 7, 2011Applicant: FUJITSU LIMITEDInventors: Masahito KANAMURA, Toshihide Kikkawa
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Publication number: 20110073842Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.Type: ApplicationFiled: June 5, 2009Publication date: March 31, 2011Applicant: National Institue of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Publication number: 20110073841Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Inventors: ZhongLiang Huo, Subramanya Mayya, Xiaofeng Wang, In-Seok Yeo
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Publication number: 20110073840Abstract: An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry. Another embodiment is a method and apparatus of a semiconductor device with bottom gate structure and having radial contact using nanowires. A gate electrode is deposited on a substrate. A dielectric layer is deposited on the substrate and the gate electrode. A source-drain assembly is deposited on the dielectric layer. The source-drain assembly has source and drain electrodes connected via a nanowire in a rotationally invariant geometry. Another embodiment is a method and apparatus of a semiconductor device with top gate structure and having radial contact using nanowires. An isolation barrier layer is deposited on a substrate.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Michael L. Chabinyc, William S. Wong, Sourobh Raychaudhuri
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Patent number: 7915608Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.Type: GrantFiled: May 8, 2009Date of Patent: March 29, 2011Assignees: IMEC, Katholieke Universiteit LeuvenInventors: Geert Hellings, Geert Eneman, Marc Meuris
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Patent number: 7915642Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
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Patent number: 7915643Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: September 17, 2007Date of Patent: March 29, 2011Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Publication number: 20110068324Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Kazuhiko MATSUMOTO, Atsuhiko Kojima, Satoru Nagao
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Publication number: 20110068323Abstract: Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Zhihong Chen, Aaron D. Franklin, James B. Hannon, George S. Tulevski
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Patent number: 7910917Abstract: A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.Type: GrantFiled: April 10, 2006Date of Patent: March 22, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Thomas Ernst, Stephan Borel
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Publication number: 20110062418Abstract: A carbon nanotube electronic circuit utilizing a differential amplifier is implemented on a single carbon nanotube. Field effect transistors are formed from a first group of electrical conductors in contact with the carbon nanotube and a second group of electrical conductors insulated from, but exerting electric fields on, the carbon nanotube form the gates of the field effect transistors. A signal input circuit has a first input portion and a second input portion. A first field effect transistor electrically responsive to a first incoming signal is formed on the first input portion. A carbon nanotube actuator having electrical terminals and responsive to electrical conditions is an electrical load. A current source, connected to the signal input circuit, is formed on the carbon nanotube from one or more second field effect transistors.Type: ApplicationFiled: November 22, 2010Publication date: March 17, 2011Inventor: Lester F. Ludwig
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Publication number: 20110062417Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion on a channel region between the source/drain regions. Third semiconductor layers are on the first portions of the second semiconductor layer. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. Contact plugs are in the first semiconductor layers, the first portions of the second semiconductor layers and the third semiconductor layers in the source/drain regions. A diameter of the contact plug in the second semiconductor layer is smaller than a diameter of the contact plug in the first and third semiconductor layers.Type: ApplicationFiled: February 4, 2010Publication date: March 17, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masayoshi Iwayama, Takeshi Kajiyama, Yoshiaki Asao
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Publication number: 20110062419Abstract: Provided is a carbon nanotube field effect transistor manufacturing method wherein carbon nanotube field effect transistors having excellent stable electric conduction property are manufactured with excellent reproducibility. After arranging carbon nanotubes to be a channel on a substrate, the carbon nanotubes are covered with an insulating protection film. Then, a source electrode and a drain electrode are formed on the insulating protection film. At this time, a contact hole is formed on the protection film, and the carbon nanotubes are connected with the source electrode and the drain electrode. Then, a wiring protection film, a conductive film and a plasma CVD film are sequentially formed on the insulating protection film, the source electrode and the drain electrode. In the field effect transistor thus manufactured, since the carbon nanotubes to be the channel are not contaminated and not damaged, excellent stable electric conductive property is exhibited.Type: ApplicationFiled: May 22, 2009Publication date: March 17, 2011Inventors: Hiroaki Kikuchi, Osamu Takahashi, Katsunori Kondo, Tomoaki Yamabayashi, Kunio Ogasawara, Tadashi Ishigaki, Yutaka Hienuki, Motonori Nakamura, Agus Subagyo
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Patent number: 7906776Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.Type: GrantFiled: April 26, 2010Date of Patent: March 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Glyn Braithwaite, Richard Hammond, Matthew Currie