Field Effect Device Patents (Class 257/24)
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Publication number: 20100252813Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.Type: ApplicationFiled: July 17, 2007Publication date: October 7, 2010Applicant: SHARP LABORATORIES OF AMERICA, INC.Inventors: Mark A. Crowder, Yutaka Takafuji
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Publication number: 20100252800Abstract: A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti Chidambarrao, Xiao H. Liu, Lidija Sekaric
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Publication number: 20100252801Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lidija Sekaric, Dureseti Chidambarrao, Xiao H. Liu
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Publication number: 20100252812Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.Type: ApplicationFiled: December 29, 2006Publication date: October 7, 2010Inventors: Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De
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Patent number: 7807990Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.Type: GrantFiled: May 24, 2007Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
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Publication number: 20100243990Abstract: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.Type: ApplicationFiled: June 2, 2010Publication date: September 30, 2010Applicant: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Hongkun Park, Qingqiao Wei, Yi Cui, Wenjie Liang
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Publication number: 20100237324Abstract: A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.Type: ApplicationFiled: December 8, 2009Publication date: September 23, 2010Applicant: International Business Machines CorporationInventors: Zhong-Xiang He, Qizhi Liu
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Patent number: 7795622Abstract: A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and comprising GaN whose energy bandgap is smaller than the second layer, and a channel region layer formed on the third layer.Type: GrantFiled: March 31, 2008Date of Patent: September 14, 2010Assignee: Fujitsu LimitedInventors: Toshihide Kikkawa, Kenji Imanishi
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Publication number: 20100224861Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.Type: ApplicationFiled: January 4, 2010Publication date: September 9, 2010Inventors: Faquir Chand Jain, Evan Heller
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Publication number: 20100224862Abstract: When an electronic element using a carbon nanotube (CNT) is fabricated, particularly when a carbon nanotube thin film is formed on a previously formed electrode, a CNT film is manufactured on the previously formed electrode, and the CNT film on the electrode is used as an electronic element, as it is. In this case, a problem is that unless the carbon nanotubes and the electrode are in sufficient contact with each other, the contact resistance increases, and sufficient element properties are not obtained. When a carbon nanotube thin film is formed on a previously formed electrode, a conductive organic polymer thin film is formed, before or after the carbon nanotube thin film is manufactured, to decrease the contact resistance.Type: ApplicationFiled: September 2, 2008Publication date: September 9, 2010Inventors: Hiroyuki Endoh, Satoru Toguchi, Hideaki Numata
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Patent number: 7791107Abstract: A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.Type: GrantFiled: June 16, 2004Date of Patent: September 7, 2010Assignee: Massachusetts Institute of TechnologyInventors: Saurabh Gupta, Minjoo Larry Lee, Eugene A. Fitzgerald
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Patent number: 7786466Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: January 11, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20100213441Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.Type: ApplicationFiled: February 20, 2009Publication date: August 26, 2010Inventors: Ravi Pillarisetty, Titash Rakshit, Mantu Hudait, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
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Publication number: 20100214012Abstract: An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel.Type: ApplicationFiled: February 23, 2010Publication date: August 26, 2010Applicant: Cornell UniversityInventor: Hassan Raza
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Publication number: 20100207103Abstract: A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture.Type: ApplicationFiled: May 3, 2010Publication date: August 19, 2010Applicant: NEW JERSEY INSTITUTE OF TECHNOLOGYInventors: Reginald Conway Farrow, Amit Goyal
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Publication number: 20100207102Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.Type: ApplicationFiled: December 1, 2009Publication date: August 19, 2010Inventors: Eun-hong Lee, Un-jeong Kim, Woo-jong Yu, Young-hee Lee
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Publication number: 20100207101Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Board of Regents, The University of Texas SystemInventors: Leonard Franklin Register, II, Sanjay Banerjee
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Publication number: 20100200838Abstract: In a switching element using, for the active layer, a carbon nanotube (CNT) dispersed film which can be manufactured at low temperatures, the interaction between the CNT and the surface of the gate insulating film is insufficient. For this reason, a problem of such a switching element is that the amount of CNT fixed in the channel region is insufficient, resulting in insufficient uniformity. In the switching element of the exemplary embodiment, a gate insulating film is formed of a nonconjugated polymer material containing, in the main chain, an aromatic group and a substituted or unsubstituted alkylene or alkyleneoxy group having 2 or more carbon atoms as repeating units. As a result, the interaction between the CNT and the surface of the gate insulating film is enhanced while maintaining the flexibility of the gate insulating film, and the amount of CNT fixed in the channel region can be increased.Type: ApplicationFiled: February 19, 2008Publication date: August 12, 2010Applicant: NEC CORPORATIONInventors: Satoru Toguchi, Hiroyuki Endoh
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Publication number: 20100193771Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: ApplicationFiled: April 8, 2010Publication date: August 5, 2010Inventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Publication number: 20100193770Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Jeffrey W. Sleight
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Publication number: 20100198521Abstract: The present invention provides an electronic nose device based on chemically sensitive field effect transistors. In particular, the sensors of the electronic nose device are composed of non-oxidized, functionalized silicon nanowires which can detect volatile organic compounds with very high sensitivity. Methods of use in diagnosing diseases including various types of cancer are disclosed.Type: ApplicationFiled: July 24, 2008Publication date: August 5, 2010Applicant: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD.Inventor: Hossam Haick
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Publication number: 20100187503Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0<x<0.5) on the (100) plane of the Ge nano wire.Type: ApplicationFiled: January 27, 2010Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko MORIYAMA, Yoshiki Kamata, Tsutomu Tezuka
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Publication number: 20100187502Abstract: A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.Type: ApplicationFiled: May 19, 2006Publication date: July 29, 2010Inventors: Jeffrey Peter Gambino, Son Van Nguyen
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Publication number: 20100188905Abstract: According to an embodiment of the present invention, a spin device includes an intermediate semiconductor region arranged between a first terminal and a second terminal, wherein the first terminal is adapted to provide a current having a first degree of spin polarization to the intermediate semiconductor region, and wherein the second terminal is adapted to output the current having a second degree of spin polarization.Type: ApplicationFiled: January 23, 2009Publication date: July 29, 2010Inventors: Gerhard Poeppel, Hans-Joerg Timme, Werner Robl
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Publication number: 20100163849Abstract: A quantum well is formed for a deep well III-V semiconductor device using double pass patterning. In one example, the well is formed by forming a first photolithography pattern over terminals on a material stack, etching a well between the terminals using the first photolithography patterning, removing the first photolithography pattern, forming a second photolithography pattern over the terminals and at least a portion of the well, deepening the well between the terminals by etching using the second photolithography pattern, removing the second photolithography pattern, and finishing the terminals and the well to form a device on the material stack.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: MARKO RADOSAVLIJEVIC, Benjamin Chu-Kung, Mantu K. Hudait, Ravi Pillarisetty
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Publication number: 20100163844Abstract: A layer of high aspect ratio nanoparticles is disposed on a surface of a substrate under the influence of an electrical field applied on the substrate. To create the electrical field, a voltage is applied between a pair of electrodes arranged near the substrate or on the substrate, and the high aspect ratio nanoparticles disposed on the substrate are at least partially aligned along direction(s) of the applied electrical field. The high aspect ratio nanoparticles are grown from catalyst nanoparticles in an aerosol, and the aerosol is directly used for forming the nanoparticle layer on the substrate at room temperature. The nanoparticles may be carbon nanotubes, in particular single wall carbon nanotubes. The substrate with the layer of aligned high aspect ratio nanoparticles disposed thereon can be used for fabricating nanoelectronic devices.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventor: Vladimir Alexsandrovich Ermolov
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Publication number: 20100163843Abstract: The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.Type: ApplicationFiled: September 11, 2008Publication date: July 1, 2010Applicant: Chungbuk National University Industry-Academic Cooperation FoundationInventors: Jung Bum Choi, Chang Keun Lee, Min Sik Kim
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Publication number: 20100163850Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Inventors: Gee-Sung Chae, Mi-Kyung Park
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Publication number: 20100163845Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Niti Goel, Wilman Tsai, Jack Kavalieros
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Publication number: 20100163848Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Prashant Majhi, Jack Kavalieros, Wilman Tsai
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Publication number: 20100163846Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20100163847Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Publication number: 20100155701Abstract: A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer and having a first sidewall, a source region formed on the III-V source extension region and having a second sidewall, a III-V drain extension region formed on the III-V etch stop layer and having a third sidewall, a drain region formed on the III-V drain extension region and having a fourth sidewall, a conformal high-k gate dielectric layer formed on the first, second, third, and fourth sidewalls and on a top surface of the etch stop layer, and a metal layer formed on the high-k gate dielectric layer.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Inventors: Marko Radosavljevic, Benjamin Chu-Kung, Mantu K. Hudait, Ravi Pillarisetty
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Publication number: 20100155702Abstract: A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample- and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).Type: ApplicationFiled: March 28, 2008Publication date: June 24, 2010Inventor: Lars-Erik Wernersson
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Publication number: 20100155703Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.Type: ApplicationFiled: July 7, 2009Publication date: June 24, 2010Inventors: Myung-Sim JUN, Moon-Gyu JANG, Tae-Gon NOH, Tae-Moon ROH
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Publication number: 20100156475Abstract: A group III nitride-based transistor capable of achieving terahertz-range cutoff and maximum frequencies of operation at relatively high drain voltages is provided. In an embodiment, two additional independently biased electrodes are used to control the electric field and space-charge close to the gate edges.Type: ApplicationFiled: December 23, 2009Publication date: June 24, 2010Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
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Publication number: 20100152057Abstract: The present invention generally relates to nanoscale wire devices and methods for use in determining analytes suspected to be present in a sample. The invention provides a nanoscale wire that has improved sensitivity, as the carrier concentration in the wire is controlled by an external gate voltage, such that the nanoscale wire has a Debye screening length that is greater than the average cross-sectional dimension of the nanoscale wire when the nanoscale wire is exposed to a solution suspected of containing an analyte. This Debye screening length (lambda) associated with the carrier concentration (p) inside nanoscale wire is adjusted by adjusting the gate voltage applied to an FET structure, such that the carriers in the nanoscale wire are depleted.Type: ApplicationFiled: November 19, 2007Publication date: June 17, 2010Applicant: President and Fellows of Havard CollegeInventors: Charles M. Lieber, Xuan Gao, Gengfeng Zheng
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Publication number: 20100148153Abstract: A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Robert S. Chau, Marko Radosavljevic, Ravi Pillarisetty, Aaron A. Budrevich
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Patent number: 7737432Abstract: A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit.Type: GrantFiled: June 14, 2005Date of Patent: June 15, 2010Assignee: National Research Council of CanadaInventors: Pawel Hawrylak, Marek Korkusinski
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Patent number: 7737467Abstract: A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.Type: GrantFiled: August 22, 2006Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Masaaki Onomura
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Publication number: 20100142259Abstract: Disclosed are methods of fabricating nanogaps and various devices composed of nanogaps. The nanogap devices disclosed herein can be used as in a number of electronic, photonic and quantum mechanical devices, including field-effect transistors and logic circuits.Type: ApplicationFiled: March 21, 2006Publication date: June 10, 2010Applicant: The Trustees of the University of PennsylvaniaInventors: Marija Drndic, Michael Fischbein
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Publication number: 20100140588Abstract: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes a catalyst portion (55) containing a second material which is different from the first material. The first material includes a metal containing at least one of elements selected from the second group to the fourteenth group of the periodic table or a compound thereof. The second material is a catalyst which grows carbon nanotubes in a vapor phase.Type: ApplicationFiled: July 17, 2009Publication date: June 10, 2010Applicant: NEC CORPORATIONInventor: Hiroo Hongo
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Publication number: 20100140589Abstract: A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.Type: ApplicationFiled: December 4, 2009Publication date: June 10, 2010Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventor: Mihai Adrian IONESCU
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Publication number: 20100140590Abstract: The present invention is a transistor and a process for making the transistor in which the semiconductor component comprises at least one carbon nanotube functionalized by cycloaddition with a fluorinated olefin. Functionalization with the fluorinated olefin renders the carbon nanotube semiconducting.Type: ApplicationFiled: December 8, 2009Publication date: June 10, 2010Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: GRACIELA BEATRIZ BLANCHET, Helen S. M. Lu
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Patent number: 7732804Abstract: Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.Type: GrantFiled: August 20, 2003Date of Patent: June 8, 2010Assignee: Quocor Pty. Ltd.Inventors: Lloyd Christopher Leonard Hollenberg, Andrew Steven Dzurak, Cameron Wellard, Alexander Rudolf Hamilton, David J. Reilly, Gerard J. Milburn, Robert Graham Clark
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Publication number: 20100133511Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.Type: ApplicationFiled: November 24, 2009Publication date: June 3, 2010Inventors: Chongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
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Publication number: 20100133512Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.Type: ApplicationFiled: February 4, 2010Publication date: June 3, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ashesh Parikh, Andrew Marshall
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Publication number: 20100133510Abstract: Provided is a bio-sensor chip. The bio-sensor chip includes a sensing part, a board circuit part, a channel part, and a cover. In the sensing part, a target material and a detection material interact with each other to detect the target material. The board circuit part is electrically connected to the sensing part. The channel part provides a solution material containing the target material into the sensing part. The cover is coupled to the board circuit part to cover the channel part and the sensing part.Type: ApplicationFiled: September 16, 2009Publication date: June 3, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Taeyoub KIM, Jong-Heon YANG, Chang-Geun AHN, Chan Woo PARK, Chil Seong AH, Ansoon KIM, In Bok BAEK, Gun Yong SUNG, Seon Hee PARK
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Publication number: 20100133509Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.Type: ApplicationFiled: June 4, 2008Publication date: June 3, 2010Applicant: PANASONIC CORPORATIONInventors: Takahiro Kawashima, Tohru Saitoh
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Publication number: 20100127242Abstract: Methods and devices for transparent electronics are disclosed. According to an embodiment, transparent electronics are provided based on transfer printed carbon nanotubes that can be disposed on both rigid and flexible substrates. Methods are provided to enable highly aligned single-walled carbon nanotubes (SWNTs) to be used in transparent electronics for achieving high carrier mobility while using low-temperature processing. According to one method, highly aligned nanotubes can be grown on a first substrate. Then, the aligned nanotubes can be transferred to a rigid or flexible substrate having pre-patterned gate electrodes. Source and drain electrodes can be formed on the transferred nanotubes. The subject devices can be integrated to provide logic gates and analog circuitry for a variety of applications.Type: ApplicationFiled: August 10, 2009Publication date: May 27, 2010Inventors: CHONGWU ZHOU, Fumiaki Ishikawa, Hsiao-Kang Chang, Koungmin Ryu