Field Effect Device Patents (Class 257/24)
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Publication number: 20110315960Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Inventors: Niti Goel, Wilman Tsai, Jack Kavalieros
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Publication number: 20110315953Abstract: A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.Type: ApplicationFiled: June 28, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Mikael Bjoerk, Guy M. Cohen, Heike E. Riel, Heinz Schmid
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Publication number: 20110316565Abstract: A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: International Business Machines Corp.Inventors: Dechao Guo, Christian Lavoie, Christine Qiqing Ouyang, Yanning Sun, Zhen Zhang
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Patent number: 8084308Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.Type: GrantFiled: May 21, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
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Publication number: 20110309333Abstract: A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Ghavam G. Shahidi
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Publication number: 20110309334Abstract: A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.Type: ApplicationFiled: June 22, 2010Publication date: December 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
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Publication number: 20110309332Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
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Publication number: 20110297916Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: ApplicationFiled: May 25, 2011Publication date: December 8, 2011Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Publication number: 20110278544Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
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Publication number: 20110278543Abstract: A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar, Jeffrey W. Sleight
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Publication number: 20110278542Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.Type: ApplicationFiled: May 11, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
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Publication number: 20110272673Abstract: A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxailly depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad.Type: ApplicationFiled: May 10, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
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Patent number: 8053760Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer includes a carbon nanotube structure comprised of carbon nanotubes. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The carbon nanotube structure is connected to both the source electrode and the drain electrode, and an angle exist between each carbon nanotube of the carbon nanotube structure and a surface of the semiconductor layer, and the angle ranges from about 0 degrees to about 15 degrees.Type: GrantFiled: April 2, 2009Date of Patent: November 8, 2011Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Chang-Hong Liu, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Patent number: 8044391Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.Type: GrantFiled: December 3, 2009Date of Patent: October 25, 2011Assignee: LG Display Co., Ltd.Inventors: Gee-Sung Chae, Mi-Kyung Park
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Publication number: 20110253981Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.Type: ApplicationFiled: April 8, 2011Publication date: October 20, 2011Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: Rita Rooyackers, Daniele Leonelli, Anne Vandooren, Anne S. Verhulst, Roger Loo, Stefan De Gendt
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Publication number: 20110253982Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.Type: ApplicationFiled: October 28, 2009Publication date: October 20, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
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Publication number: 20110253980Abstract: Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.Type: ApplicationFiled: April 19, 2010Publication date: October 20, 2011Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Christian Lavoie, Zhen Zhang
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Patent number: 8039334Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.Type: GrantFiled: October 12, 2010Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
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Publication number: 20110233523Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Dae SUK, Kyoung-Hwan YEO, Ming LI, Yun-Young YEOH
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Publication number: 20110233521Abstract: The present disclosure relates to a semiconductor device that has a first semiconductor structure that is grown to form a non-planar growth surface. The non-planar growth surface is formed from multiple facets and provides a defined contour. The defined contour may include, but is not limited to a corrugated contour or a pyramidal contour. A second semiconductor structure is grown over the non-planar growth surface of the first semiconductor structure, and as such, the second semiconductor structure is non-planar and follows the defined contour of the non-planar growth surface of the first semiconductor structure. The first and second semiconductor structures may form the foundation for various types of electrical and optoelectrical semiconductor devices, such as diodes, transistors, thyristors, and the like.Type: ApplicationFiled: March 24, 2010Publication date: September 29, 2011Applicant: CREE, INC.Inventor: Adam William Saxler
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Publication number: 20110233522Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: International Business Machines CorporationInventors: Guy Cohen, Conal E. Murray, Michael J. Rooks
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Patent number: 8026508Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.Type: GrantFiled: July 7, 2009Date of Patent: September 27, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Myung-Sim Jun, Moon-Gyu Jang, Tae-Gon Noh, Tae-Moon Roh
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Patent number: 8026509Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.Type: GrantFiled: December 30, 2008Date of Patent: September 27, 2011Assignee: Intel CorporationInventors: Niti Goel, Wilman Tsai, Jack Kavalieros
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Patent number: 8026504Abstract: A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.Type: GrantFiled: March 2, 2009Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
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Publication number: 20110227043Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8022393Abstract: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.Type: GrantFiled: July 29, 2008Date of Patent: September 20, 2011Assignee: Nokia CorporationInventor: Alan Colli
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Publication number: 20110220875Abstract: A method for manufacturing a semiconductor device comprises: growing a carbon nano tube on a semiconductor substrate; forming an insulating film in the inside and the outside of the carbon nano tube; and forming a graphene on the surface of the insulating film, thereby securing a channel region corresponding to a region extended by the carbon nano tube to prevent a short channel effect. As a result, channel resistance is reduced to facilitate the manufacturing of the device that can be operated at a high speed. The carbon nano tube is applied to a semiconductor device of less than 30 nm so that a micro-sized semiconductor device can be manufactured regardless of limitation of exposure light sources.Type: ApplicationFiled: July 11, 2010Publication date: September 15, 2011Applicant: Hynix Semiconductor Inc.Inventor: Chi Hwan JANG
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Patent number: 8017933Abstract: A compositionally-graded quantum well channel for a semiconductor device is described. A semiconductor device includes a semiconductor hetero-structure disposed above a substrate and having a compositionally-graded quantum-well channel region. A gate electrode is disposed in the semiconductor hetero-structure, above the compositionally-graded quantum-well channel region. A pair of source and drain regions is disposed on either side of the gate electrode.Type: GrantFiled: June 30, 2008Date of Patent: September 13, 2011Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu K. Hudait, Marko Radosavljevic, Gilbert Dewey, Willy Rachmady, Titash Rakshit
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Patent number: 8017934Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: August 4, 2010Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20110215298Abstract: A photodetector is provided that includes a FET structure with a channel structure having one or more nanowire structures. Noble metal nanoparticles are positioned on the channel structure so as to produce a functionalized channel structure. The functionalized channel structure exhibits pronounced surface plasmon resonance (SPR) absorption near the SPR frequency of the noble metal nanoparticles.Type: ApplicationFiled: March 2, 2010Publication date: September 8, 2011Inventors: Jin Young Kim, Ramses Martinez, Francesco Stellacci, Javier Martinez, Ricardo Garcia
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Patent number: 8013320Abstract: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.Type: GrantFiled: March 1, 2007Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Hisayoshi Matsuo, Tatsuo Morita, Tetsuzo Ueda, Daisuke Ueda
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Patent number: 8013324Abstract: In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.Type: GrantFiled: April 3, 2009Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Lidija Sekaric
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Patent number: 8013321Abstract: A composite of a base and an array of needle-like crystals formed on the surface of the base is provided, in which the base side and the opposite side to the base with respect to the array can be isolated in a satisfactory manner. A composite 10 includes a transparent electrode 2 serving as the base, an array 4 of needle-like crystals 3 formed thereon, and a coating film 15 covering the surface of the needle-like crystals 3. The needle-like crystals 3 are made of, for example, zinc oxide, and the coating film 15 contains, for example, titanium oxide. The array 4 includes a first region R1 on the transparent electrode 2 side and a second region R2 on the opposite side to the transparent electrode 2 with respect to the first region R1.Type: GrantFiled: May 31, 2006Date of Patent: September 6, 2011Assignees: Kyocera Corporation, Susumu YoshikawaInventors: Junji Aranami, Susumu Yoshikawa
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Patent number: 8008650Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.Type: GrantFiled: November 30, 2010Date of Patent: August 30, 2011Assignee: Japan Science and Technology AgencyInventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao
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Patent number: 8008649Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.Type: GrantFiled: February 13, 2009Date of Patent: August 30, 2011Assignee: Board of Regents, The University of Texas SystemInventors: Leonard Franklin Register, II, Sanjay Banerjee
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Publication number: 20110204332Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.Type: ApplicationFiled: January 31, 2011Publication date: August 25, 2011Applicants: Samsung Electronics Co., Ltd.Inventors: Eun-hong Lee, Seung-hun Hong, Un-jeong Kim, Hyung-woo Lee, Sung Myung
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Publication number: 20110204331Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.Type: ApplicationFiled: March 26, 2008Publication date: August 25, 2011Inventors: Lars Samuelson, Claes Thelander
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Patent number: 7999248Abstract: A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO3 and LaAlO3 is provided. The method uses the tip of a conducting atomic force microscope to locally and reversibly switch between conducting and insulating states. This allows ultra-high density patterning of quasi zero or one dimensional electron gas conductive regions, such as nanowires and conducting quantum dots respectively. The patterned structures are stable at room temperature after removal of the external electric field.Type: GrantFiled: March 25, 2008Date of Patent: August 16, 2011Assignee: University of Pittsburgh-of the Commonwealth System of Higher EducationInventor: Jeremy Levy
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Patent number: 7989800Abstract: A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode.Type: GrantFiled: October 14, 2009Date of Patent: August 2, 2011Assignee: George Mason Intellectual Properties, Inc.Inventors: Qiliang Li, Dimitris E. Ioannou, Yang Yang, Xiaoxiao Zhu
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Publication number: 20110180846Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Heng-Kuang Lin, Pei-Chin Chiu, Jen-Inn Chyi, Han-Chieh Ho, Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
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Publication number: 20110168980Abstract: A nanofiber composite including a nanofiber formed of a hydrophobic polymer, a nanowire formed of a conductive or semiconductive organic material that is oriented in the nanofiber in the longitudinal direction of the nanofiber, and an ionic active material.Type: ApplicationFiled: June 30, 2010Publication date: July 14, 2011Inventors: Jae-hyun Hur, Jong-jin Park, Seung-nam Cha, Jong-min Kim, Chi-yul Yoon
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Publication number: 20110163296Abstract: Disclosed herein are methods of preparing and using doped MWNT electrodes, sensors and field-effect transistors. Devices incorporating doped MWNT electrodes, sensors and field-effect transistors are also disclosed.Type: ApplicationFiled: January 26, 2007Publication date: July 7, 2011Inventors: Salvatore J. Pace, Piu Francis Man, Ajeeta Pradip Patil, Kah Fatt Tan
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Publication number: 20110163297Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Inventors: Mark A. Crowder, Yutaka Takafuji
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Patent number: 7973305Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer comprises at least two stacked carbon nanotube films, and each carbon nanotube film comprises a plurality of carbon nanotubes primarily oriented along a same direction, and the carbon nanotubes in at least two adjacent carbon nanotube films are aligned along different directions.Type: GrantFiled: April 2, 2009Date of Patent: July 5, 2011Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Publication number: 20110156005Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Inventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
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Publication number: 20110156006Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.Type: ApplicationFiled: March 11, 2011Publication date: June 30, 2011Inventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
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Publication number: 20110156004Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Inventors: Marko Radosavljevic, Uday Shah, Gilbert Dewey, Niloy Mukherjee, Robert S. Chau, Jack Kavalieros, Ravi Pillarisetty, Titash Rakshit, Matthew V. Metz
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Publication number: 20110147713Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
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Publication number: 20110147714Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.Type: ApplicationFiled: June 14, 2010Publication date: June 23, 2011Applicants: Samsung Electronics Co., Ltd., Seoul University Research and Business FoundationInventors: Seung Hun HONG, Byeong Ju KIM, Moon Sook LEE
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Publication number: 20110147708Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Inventors: Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Niloy Mukherjee