Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

Abstract: A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench. Conductive contacts are formed in the passivating layer to provide electrical connectivity to the fins. The conductive contacts are in direct contact with sidewalls of the barrier. A semiconductor device includes a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

Abstract: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

Abstract: In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and an overheating detection circuit for detecting overheating of the switching circuit.

Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.

Abstract: A new form of a solid-state non-volatile memory cell is presented. The solid-state memory cell comprises a series of different layers of ferroelectric materials, semiconductors, ferroelectric semiconductors, metals, and ceramics, and oxides. The memory device stores information in the direction and magnitude of polarization of the ferroelectric layers. Additionally, a method is presented for storing multiple bits of information in a single memory cell by allowing partial polarization of a single ferroelectric layer and stacking of multiple ferroelectric functional units on top of each other. Additionally, a technique for reading and writing said memory cell is presented. Additionally, the memory cell design allows for the formation of Schottky barriers which act to improve functionality and increase resistance. Additionally, a method is presented for depositing textured lithium niobate thin films.

Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

Abstract: A Ga2O3 semiconductor element includes: an n-type ?-Ga2O3 single crystal film, which is formed on a high-resistance ?-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type ?-Ga2O3 single crystal film; and a gate electrode, which is formed on the n-type ?-Ga2O3 single crystal film between the source electrode and the drain electrode.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

Abstract: A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe.

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract: Provided is a diode element, a detecting device, and the like which solve problems of a conventional lateral diode element. In the conventional element, a semiconductor interface appears in current path between two electrodes on a surface thereof, and thus noise caused by the interface is large. The diode element includes: a first-conductive-type low carrier concentration layer; a first-conductive-type high carrier concentration layer; and a Schottky electrode and an ohmic electrode which are formed on a semiconductor surface. The low carrier layer has a carrier concentration that is lower than that of the high carrier layer. The diode element includes a first-conductive-type impurity introducing region formed below the ohmic electrode, and includes a second-conductive-type impurity introducing region so as not to be in electrical contact with the Schottky electrode on the semiconductor surface between the Schottky and the ohmic.

Abstract: An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

Abstract: An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Abstract: A semiconductor device includes a semiconductor layer, an insulating film of silicon nitride on the semiconductor layer, source and drain electrodes formed in openings of the insulating film and in contact with the semiconductor layer, and a gate electrode formed in an opening in the insulating film that is located between the source electrode and the drain electrode and formed in contact with the semiconductor layer. The insulating film has an Si content that is uniform in a direction of thickness of the insulating film, an upper region, and a lower region. The upper region can have an oxygen concentration that is greater than that of the lower region. The upper region can be formed by exposing the surface of the insulating film to ozone or an oxygen plasma.

Abstract: A semiconductor device includes a first active layer disposed over a substrate. The second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. The first electrode establishes a Schottky junction with the second active layer. The first electrode includes a first electrode pad and a first series of fingers in electrical contact with the first electrode pad. The second electrode establishes an ohmic junction with the first active layer. The second electrode includes a second electrode pad and a second series of fingers in electrical contact with the second electrode pad. The first and second series of electrode fingers form an interdigitated pattern. The first electrode pad is located over the first and second series of electrode fingers.

Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

Abstract: High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain.

Abstract: Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.

Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.

Abstract: It is to enhance a current increasing effect by increasing a stress applied on a channel of a transistor. The invention is characterized by comprising: side wall insulating films 33 and 53 formed on a semiconductor substrate 11 with trenches 39 and 59 which are formed by removing dummy gates; gate electrodes 43 and 63 formed within the trenches 39 and 59 through a gate insulating film 41; first and second stress applying films 21 and 22 respectively formed along the side wall insulating films 33 and 53 over the semiconductor substrate 11; and source/drain regions 35, 36, 55, and 56 which are formed in the semiconductor substrate 11 on the both sides of the gate electrodes 43 and 63, in that the stress applying films 21 and 22 are formed before the first trench 39 and the second trench 59 are formed.

Abstract: According to one embodiment, a solid-state imaging device includes a first structure part, a second structure part, and a third structure part. The first structure part includes a first insulating body and a first photoelectric conversion part. The first photoelectric conversion part is periodically disposed in the first insulating body and selectively absorbs light in the first wavelength band. The second structure part includes a second insulating body and a second photoelectric conversion part. The second photoelectric conversion part is periodically disposed in the second insulating body and selectively absorbs light in the second wavelength band. The third structure part includes a third photoelectric conversion part. The third photoelectric conversion part absorbs light in a third wavelength band. When viewed in the light incidence direction, the first photoelectric conversion part, the second photoelectric conversion part, and the third photoelectric conversion part are disposed in this order.

Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.

Abstract: Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.

Abstract: A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.

Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.

Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.

Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.

Abstract: A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it.

Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

Abstract: A Schottky diode includes a first nitride-based semiconductor layer disposed atop a substrate. A second nitride-based semiconductor layer is disposed atop a portion of the first nitride-based semiconductor layer. The second layer has a doping concentration lower than that of the first layer. A first Schottky contact metal layer having a first metal work function is disposed on a top planar surface of the second layer, forming a first Schottky junction. A second Schottky contact metal layer having a second metal work function is disposed atop of and laterally surrounding the first Schottky contact metal layer, the metal work function of the second metal layer is higher than that of the first metal layer. A metal layer disposed on first and second planar surfaces forms an ohmic contact with the first nitride-based semiconductor layer.

Abstract: A mask frame assembly for thin film deposition includes a frame including an opening portion, and a plurality of unit mask strips that are fixed to the frame after a tensile force is applied to both of end portions of the unit mask strips in a lengthwise direction of the unit mask strips. Each of the plurality of unit mask strips includes a plurality of unit masking pattern portions each including a plurality of opening patterns. Before the tensile force is applied to both of the end portions of the unit mask strips in the lengthwise direction and the unit mask strips are fixed to the frame, a width of each of the unit masking pattern portions in a widthwise direction perpendicular to the lengthwise direction increases as a function of a closeness of a portion of the unit masking pattern portion where the width is measured to a central portion of each of the unit masking pattern portions.

Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.