With Schottky Gate Patents (Class 257/280)
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Publication number: 20130277718Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing Chor Chan, Chih Min Hu, Jeng Gong
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Publication number: 20130277687Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: ApplicationFiled: March 12, 2013Publication date: October 24, 2013Applicant: RF MICRO DEVICES, INC.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Patent number: 8552476Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.Type: GrantFiled: September 19, 2011Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki
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Patent number: 8546852Abstract: A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width WA1 of the active area between gate and source is wider than width WA2 of the active area between gate and drain. Channel resistance of an active area between source and gate placed between a gate electrode and a source electrode is reduced, and high-frequency performance is provided.Type: GrantFiled: October 28, 2008Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8519440Abstract: A semiconductor device includes: a semiconductor substrate of a compound semiconductor material; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer varies with distance from a top surface of the channel layer and is inversely proportional to the third power of depth into the channel layer from the top surface of the channel layer. The buffer layer has a lower electron affinity than the channel layer and is a different compound semiconductor material from the channel layer.Type: GrantFiled: May 1, 2012Date of Patent: August 27, 2013Assignee: Mitsubishi Electric CorporationInventor: Yoichi Nogami
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Patent number: 8518778Abstract: A method of forming a semiconductor structure is provided. A second area is between first and third areas. An epitaxial layer is formed on a substrate. A first gate is formed in the epitaxial layer and partially in first and second areas. A second gate is formed in the epitaxial layer and partially in second and third areas. A body layer is formed in the epitaxial layer in first and second areas. A doped region is formed in the body layer in the first area. All of the doped region, the epitaxial layer and the second gate are partially removed to form a first opening in the doped region and in the body layer in the first area, and form a second opening in the epitaxial layer in the third area and in a portion of the second gate. A first metal layer is filled in first and second openings.Type: GrantFiled: May 25, 2012Date of Patent: August 27, 2013Assignee: Excelliance MOS CorporationInventor: Chu-Kuang Liu
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Patent number: 8519452Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.Type: GrantFiled: September 29, 2011Date of Patent: August 27, 2013Assignee: DENSO CORPORATIONInventor: Rajesh Kumar Malhan
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Patent number: 8492254Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.Type: GrantFiled: November 10, 2011Date of Patent: July 23, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Tomonori Mizushima
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Patent number: 8487319Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.Type: GrantFiled: November 30, 2010Date of Patent: July 16, 2013Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Publication number: 20130161706Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).Type: ApplicationFiled: February 21, 2013Publication date: June 27, 2013Applicant: International Business Machines CorporationInventor: International Business Machines Corporation
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Patent number: 8461631Abstract: A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.Type: GrantFiled: July 23, 2007Date of Patent: June 11, 2013Assignee: Sensor Electronic Technology, Inc.Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
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Patent number: 8455980Abstract: The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.Type: GrantFiled: July 8, 2011Date of Patent: June 4, 2013Assignee: National Semiconductor CorporationInventor: Jeffrey A. Babcock
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Patent number: 8450798Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the top surface of the semiconductor layer adjacent the trench so as to form a Schottky contact with the top surface of the semiconductor layer adjacent the trench. A surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.Type: GrantFiled: October 21, 2011Date of Patent: May 28, 2013Assignee: Fairchild Semiconductor CorporationInventor: Fred Session
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Patent number: 8421128Abstract: A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.Type: GrantFiled: December 19, 2007Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
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Patent number: 8410531Abstract: A thin film transistor having Schottky barrier includes a substrate, a first gate conductive layer formed on the substrate, a first semiconductor layer having a first conductive type formed on the first gate conductive layer, a source conductive layer and a drain conductive layer electrically isolated from each other and positioned on the first semiconductor layer, a second semiconductor layer having a second conductive type formed on the source conductive layer and the drain conductive layer, and a second gate conductive layer formed on the second semiconductor layer. The first conductive type is complementary to the second conductive type.Type: GrantFiled: February 16, 2011Date of Patent: April 2, 2013Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Ming-Tse Chang, Chun-Wei Su
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Patent number: 8401496Abstract: A semiconductor antenna switch has an antenna terminal, a transmission terminal and a reception terminal. The antenna switch is capable of reducing harmonic distortion even though it includes field effect transistors formed over a silicon substrate. A shunt transistor including a plurality of series-connected field effect transistors is connected between he transmission terminal and a common terminal, such as a common terminal, which may be an electrical ground. Off capacitances and/or gate widths of a plurality of the series-connected field effect transistors increase monotonically in the direction from the common terminal to the transmission terminal, or equivalently, decrease monotonically in the direction from the transmission terminal to the common terminal.Type: GrantFiled: May 23, 2011Date of Patent: March 19, 2013Assignee: Renesas Electronics CorporationInventors: Satoshi Goto, Masao Kondo
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Patent number: 8390065Abstract: An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer provided therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region.Type: GrantFiled: June 23, 2010Date of Patent: March 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8385876Abstract: In view of achieving a cost reduction of an antenna switch, a technique is provided which can reduce harmonic distortion generated in the antenna switch as much as possible in particular even when the antenna switch is comprised of a field effect transistor formed over a silicon substrate. Each of a TX series transistor, an RX series transistor, and an RX shunt transistor is comprised of a low voltage MISFET, while a TX shunt transistor is comprised of a high voltage MISFET. Thus, by reducing the number of serial connections of the high voltage MISFETs constituting the TX shunt transistor, the nonuniformity of the voltage amplitudes applied to the respective serially-coupled high voltage MISFETs is suppressed. As a result, the generation of high-order harmonics can be suppressed.Type: GrantFiled: July 31, 2012Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Satoshi Goto, Tomoyuki Miyake, Masao Kondo
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Patent number: 8368126Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: GrantFiled: April 7, 2008Date of Patent: February 5, 2013Assignee: Vishay-SiliconixInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-In Chen
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Patent number: 8338834Abstract: The diamond semiconductor device is a diamond semiconductor device where a pair of electrodes are fixed on a diamond substrate, and wherein at least one interface to the electrode on the surface of the diamond substrate has a hydrogen termination and at least the surface of the substrate between the pair of two electrodes is controlled to have a larger electric resistivity value than inside the substrate. Accordingly, a diamond semiconductor device can be realized, capable of attaining the device work stability, especially the device work stability in severe environments such as high temperature with exhibiting the function of the hydrogen termination thereof to the utmost extent.Type: GrantFiled: July 3, 2008Date of Patent: December 25, 2012Assignee: National Institute for Materials ScienceInventors: Tokuyuki Teraji, Satoshi Koizumi, Yasuo Koide
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Patent number: 8330280Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.Type: GrantFiled: June 20, 2011Date of Patent: December 11, 2012Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
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Patent number: 8330192Abstract: In broad terms the present invention is a semiconductor junction comprising a first material (102) and a second material (104), in which a surface of one or both of the junction materials has a periodically repeating structure that causes electron wave interference resulting in a change in the way electron energy levels within the junction are distributed.Type: GrantFiled: January 24, 2006Date of Patent: December 11, 2012Assignee: Borealis Technical LimitedInventors: Avto Tavkhelidze, Amiran Bibilashvili, Rodney T. Cox
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Patent number: 8319310Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).Type: GrantFiled: March 31, 2009Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Jenn Hwa Huang
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Publication number: 20120256238Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).Type: ApplicationFiled: April 6, 2011Publication date: October 11, 2012Inventors: Tak H. Ning, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni
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Patent number: 8283221Abstract: The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided.Type: GrantFiled: January 25, 2010Date of Patent: October 9, 2012Inventors: Ishiang Shih, Chunong Qiu, Cindy X. Qiu, Yi-Chi Shih
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Publication number: 20120205726Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: ApplicationFiled: June 1, 2011Publication date: August 16, 2012Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
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Patent number: 8244199Abstract: In view of achieving a cost reduction of an antenna switch, a technique is provided which can reduce harmonic distortion generated in the antenna switch as much as possible in particular even when the antenna switch is comprised of a field effect transistor formed over a silicon substrate. Each of a TX series transistor, an RX series transistor, and an RX shunt transistor is comprised of a low voltage MISFET, while a TX shunt transistor is comprised of a high voltage MISFET. Thus, by reducing the number of serial connections of the high voltage MISFETs constituting the TX shunt transistor, the nonuniformity of the voltage amplitudes applied to the respective serially-coupled high voltage MISFETs is suppressed. As a result, the generation of high-order harmonics can be suppressed.Type: GrantFiled: January 28, 2010Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Satoshi Goto, Tomoyuki Miyake, Masao Kondo
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Patent number: 8207559Abstract: In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N? type or P? type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N? and P? channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET).Type: GrantFiled: July 6, 2009Date of Patent: June 26, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai, Alexei Sadovnikov, Zia Alan Shafi
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Patent number: 8193566Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 ?m to 0.6 ?m.Type: GrantFiled: September 21, 2011Date of Patent: June 5, 2012Assignee: Mitsubishi Electric CorporationInventor: Yoichi Nogami
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Patent number: 8183103Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.Type: GrantFiled: March 4, 2010Date of Patent: May 22, 2012Assignee: United Microelectronics Corp.Inventor: Yan-Hsiu Liu
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Patent number: 8168485Abstract: A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.Type: GrantFiled: August 4, 2009Date of Patent: May 1, 2012Assignee: DENSO CORPORATIONInventors: Takeshi Endo, Eiichi Okuno, Takeo Yamamoto, Hirokazu Fujiwara, Masaki Konishi, Yukihiko Watanabe, Takashi Katsuno
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Patent number: 8169008Abstract: The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 17 is formed in an active region defined by an element separation portion 9 on a main surface of a substrate 1 comprising GaAs. The gate electrode 17 is patterned so as to extend in the vertical direction of the page surface between source electrodes 13 and drain electrodes 14, and to extend in left and right directions at other portions. Thus, the ratio of the gate electrode 17 disposed outside the active region is reduced, and the area of a gate pad 17A is reduced.Type: GrantFiled: October 21, 2010Date of Patent: May 1, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Masao Yamane, Atsushi Kurokawa, Shinya Osakabe, Eigo Tange, Yasushi Shigeno, Hiroyuki Takazawa
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Publication number: 20120080728Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.Type: ApplicationFiled: September 29, 2011Publication date: April 5, 2012Applicant: DENSO CORPORATIONInventor: Rajesh Kumar MALHAN
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Patent number: 8148806Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.Type: GrantFiled: November 12, 2008Date of Patent: April 3, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 8134178Abstract: According to an aspect of the invention, a light-emitting element includes a shift thyristor, a light emitting thyristor, and a vertical type gate load resistor. The shift thyristor includes a first anode layer, a first gate layer, and a first cathode layer. The light-emitting thyristor includes a second anode layer, a second gate layer, and a second cathode layer. The vertical type gate load resistor is arranged on the first gate layer under a power line and limits a current flowing from the first gate layer and the second gate layer to the power line.Type: GrantFiled: January 28, 2010Date of Patent: March 13, 2012Assignee: Fuji Xerox Co., Ltd.Inventor: Seiji Ohno
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Patent number: 8134180Abstract: A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a ?c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain eleType: GrantFiled: August 8, 2008Date of Patent: March 13, 2012Assignee: Rohm Co., Ltd.Inventors: Hirotaka Otake, Shigefusa Chichibu
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Patent number: 8129749Abstract: Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier layer wherein the first quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof, a second barrier layer coupled to the first quantum well channel, and a second quantum well channel coupled to the barrier layer wherein the second quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof.Type: GrantFiled: March 28, 2008Date of Patent: March 6, 2012Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu K. Hudait, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Jack T. Kavalieros
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Patent number: 8120072Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.Type: GrantFiled: July 24, 2008Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Publication number: 20120025278Abstract: A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung Yu Hung, Chih Min Hu, Wing Chor Chan, Jeng Gong
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Publication number: 20120025279Abstract: A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively.Type: ApplicationFiled: May 10, 2011Publication date: February 2, 2012Applicant: TSINGHUA UNIVERSITYInventors: Jing Wang, Wei Wang, Lei Guo, Jun Xu
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Publication number: 20120007153Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 ?m to 0.6 ?m.Type: ApplicationFiled: September 21, 2011Publication date: January 12, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Yoichi NOGAMI
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Patent number: 8084793Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.Type: GrantFiled: February 11, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hisao Kawasaki
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Patent number: 8067788Abstract: A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.Type: GrantFiled: April 2, 2008Date of Patent: November 29, 2011Assignee: Renesas Electronics CorporationInventor: Yasunori Bito
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Publication number: 20110284931Abstract: A transistor device sequentially comprises a semiconductor substrate, a drain, a source, a gate metal seed layer and a gate Schottky contact. The gate metal seed layer comprises a gelatinous substance layer and multiple metal seed crystals. A manufacture method comprises steps of providing a semiconductor substrate; forming a drain and a source; forming a patterned photoresist layer with a photolithography to define a gate area on the semiconductor substrate; forming a gate metal seed layer on the semiconductor substrate with a sensitization process and an activation process; and forming a gate Schottky contact on the gate metal seed layer with an electroless plating approach.Type: ApplicationFiled: May 20, 2011Publication date: November 24, 2011Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Wen-Chau Liu, Huey-Ing Chen, Li-Yang Chen, Chien-Chang Huang
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Patent number: 8063420Abstract: A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrode, over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film, below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film.Type: GrantFiled: July 30, 2009Date of Patent: November 22, 2011Assignee: Mitsubishi Electric CorporationInventor: Hirotaka Amasuga
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Publication number: 20110227135Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Publication number: 20110215383Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acidType: ApplicationFiled: May 10, 2011Publication date: September 8, 2011Applicant: EUDYNA DEVICES INC.Inventors: Tadashi Watanabe, Hajime Matsuda
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Patent number: 7989816Abstract: A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode.Type: GrantFiled: May 22, 2009Date of Patent: August 2, 2011Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 7973344Abstract: Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.Type: GrantFiled: April 30, 2008Date of Patent: July 5, 2011Assignee: SuVolta, Inc.Inventor: Srinivasan R. Banna
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Publication number: 20110140180Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.Type: ApplicationFiled: December 14, 2010Publication date: June 16, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko KITAGAWA