Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine.

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.

Abstract: An imaging device may have an array of image sensor pixels each having a photodiode and a floating diffusion node. Each image sensor pixel in the array may also include a dual conversion gain switch and a dual conversion gain capacitor that allows the image sensor pixel to operate in a low conversion gain mode during which the switch is turned on to share charge between the floating diffusion node and the dual conversion gain capacitor, and a high conversion gain mode in which the switch is turned off. During integration, the photodiode may generate more charge than can be held at the floating diffusion node. A buried channel may be provided beneath the dual conversion gain switch to provide a path along which the excess charge can be shared between the floating diffusion node and the dual conversion gain capacitor even when the dual conversion gain switch is off.

Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first plurality of bonding pads and a second plurality of bonding pads are formed in the recesses. In an embodiment, the first plurality of bonding pads have a first width and a first pitch, and the second plurality of bonding pads have the first width and are grouped into clusters. The first plurality of bonding pads and the second plurality of bonding pads in the first substrate are aligned to a third plurality of bonding pads in a second substrate and are bonded using a direct bonding method.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOFSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

Abstract: An image sensor includes a substrate and a plurality of infrared pixels formed in a front side of the substrate and configured to detect infrared light incident on the front side of the substrate. Each of the infrared pixels includes a photodiode, a region free of implants located above the photodiode, and a photogate formed over the substrate and above the photodiode. The image sensor also includes a plurality of color pixels dispersed among the infrared pixels, where each of the color pixels includes a pinned photodiode and is configured to detect visible light. The photodiode of each of the infrared pixels can include a deep charge-accumulation region underlying the pinned photodiode(s) of one or more neighboring color pixel(s). Methods of manufacturing also described and include forming the deep charge-accumulation regions and associated elements prior to forming any implant-blocking elements (e.g., polysilicon photogates) over the substrate.

Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.

Abstract: An image sensor module and method for forming the same are provided. A first side of a first wafer is attached to a first carrier wafer, the first wafer containing a plurality of first chips. A permanent bonding layer is formed on a second side of the first wafer. The permanent bonding layer includes at least one of a patterned bonding layer and a transparent bonding layer. A second chip is bonded with each first chip of the first wafer via the permanent bonding layer there-between. The first chip is one of an image sensor chip and a transparent filter chip, the second chip is the other of the image sensor chip and the transparent filter chip, and the image sensor chip has a photosensitive region facing the transparent filter chip.

Abstract: Provided is an imaging device including a substrate; a pixel array in which pixels are arranged in a two-dimensional manner on the substrate, each pixel including a photoelectric conversion unit that accumulates charges generated from an incident light, a charge holding unit that holds the charges transferred from the photoelectric conversion unit, and an amplification unit that receives the charges transferred from the charge holding unit; and a light-shielding portion arranged to cover at least the charge holding unit. The photoelectric conversion unit and the charge holding unit in each pixel are aligned in a first direction in a top view orthogonal to the substrate. The charge holding units of the neighboring pixels are aligned in a second direction intersecting the first direction in the top view. The light-shielding portion extends in the second direction and over the charge holding units, and covers a region between the charge holding units.

Abstract: A pixel sensor array includes a plurality of surface pixel sensors disposed in a substrate, a layer of dielectric material formed over the surface of the pixel sensors, a plurality of apertures formed in the dielectric layer each aligned with one of the surface pixel sensors and having an inner side wall. A lining layer is formed on the inner side wall of each aperture and is substantially fully reflective to visible light. The lining layer is spaced apart from the surface of the substrate and has a smaller cross-sectional area than a cross-sectional area of each surface pixel sensor. A filler material substantially transparent to visible light is disposed inside of the reflective lining layer and has a top surface lying in the plane with the top surface of the layer of dielectric material. A microlens is disposed over the top surface of each aperture.

Abstract: A display device including a lower structure with a substrate and organic light emitting diode (OLED) pixels and an upper structure with a cover glass, overcoat layer, and a reflective layer. The upper structure is adjoined to the lower structure. The cover glass includes a viewing surface of the display device and covers the OLED pixels. The OLED pixels emit light towards the viewing surface of the display device. An overcoat layer on the cover glass is on a surface opposite to the viewing surface. The reflective layer on the overcoat layer reflects light emitted from the OLED pixels towards the viewing surface.

Abstract: An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.

Abstract: An imaging device includes: a first chip including a light receiving unit, and a read circuit; a second chip including a timing control circuit, an A/D conversion circuit, and a cable transmission circuit; and a connection unit configured to connect the first and the second chips. The read circuit includes a column read circuit and a horizontal selection circuit, and a vertical selection circuit. The connection unit of the first chip is provided in a first area along a side of the rectangular light receiving unit, and in a second area adjacent to the column read circuit, the horizontal selection circuit, and the vertical selection circuit. The connection unit of the second chip is provided in a third area around the timing control circuit, the A/D conversion circuit, and the cable transmission circuit and in a fourth area adjacent to the timing control circuit and the A/D conversion circuit.

Abstract: An imaging device includes: a pixel; a signal line electrically connected to the pixel; and a first and second sample-and-hold circuits electrically connected to the signal line. The pixel includes: a photoelectric converter that generates signal charge; a charge accumulation region that accumulates the signal charge; a reset transistor that resets a voltage of the charge accumulation region; and an amplifier transistor that amplifies a signal voltage. The first sample-and-hold circuit includes: a first switch that is electrically connected to the signal line and has input-output characteristics in which an output is clipped at a clipping voltage with respect to an input exceeding the clipping voltage; and a first capacitor electrically connected to the signal line through the first switch. The second sample-and-hold circuit includes: a second switch electrically connected to the signal line; and a second capacitor electrically connected to the signal line through the second switch.

Abstract: The present disclosure relates to a solid-state imaging apparatus and an electronic device capable of reducing a product yield and reliability risk. By forming a contact by forming an opening in an insulating film on a back surface of a peripheral circuit region without connecting a light-shielding metal on the peripheral circuit region to the ground (GND), the light-shielding metal is connected to a Si substrate. Furthermore, a light-shielding metal on a pixel region is connected to the ground (GND). Therefore, by disposing an isolated region (insulating region) where no metal is formed between the light-shielding metal on the pixel region and the light-shielding metal on the peripheral circuit region, the light-shielding metal on the pixel region does not cause a short circuit with the light-shielding metal on the peripheral circuit region. The present disclosure can be applied to, for example, a CMOS solid-state imaging apparatus used for an imaging apparatus such as a camera.

Abstract: A photoelectric conversion apparatus includes a semiconductor substrate including recessed portions and insulators disposed on the respective recessed portions. The semiconductor substrate includes a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region that is of a conductivity type different from the first-conductivity-type and that is formed in the first semiconductor region, a second-conductivity-type third semiconductor region in contact with the second semiconductor region on a surface of the semiconductor substrate, and a first-conductivity-type fourth semiconductor region that includes the recessed portions. The second semiconductor region and the third semiconductor region are surrounded by the fourth semiconductor region on the surface of the semiconductor substrate. The insulators on the recessed portions extend through the fourth semiconductor region and are in contact with the first semiconductor region.

Abstract: An image sensor, comprising: a photoelectric conversion element; a transfer transistor formed over the photoelectric conversion element; and a reset transistor formed over the photoelectric conversion element, formed substantially at the same level as the transfer transistor, and spaced apart from the transfer transistor by a gap, wherein the transfer transistor and the reset transistor are trench-type transistors and are symmetrical structure to each other with respect to the gap, wherein the photoelectric conversion element is a continuous layer under both the transfer transistor and the reset transistor, and is completely below the transfer transistor and the reset transistor.

Abstract: A solid-state imaging device has: a counter dope region of a first conductivity type which is formed so as to surround a drain region of a transfer transistor of the solid-state imaging device and in which impurity concentration of the first conductivity type is lower than that of the drain region; and an isolating region of a second conductivity type which is formed in a deep region below channel regions of a plurality of transistors and in which impurity concentration of the second conductivity type is higher than that of a well region, wherein a depth position of a lower surface of the counter dope region is deeper than a depth position of a lower surface of a buried channel region.

Abstract: A method of forming a device including a SPAD detector and a BSI visible light sensor positioned on different planes, the device exhibiting improved resolution and pixel density are provided. Embodiments include a photodiode for detecting visible light; and a SPAD detector for detecting IR radiation, wherein the photodiode and the SPAD detector are on different planes.

Abstract: An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate, containing first doping ions and including a pixel region for forming a pixel structure; forming a deeply doped region, in the photosensitive region of the substrate and containing second doping ions; forming a floating diffusion area in the floating diffusion region of the substrate and containing third doping ions; forming a gate structure on the substrate at the junction of the photosensitive region and the floating diffusion region; forming a sidewall film covering the gate structure and the substrate; forming a sidewall spacer; forming a first doped region in the floating diffusion region on one side of the gate structure; forming a metal connection layer on the first doped region; forming an interlayer dielectric layer on the substrate; and forming a source/drain contact plug in the interlayer dielectric layer.

Abstract: A stacked image sensor and a method of manufacturing the same are provided. The stacked image sensor includes a lower photoelectric conversion layer, a micro-lens provided on the lower photoelectric conversion layer, and an upper photoelectric conversion layer provided on the micro-lens. The lower photoelectric conversion layer and the upper photoelectric conversion layer are different types of photoelectric conversion layers.

Abstract: Provided is a technique that reduces patterning defects of data lines in an imaging panel and drain electrodes in thin film transistors without lowering the aperture ratio of the imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes, in each of the pixels, a conversion element that converts scintillation light to electric charge, and a thin film transistor connected to the gate line, data line, and conversion element. A drain electrode of the thin film transistor is formed such that edges of the drain electrode near the data line are more inside the pixel than edges of the conversion element near the data line.

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.

Abstract: The present invention aims at inhibiting the occurrence of thinning or disconnecting of the bias wiring line in an imaging panel and X-ray imaging device, thereby inhibiting signal delays, signal transmission defects, and the like. A second contact hole electrically connecting an electrode of a photodiode to a bias wiring line penetrates a second interlayer insulating film and photosensitive resin layer. In the second contact hole, an area of a region where the photosensitive resin layer opens is smaller than an area of a region where the second interlayer insulating film opens.

Abstract: A display device includes a display substrate; a thin film transistor over the display substrate; a bank layer covering the thin film transistor, where an opening is defined through the bank layer; an emission layer in the opening and including a micro p-n diode; a first electrode electrically connected between the thin film transistor and the emission layer; a second electrode over the emission layer; and a sealing layer covering the second electrode. The thin film transistor and the emission layer are adjacent to each other in a horizontal direction of the display substrate.

Abstract: A photodetection device includes: a photoelectric converter generating charge; a first transfer channel having first and second ends, the first end being connected to the photoelectric converter, charge from the photoelectric converter being transferred from the first end toward the second end; a second transfer channel diverging from the first transfer channel at a first position; a third transfer channel diverging from the first transfer channel at a second position, further than the first position from the first end; a first charge accumulator accumulating charge transferred through the second transfer channel; a second charge accumulator accumulating charge transferred through the third transfer channel; a first gate electrode switching between transfer/cutoff of charge in the first transfer channel; and at least one second gate electrode switching between transfer/cutoff of charge in the second and third transfer channels, the third transfer channel being wider than the second transfer channel.

Abstract: An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region. The second potential level is greater than the first potential level.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A photo detector device is provided. The photo detector device includes a substrate, a first metal layer, a first interlayer dielectric layer, an active layer, a photodiode, and a second metal layer. The first metal layer is disposed on the substrate, wherein the first metal layer includes a gate line and a gate, and the gate is electrically connected to the gate line. The first interlayer dielectric layer is disposed on the first metal layer. The active layer is electrically insulated from the gate and partially overlaps the gate. The photodiode is disposed on the substrate. The second metal layer is disposed on the first interlayer dielectric layer, wherein the second metal layer includes a data line and a bias line, and the bias line is disposed on the photodiode.

Abstract: This solid-state image capturing device includes a light receiving element, a charge holding region, and a floating diffusion region that are arranged in a semiconductor substrate, and the light receiving element, a first transfer gate, and a second transfer gate in the semiconductor substrate, and is configured to have a potential gradient in the charge holding region such that signal charges that have been transferred from the light receiving element to the charge holding region by the first transfer gate are distributed more on the second transfer gate side than on the first transfer gate side.

Abstract: An image sensor pixel may include a photodiode coupled to a pixel charge storage via a charge transfer transistor, a charge overflow capacitor coupled to the pixel charge storage via a gain control transistor, and an adjustable reset drain that is coupled to the charge overflow capacitor via a reset transistor. The reset transistor may receive a reset signal that is dynamically adjusted during an acquisition phase to help reduce flicker. The potential barrier of the reset transistor may also be calibrated during readout to reduce fixed pattern noise among different pixels. The image sensor pixel may generate an image using a linear combination of at least three signals read out using the charge overflow capacitor and light flickering mitigation operations. The image may be a high dynamic range image that is generated from at least a low exposure signal and a high exposure signal.

Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.

Abstract: An image sensor includes a photodiode disposed in a semiconductor material to generate image charge in response to incident light, and a floating diffusion disposed in the semiconductor material proximate to the photodiode. A transfer transistor is coupled to the photodiode to transfer the image charge from the photodiode into the floating diffusion in response to a transfer signal applied to a transfer gate of the transfer transistor. A source follower transistor is coupled to the floating diffusion to amplify a charge on the floating diffusion. The source follower transistor includes a gate electrode including a semiconductor material having a first dopant type; a source electrode, having a second dopant type, disposed in the semiconductor material; a drain electrode, having the second dopant type, disposed in the semiconductor material; and a channel, having the second dopant type, disposed between the source electrode and the drain electrode.

Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.

Abstract: An image sensor for short-wavelength light includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. An anti-reflection or protective layer is formed on top of the pure boron layer. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor.

Abstract: Disclosed is a touch sensor, including a separation layer, an electrode pattern part formed on the separation layer and including at least one electrode pattern and an insulating layer, and a passivation layer formed of an inorganic material on the electrode pattern part, wherein the passivation layer has a thickness selected from among a thickness ranging from 50 nm to 120 nm, a thickness ranging from 220 nm to 290 nm, and a thickness ranging from 360 nm to 420 nm.

Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.

Abstract: A CMOS pixel including a photodiode having a terminal connected to a potential GND and another terminal connected to a sense node by a first MOS transistor; a second MOS transistor connecting the sense node to a potential VDDH; and a third MOS transistor having its gate connected to the sense node, the transistors having a same gate insulator thickness, wherein the third transistor has a gate length and/or width smaller than those of the first and second transistors, wherein difference VDDH-GND is greater than the nominal voltage of the third MOS transistor, and wherein the body or drain region of the third transistor is connected to a potential VL between potentials VDDH and GND.

Abstract: An inventive solid-state imaging apparatus is provided which can improve the efficiency of the electric carrier transfer from a photoelectric conversion portion to an electric-carrier accumulation portion. The solid-state imaging apparatus includes an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and a floating diffusion, and an element isolation region having an insulator defining the active region. In planer view, the width of the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than the width of the active region in the photoelectric conversion portion under the gate of the first transfer transistor.

Abstract: A display device includes a buffer connected to a data line of a display panel, a bias-mode verification unit which generates a bias-mode signal based on an nth image data signal and an mth image data signal (“m” is a natural number smaller than “n”) corresponding to the data line, a data selecting unit which selects one of a plurality of bias enable signals having different duty ratios from one another based on the bias-mode signal, a control signal generating unit which generates a switching control signal based on the bias enable signal selected by the data selecting unit, and a bias control unit which applies, to the buffer, at least one of a plurality of bias control signals having different levels from one another in an output period defined by the switching control signal.

Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor includes: a substrate having a front surface and a back surface; a trench isolation in the substrate, the trench isolation extending from the front surface of the substrate toward the back surface of the substrate, the trench isolation having a first surface and a second surface opposite to the first surface, the first surface being coplanar with the front surface of the substrate, the second surface being distanced from the back surface of the substrate by a distance greater than 0; wherein the substrate includes: a first layer doped with dopants of a first conductivity type, the first layer extending from the back surface of the substrate toward the trench isolation and laterally surrounding at least a portion of sidewalls of the trench isolation.

Abstract: An imaging device of a CMOS type having a global shutter function is downsized. In the imaging device, a photoelectric conversion unit generates charge corresponding to an exposure amount in a predetermined exposure period. A generated charge retaining unit is formed to have a predetermined impurity concentration in a semiconductor substrate and retains the charge. A generated charge transferring unit renders the photoelectric conversion unit and the generated charge retaining unit conductive therebetween after the exposure period has elapsed and transfers the charge from the photoelectric conversion unit to the generated charge retaining unit. An output charge retaining unit is formed to have substantially the same impurity concentration as that of the generated charge retaining unit and retains charge.

Abstract: A camera and a method for manufacturing the camera are disclosed, the camera including parts including a lens unit formed with at least one lens for concentrating an image of an outside object, and an image sensor for converting the image of the outside object concentrated in the lens to an electric signal; and a molding unit for exposing the lens of the lens unit and for integrating the parts without any coupling seams.

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.