Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: Provided is a storage device that includes a plurality of first wiring lines including a plurality of first and second selection lines, a plurality of second wiring lines including a plurality of third and fourth selection lines, a first selection line driver that applies a first voltage and a second voltage to one or more selection lines of the plurality of first and second selection lines respectively, the first voltage and the second voltage being one of a first and a second selection voltage, and the first and the second voltage are different, and a second selection line driver that applies a third voltage and a fourth voltage to one or more selection lines of the plurality of third and fourth selection lines respectively, the third voltage and the fourth voltage being one of the first and the second selection voltage, and the third and the fourth voltage being different.

Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Abstract: A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.

Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.

Abstract: A nonvolatile memory device according to an embodiment includes a first electrode layer, a first barrier layer, a resistive memory layer, a second barrier layer and a second electrode layer that are sequentially disposed. The resistive memory layer comprises a Mott material, the Mott material having a resistivity that varies depending on an externally applied electric field.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

Abstract: An embodiment includes an apparatus comprising: a memory array comprising: a selector switch including top and bottom electrodes, a metal layer, and a solid electrolyte layer; a memory cell in series with the selector switch; bit and write lines, wherein (a) (i) the top electrode couples to one of the bit and write lines and the bottom electrode couples to another of the bit and write lines, and (a) (ii) the memory cell is between one of the top and bottom electrodes and one of the bit and write lines; wherein (b) (i) the metal layer includes silver (Ag), and (b) (ii) Ag ions from the metal layer form a conductive path in the SE layer when the top electrode is biased and disband the conductive path when the top electrode is not biased. Other embodiments Electrode are described herein.

Abstract: Perovskite-based photoactive devices, such as solar cells, include an insulating tunneling layer inserted between the perovskite photoactive material and the electron collection layer to reduce charge recombination and concomitantly provide water resistant properties to the device.

Abstract: A capacitive tuning circuit includes radio frequency (RF) switches connected to an RF line. Each RF switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, and RF terminals having lower metal portions and upper metal portions. Alternatively, the RF terminals can have a trench metal liner separated from a trench metal plug by a dielectric liner. At least one capacitor is formed in part by at least one of the lower metal portions, upper metal portions, or trench metal liner. The capacitive tuning circuit can be set to a desired capacitance value when a first group of the RF switches is in an OFF state and a second group of the RF switches is in an ON state.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.

Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.

Abstract: The semiconductor memory device includes: a first electrode and a second electrode disposed opposed to each other in a first direction; a resistance change film that is provided between the first electrode and the second electrode and contains at least one kind of element selected from germanium, antimony, and tellurium; and a first layer that is provided on a side surface of the resistance change film in a second direction intersecting the first direction and contains at least one kind of the element forming the resistance change film and at least one kind of element selected from nitrogen, carbon, boron, and oxygen.

Abstract: A bulk acoustic wave resonator includes: a substrate; a first electrode disposed on the substrate; a piezoelectric layer at least partially disposed on the first electrode; and a second electrode disposed on the piezoelectric layer; wherein the first electrode includes an aluminum alloy layer containing scandium (Sc), and has a surface roughness of 2.4 nm or less, based on an arithmetic mean roughness.

Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: A structure and formation method of a semiconductor device structure is provided. The method includes forming a lower electrode layer over a semiconductor substrate and forming a data storage layer over the lower electrode layer. The method also includes forming an ion diffusion barrier layer over the data storage layer and forming a capping layer over the ion diffusion barrier layer. The ion diffusion barrier layer is a metal material doped with nitrogen, carbon, or a combination thereof. The capping layer is made of a metal material. The method further includes forming an upper electrode layer over the capping layer.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

Abstract: A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed. The resistive memory device includes a lower electrode, a resistive layer formed in a resistance change region on the lower electrode, an upper electrode formed on the resistive layer, and an insertion layer configured to allow a reset current path of the resistive layer, which is formed from the upper electrode to the lower electrode, to be bypassed in a direction perpendicular to or parallel to a surface of the lower electrode.

Abstract: An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element is physically stacked upon a conductive layer and electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced.

Abstract: Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer.

Abstract: Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

Abstract: An electronic device includes a semiconductor memory comprising row lines, column lines, memory cells, and a plurality of contact plugs including row contact plugs respectively coupled to the row lines and column contact plugs respectively coupled to the column lines. Each memory cell is coupled to a row line and a column line, and has a current path comprising a portion of that row line and a portion of that column line. First and second contact plug are respectively coupled to first and second memory cells respectively having first and second current paths. A resistance of the first current path is lower than a resistance of the second current path, and a resistance of the first contact plug is increased relative to a resistance of the second contact plug to offset the lower resistance of the first current path.

Abstract: The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.

Abstract: The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.

Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.

Abstract: A method for manufacturing a semiconductor memory device includes forming a first silicon layer on a bottom conductive layer, transforming the first silicon layer into a first polysilicon layer, forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer, transforming the second and third silicon layers into second and third polysilicon layers, wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type, forming an amorphous silicon layer on the third polysilicon layer, and forming a top conductive layer on the amorphous silicon layer.

Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

Abstract: A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure, where a first contact formed at an interface between the bottom contact and the memory layer is ohmic, and where a second contact formed at an interface between the memory layer and the top electrode is ohmic.

Abstract: A method is provided that includes forming a memory cell that includes a memory element coupled in series with an isolation element. The isolation element includes a vertical thin-film transistor and a threshold selector device.

Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.

Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.