Abstract: A three-terminal non-volatile multi-state device based on mobile ion induced electrical resistivity change is provided. The three-terminal non-volatile multi-state memory device includes a substrate having a first electrode and a second electrode therein. The three-terminal non-volatile multi-state memory device further includes a mobile ion including resistor layer disposed over the first electrode, the second electrode, and part of the substrate. The three-terminal non-volatile multi-state memory device also includes a third electrode formed over the mobile ion including resistor layer. The three-terminal non-volatile multi-state memory device provides multi-level states determined by an electrical resistivity the mobile ion including resistor layer which changes the electrical resistivity based on the mobile ion concentration in the material.

Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

Abstract: A two-terminal memory device can be formed according to a manufacturing process that utilizes two distinct chemical-mechanical planarization (CMP) processes for each of bottom electrode/terminal (BE) and the top electrode/terminal (TE). The CMP processes can reduce planar height variations for a top surface of the BE and a top surface of the TE. The CMP processes can reduce height differences between the top surface of the BE and adjacent dielectric surfaces and reduce height differences between the top surface of the TE and adjacent dielectric surfaces.

Abstract: The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided.

Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer including CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer including MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

Abstract: A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.

Abstract: A method for depositing a silicon nitride film is provided. A nitrided adsorption site is formed in a recess formed in a surface of a substrate by supplying an ammonia-containing gas to the substrate for nitriding the surface of the substrate including the recess. A non-adsorption site is formed in a predetermined upper area of the recess by adsorbing a chlorine-containing gas on the nitride adsorption site in the predetermined upper area by physical adsorption. The predetermined upper area ranges from an upper end of the recess to a predetermined depth of the recess. A silicon-containing gas is adsorbed on the nitride adsorption site other than the predetermined upper area so as to deposit a silicon nitride film by a chemical reaction between the adsorbed ammonia-containing gas and the adsorbed silicon-containing gas. The nitride adsorption site includes a bottom surface of the recess.

Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.

Abstract: An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.

Abstract: Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

Abstract: A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Abstract: A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.

Abstract: According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

Abstract: A method is provided that includes forming a first level above a substrate, forming a second level above the first level, and forming a third level above the second level. The first level includes a plurality of first elements having a first minimum pitch, the second level includes a plurality of second elements having a second minimum pitch greater than the first minimum pitch, and the third level includes a plurality of third elements having a third minimum pitch greater than the first minimum pitch. The second elements are disposed above and aligned with a first plurality of the first elements, and the third elements are disposed above and aligned with a second plurality of the first elements.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.

Abstract: Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

Abstract: Provided an electronic device including a semiconductor memory. The semiconductor memory may include: a selecting element; a variable resistance element electrically coupled to the selecting element through a first conductive plug; a first line electrically coupled to the variable resistance element through a second conductive plug; a second line electrically coupled to the selecting element through a third conductive plug; and one or more barrier layers arranged to form one or more electrical connections with the variable resistance element or the selecting element or the both and operated as an insulator or conductor according to a resistance state of the variable resistance element during a read operation.

Abstract: A hybrid MOS-PCM IC switch utilizes both MOS transistors and groups of parallel-connected Phase-Change Material (PCM) cells to control signal transmissions. The MOS transistors are separated by PCM cell groups, and the PCM cells are configured to generate similar COFF or lower values as the MOS transistors, whereby the hybrid switch is both smaller and exhibits lower FOM than standard CMOS SOI switches. When switched into an open (OFF/high-resistance) state, both the PCM cells and MOS transistors function to distribute high VBSR voltages, and the MOS transistors prevent unintended phase changes (ON/OFF switching) of the PCM cells by preventing exponential current flow. In the closed (ON/conducting) state, the PCM cells facilitate lower total RON, whereby the hybrid CMOS SOI switch achieves improved FOM. The MOS transistors may also function as drivers during programming (switching) of direct-heating-type PCM cells.

Abstract: A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.

Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN; XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.

Abstract: An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.

Abstract: A memory device according to an embodiment includes an insulating layer containing silicon, an interface layer provided on the insulating layer and containing a chalcogenide compound of a transition metal, and a conductive layer provided on the interface layer, containing antimony or bismuth, and having a superlattice structure.

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns.

Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.

Abstract: The present disclosure relates to integrated circuits having a resistive random access memory (RRAM) cell, and associated methods of forming such RRAM cells. In some embodiments, the RRAM cell includes a bottom electrode and a top electrode which are separated from one another by an RRAM dielectric. A bottom electrode sidewall and a top electrode sidewall are vertically aligned to one another, and an RRAM dielectric sidewall is recessed back from the bottom electrode sidewall and the top electrode sidewall.

Abstract: A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy.

Abstract: A semiconductor structure includes a front side and a back side opposite to the front side, at least a transistor device formed on the front side of the substrate, and an adjustable resistor formed on the back side of the substrate. The adjustable resistor includes at least a phase change material PCM layer.

Abstract: A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; an insulating layer interposed between the first and second electrode layers and containing a plurality of neutral defects; and an additional insulating layer interposed between the insulating layer and one or each of the first and second electrode layers, and being substantially free from neutral defects, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: An electrically alterable thin film memory device or non-volatile trigger which can be switched from a high resistance state to a low resistance state. The device increases the concentration of electrically active impurities at correspondent electrodes to which respect impurities would electro migrate during a large number of set-reset cycles. The device comprises a layered structure with memory layers formed on an interface of two regions as the result of the mutual mixing and migration of their constituents. One region contains an electrically active donor impurity. A thin layer of dielectric is placed in the other region. Each of the memory layers includes an interface of chalcogenide films.

Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

Abstract: The loss of sulfur cathode material as a result of polysulfide dissolution causes significant capacity fading in rechargeable lithium/sulfur cells. Embodiments of the invention use a chemical approach to immobilize sulfur and lithium polysulfides via the reactive functional groups on graphene oxide. This approach obtains a uniform and thin (˜tens of nanometers) sulfur coating on graphene oxide sheets by a chemical reaction-deposition strategy and a subsequent low temperature thermal treatment process. Strong interaction between graphene oxide and sulfur or polysulfides demonstrate lithium/sulfur cells with a high reversible capacity of 950-1400 mAh g?1, and stable cycling for more than 50 deep cycles at 0.1 C.

Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

Abstract: Some embodiments relate to an integrated circuit including a memory cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A data storage layer is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the data storage layer and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: A semiconductor memory includes first to third lines, the second line crossing the first and third lines between the first line and the third line, a first memory element overlapping an intersection region of the first and second lines between the first line and the second line, the first memory element including a first memory layer, a first electrode under the first memory layer, and a second electrode over the first memory layer, and a second memory element overlapping an intersection region of the second and third lines between the second line and the third line, the second memory element including a second memory layer, a third electrode under the second memory layer, and a fourth electrode over the second memory layer. An electrical resistance relation of the third and fourth electrodes is controlled according to an electrical resistance relation of electrical resistances of the first and second electrodes.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.