Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: A semiconductor memory device according to an embodiment comprises: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; and a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a first film whose resistance changes electrically, a second film having conductivity, and a third film having an insulating property which are stacked sequentially in a third direction that intersects the first and second directions.

Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.

Abstract: A first electrode and an insulation material layer are sequentially formed over a substrate. A doping mask pattern is formed over the insulation material layer. The doping mask pattern exposes a portion of the insulation material layer. Dopants are injected into the exposed portion of the insulation material layer. The doping mask pattern is removed. A second electrode layer is formed over the insulation material layer. One or more pillar-shaped structures, each of which includes a second electrode, an insulation layer and a first electrode formed by respectively patterning the second electrode layer, the insulation material layer, and the first electrode layer. Each of the one or more pillar-shaped structures includes, in the insulation layer, a part of the exposed portion of the insulation material layer that is doped with the dopants. A threshold switching operation is performed in a region doped with the dopants of the insulation layer.

Abstract: Discloses is an electronic device and a method for its operation. The device has first and second electrodes and an active material. The active material has selectable and stable first and second macroscopic quantum states, such as charge density wave ordered states, having respectively first and second values of electrical resistivity ?1 and ?2 at the same temperature. ?1 is at least 2 times ?2. The method includes the step of switching between the first and second macroscopic quantum states by injection of current via the electrodes.

Abstract: This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.

Abstract: According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.

Abstract: A method for operating an electronic device including a variable resistance element comprises performing a reset operation on the variable resistance element. The variable resistance element is fully reset by a first reset voltage applied thereto. The performing of the reset operation includes applying a second reset voltage to the variable resistance element, the second reset voltage having a magnitude smaller than that of the first reset voltage, determining whether the variable resistance element is mildly reset or not, and applying a third reset voltage to the variable resistance element when it is determined that the variable resistance element is mildly reset, or terminating the reset operation when it is determined that the variable resistance element is fully reset, the third reset voltage having a magnitude smaller than that of the first reset voltage.

Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

Abstract: A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less ?A level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.

Abstract: An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.

Abstract: A plurality of memory cells in a cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

Abstract: A resistive floating electrode device (RFED) provides a logic cell or non-volatile storage or dynamic or static random access memory on an extremely compact matrix with individual cells scalable to the minimum available lithographic feature size regime by providing atomic switches connected in anti-parallel relationship, preferably with a common inert electrode. Programming is facilitated by limiting current to a compliance current level in order to maintain an OB state from which the cell can be written to either the 0 or 1 state. A perfecting feature of the invention provides for selective operation of a cell as a diode or in a volatile or non-volatile storage mode within the same memory array. A series connection of three or more RFEDs in accordance with the invention having different ON state currents, OFF state currents and reset currents can be used as adaptive, neural or chaotic logic cells.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.

Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

Abstract: A resistive non-volatile memory cell including a Metal-Insulation-Metal stack including two electrodes and a multilayer of insulation, placed between the two electrodes, including a thin layer of oxide allowing for a resistive transition and an oxygen vacancy reservoir layer is provided. The stack includes from bottom to top: the bottom electrode including a metal layer, the insulation including a layer of stoichiometric metal oxide and a layer of substoichiometric metal oxide forming the oxygen vacancy reservoir layer, and the top electrode including a layer of metal oxide and a metal layer, such that the oxygen vacancy reservoir layer is inserted between two metal oxide stoichiometric layers.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

Abstract: A storage device includes a first wiring layer, a second wiring layer above the first wiring layer, a third wiring layer above the second wiring layer, a first contact in electrical contact with the first and third wiring layers and electrically insulated from the second wiring layer, a second contact in electrical contact with the first and second wiring layers and electrically insulated from the third wiring layer, and an insulating layer in contact with the second contact and above the third wiring layer, the first contact, and the second contact.

Abstract: A semiconductor device includes a substrate including a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned in the trench at a level lower than a top surface of the substrate, and including a first buried portion and a second buried portion over the first buried portion; and a first doping region and a second doping region formed in the substrate on both sides of the gate electrode, and overlapping with the second buried portion, wherein the first buried portion includes a first barrier which has a first work function, and the second buried portion includes a second barrier which has a second work function lower than the first work function.

Abstract: A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments.

Abstract: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: Apparatuses and methods include an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines, and the use thereof. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

Abstract: An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The antifuse material layer may be a phase change material alloy of tantalum and nitrogen, wherein at least a base surface of the antifuse material layer is present on the contact surface and sidewall surfaces of the antifuse material layer are present on sidewalls of the opening through the dielectric material. An airgap or solid material core may be in the opening atop the base surface of the phase change material alloy. An electrically conductive material may be in direct contact with at least the antifuse material layer.

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.

Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

Abstract: A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields.

Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A vertical transistor may include a pillar, a gate and an electric field-buffering region. The pillar may be vertically extended from a surface of a semiconductor substrate. The pillar may include a source, a channel region and a drain. The gate may be formed on an outer surface of the pillar. The gate may be overlapped with the channel region, a portion of the source configured to make contact with the channel region, and a portion of the drain configured to make contact with the channel region. The electric field-buffering region may be formed in the portion of the drain overlapped with the gate. The electric field-buffering region may have a band gap different from a band gap of a material in the pillar.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity ? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Abstract: Technology is described for reversible resistivity memory having a crystalline silicon bit line. In one aspect, a memory structure comprises a hollow pillar of crystalline silicon inside of reversible resistivity material. The crystalline silicon may serve as a bit line. The memory structure may further comprise conductive material that forms word lines coupled to the outer surface of the reversible resistivity material. A memory cell comprises a portion of the reversible resistivity material between the crystalline silicon and one of the word lines. In one aspect, the hollow pillar of crystalline silicon surrounds a gate oxide, which surrounds a conductive transistor gate. Thus, the hollow pillar of crystalline silicon may function as a channel of a transistor. In one aspect, the crystalline silicon has predominantly a (100) orientation with respect to an inner surface of the reversible resistivity material. In one aspect, the crystalline silicon is a single crystal.

Abstract: A non-volatile semiconductor memory device according to an embodiment includes a plurality of first wiring lines that extend in a first direction, a plurality of second wiring lines that extend in a second direction intersecting the first direction to cross the first wiring lines, and memory cells, each of which is provided at a portion where the first wiring line crosses the second wiring line. The memory cell includes a variable resistance layer in the space between the wiring lines where the first wiring line crosses the second wiring line, a seam in the variable resistance layer extending in a direction between the first wiring layer and the second wiring layer, and a metal supply layer that comes in contact with the variable resistance layer and the seam.

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer including a defect engineering film; and a top electrode on the resistive material layer.

Abstract: A structure for a resistive memory device and a method to fabricate the same is disclosed. The method includes providing a bottom electrode comprising a metal and forming a memory layer on the bottom electrode. The memory layer includes a first layer of metal oxide, and a second layer including the nitrogen-containing metal oxide. A top electrode is formed over the memory layer.

Abstract: A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.