Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments a method may include forming a structure on a first portion of a substrate while maintaining a second portion of the substrate exposed. A sealing layer may be deposited over the structure and over at least a portion of the exposed second portion of the substrate. A conductive via may be formed by way of a dry etch through the sealing layer to contact the exposed metal layer. In embodiments, an etch-stop control layer may be utilized to control an etching process prior to formation of metal contacts over the CEM switch and the conductive via.

Abstract: A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.

Abstract: A significantly reduced parasitic capacitance phase-change material (PCM) radio frequency (RF) switch includes an RF clearance zone including a step-wise structure of intermediate interconnect segments and vias to connect PCM contacts to setback top routing interconnects. The said RF clearance zone does not include cross-over interconnect segments. A low-k dielectric is situated in the RF clearance zone. A closed-air gap is situated in the RF clearance zone within the low-k dielectric. The setback top routing interconnects are situated higher over a substrate than the PCM contacts and the intermediate interconnect segments. The PCM RF switch may further include an open-air gap situated between the setback top routing interconnects.

Abstract: An electronic component includes an electronic chip and a magnetic phase change material configured to consume energy when changing between different magnetic phases in response to heating above a phase change temperature. The phase change material is thermally coupled with the electronic chip to thereby dissipate heat from the electronic chip upon heating up to or above the phase change temperature.

Abstract: A cross-point array device according to an embodiment includes a substrate, a first pillar structure, including a threshold switching layer, disposed on the substrate, a resistance switching layer surrounding an upper surface and a sidewall surface of the first pillar structure, and a second pillar structure, including a resistance change memory layer, disposed on the resistance switching layer. The resistance switching layer has a conductive filament electrically connecting the first pillar structure to the second pillar structure.

Abstract: Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.

Abstract: To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer insulating film and comprises an active electrode, the side surface and the bottom surface of which are covered by a barrier metal; a variable resistance film that is formed on the upper surface of the first electrode; a second electrode that is formed on the variable resistance film; and an insulating film spacer that is formed between the variable resistance film and the barrier metal which covers the side surface of the first electrode. In this connection, the variable resistance film and the barrier metal which covers the side surface of the first electrode are in contact with the insulating film spacer, respectively.

Abstract: A memory cell includes a bit line and a reset line sharing a same line, a word line, a first diode including a first N-well region in a substrate, and a first P-type doped region adjacent to the first N-well region that is coupled to a set line, a second diode spaced apart from the first diode and including a second N-well region in the substrate, a first N-type doped region and a second P-type doped region spaced apart from each other and adjacent to the second N-well region, the second P-type doped region coupled to the bit line and the reset line, a bottom electrode coupled to the first P-type doped region and the first N-type doped region, a top electrode coupled to the word line, and a data storage material layer disposed between the bottom electrode and the top electrode.

Abstract: A semiconductor device includes a semiconductor fin formed on a substrate, a first gate formed around the semiconductor fin, and a second gate formed around the semiconductor fin below the first gate and separated from the first gate.

Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

Abstract: An array includes a shared pulse generator and a plurality of cells. A selected cell the plurality of cells includes a phase-change material (PCM) and a heating element, the heating element being transverse to the PCM. The array further includes a row selector configured to connect the shared pulse generator to the selected cell, and a selector configured to connect the selected cell to a ground. The shared pulse generator provides an electrical pulse to cause the heating element in the selected cell to generate a heat pulse. In one approach, the selected cell also includes a non-linear device such as a diode, and the shared pulse generator provides the electrical pulse to a PCM RF switch of the selected cell through the non-linear device to change a state of the PCM RF switch.

Abstract: A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: A neuromorphic device includes a synapse. The synapse, according to an embodiment, includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a reactive metal layer disposed between the oxygen-containing layer and the second electrode. The oxygen-containing layer includes oxygen ions. The reactive metal layer is capable of reacting with the oxygen ions of the oxygen-containing layer. A width of the reactive metal layer decreases along a direction toward the oxygen-containing layer from the second electrode.

Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. The oxygen-containing layer includes a P-type material and oxygen ions. The reactive metal layer reacts with the oxygen ions of the oxygen-containing layer. The oxygen diffusion-retarding layer includes an N-type material and interferes with a movement of the oxygen ions from the oxygen-containing layer to the reactive metal layer. An interface between the oxygen-containing layer and the oxygen diffusion-retarding layer is a P-N junction.

Abstract: A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.

Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Abstract: Selector switch provided with: a structure based on at least one phase change material placed between a first conducting element and a second conducting element, the phase change material being capable of changing state, means of heating the phase change material provided with at least one first heating electrode and at least one other heating electrode, the structure based on a phase change material being configured to form a confined active zone of the phase change material at a distance from the conducting elements.

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Abstract: A resistive memory device includes a first electrode, a second electrode spaced from the first electrode along a spacing direction, and a hafnium oxide resistive material portion of a resistive memory cell located between the first electrode and the second electrode and having a compositional modulation in oxygen concentration within directions that are perpendicular to the spacing direction.

Abstract: Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.

Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.

Abstract: An embodiment includes a resistive random access memory (RRAM) comprising: top and bottom electrodes; first and second oxygen exchange layers (OELs) between the top and bottom electrodes; an oxide layer between the first and second OELs; wherein (a) first oxygen vacancies are within an upper third of the oxide layer at a first concentration, (b) second oxygen vacancies are within a lower third of the oxide layer at a second concentration, and (c) third oxygen vacancies are within a middle third of the oxide layer at a third concentration that is less than either of the first and second concentrations. Other embodiments are described herein.

Abstract: A phase change memory and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a heating layer on the substrate; forming a phase change layer on and in contact with one sidewall surface of the heating layer. The phase change memory includes: a substrate; a heating layer on the substrate; and a phase change layer on and in contact with one sidewall surface of the heating layer.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: A nonvolatile memory device according to one embodiment includes a ferroelectric memory element and a resistive memory element. The ferroelectric memory element includes a field effect transistor having a ferroelectric gate dielectric layer. The resistive memory element includes a resistance change memory layer disposed between a first memory electrode and a second memory electrode. A drain electrode of the field effect transistor is connected to the first memory electrode or second memory electrodes.

Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.

Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.

Abstract: A method for treating a semiconductor structure comprising memory devices is provided, wherein a forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.

Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Abstract: A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer. The first insulating film is etched back to expose an upper portion of the fin-shaped semiconductor layer and a second resist is formed so as to be perpendicular to the fin-shaped semiconductor layer. The fin-shaped semiconductor layer is etched to form a pillar-shaped semiconductor layer, such that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles defines the pillar-shaped semiconductor layer.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes first and second conductive lines, and a variable resistance material and a switching element between the first and second conductive lines. The switching element includes first and second portions that extend and/or face in different first and second directions, respectively. Methods of manufacturing a variable resistance memory device are also provided.

Abstract: A crossbar switch includes a plurality of first wires extending in a first direction and second wires extending in a second direction. The switch includes third wires extending in a third direction and fourth wires extending in a fourth direction. The switch includes switch cells connected to the first and second wires. The first wires are skewed relative to the second and fourth wires, while the third wires are skewed relative to the second and fourth wires. The switch cells are connected to the third and fourth wires, and the third wires are also connected to the switch cells connected to the first wires adjacent to the respective first wires, or alternatively the fourth wires are also connected to the switch cells connected to the second wires adjacent to the respective second wires.

Abstract: Methods, systems, and devices for operating memory cell(s) using transition metal doped GST are described. As discussed herein, a composition including germanium (Ge), antimony (Sb), tellurium (Te), and at least one of yttrium (Y) and scandium (Sc) may be used as a memory element in a memory cell. For example, a memory element may include a composition having Ge in an amount ranging from 15 to 35 atomic percent (at. %) of the composition, Sb in an amount less than or equal to 50 at. % of the composition, Te in an amount greater than or equal to 40 at. % of the composition, and at least one of Y and Sc in an amount ranging from 0.15 to 10 at. % of the composition.

Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.

Abstract: A phase change material for a phase change memory and a preparing method thereof. The phase change material for a phase change memory has a chemical formula of Sc100-x-y-zGexSbyTez, wherein 0?x?60, 0?y?90, 0<z?65, 0<100-x-y-z<100. The phase change material for a phase change memory according to the present invention is capable of repeatedly changing phases. The Sc100-x-y-zGexSbyTez has two different resistance value states, i.e., a high resistance state and a low resistance state, and a reversible transformation between the high resistance state and the low resistance state can be achieved by being applied a pulse electrical signal thereto, which satisfies basic requirements of a storage material for the phase change memory.

Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.

Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

Abstract: A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes, comprising a tellurium free, low germanium composition of arsenic As, selenium Se and germanium Ge. The switching device is used in 3D cross-point memory.

Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.

Abstract: Subject matter disclosed herein may relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element disposed over a substrate and structured to exhibit different resistance states for storing data; and an upper contact plug disposed over the variable resistance element and coupled to the variable resistance element, wherein the upper contact plug includes a first portion that is disposed between an upper end of the upper contact plug and a lower end of the upper contact plug and the first portion has a width smaller than a width of each of the upper end and the lower end.

Abstract: A low temperature poly-silicon thin film transistor includes at least an interlayer dielectric layer formed of a material including silicon oxide and silicon nitride, in such a way that the interlayer dielectric layer includes a depression region channel in a stepped form. A source metal layer and a drain metal layer are formed in the depression region channel in the stepped form.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.