Abstract: The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract: The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

Abstract: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.

Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.

Abstract: A storage capacitor has a double cylinder type structure, with a small cylinder in a lower part thereof and a cylindrical lower electrode structure disposed on the cylindrical contact plug. A method of fabricating the storage capacitor includes: forming a contact hole for exposing an activation region of a transistor; depositing a conductive film to form within the contact hole a contact plug of the storage capacitor having a void therein; opening an upper part of the void of the contact plug; and covering a surface of the device with material to form the storage capacitor electrode, to obtain the storage capacitor electrode having a double cylindrical structure.

Abstract: A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground plate to the substrate; the charge storage plates are connected at the top of the capacitor by blocking the end of the first plate during the formation of the second ground plate and exposing the material of the first storage plate during deposition of the second storage plate.

Abstract: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.

Abstract: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer.

Abstract: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines

Abstract: This semiconductor device includes: a first cylinder interlayer insulating film; a second cylinder interlayer insulating film; a cylinder hole including a first cylinder hole and a second cylinder hole communicating with the first cylinder hole; and a capacitor including a lower electrode and an upper electrode. The first cylinder interlayer insulating film has an etching rate for etchant, which is two to six times as high as an etching rate for the second cylinder interlayer insulating film, a hole diameter of the first cylinder hole is larger than that of the second cylinder hole, and the hole diameter of the second cylinder hole near an interface between the first cylinder interlayer insulating film and the second cylinder interlayer insulating film increases as the second cylinder hole approaches the interface.

Abstract: A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, the insulation layer is patterned to form a trench in a predetermined area of an outer electrode around the sacrificial plug. A fenced insulation layer is formed around the sacrificial plug simultaneously. After the sacrificial plug is removed, a metal layer is filled in the predetermined area of the core and outer electrodes. A vertical MIM capacitor comprising the core electrode, the fenced insulation layer, and the outer electrode is finally formed. The invention also provides a vertical MIM capacitor.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliability in the node interconnect. There is provided a semiconductor integrated circuit device, comprising: a node interconnect (lower capacitance electrode), being embedded in a trench formed in an interlayer insulating film provided on a semiconductor substrate, a surface of said lower capacitance electrode being formed to be substantially coplanar to a surface of the interlayer insulating film; and a capacitor, including: a capacitance insulating film, being flatly formed on a surface of the interlayer insulating film; and an upper capacitance electrode, being flatly formed thereon.

Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.

Abstract: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.

Abstract: The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first fabricated in the silicon substrate. An epitaxial silicon layer is then grown on the silicon substrate. Active areas, shallow trench isolation regions, and gate conductors are formed on/in the epitaxial silicon layer.

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions formed continuously. The TFT has the first region of the semiconductor layer including a channel forming region, a source region and a drain region located outside the channel forming region, a gate insulating film adjacent to the first region of the semiconductor layer, and a gate electrode formed on the gate insulating film. The storage capacitor has the second region of the semiconductor layer, an insulating film formed adjacent to the second region of the semiconductor layer, and a capacitor wiring formed on the insulating film. The second region of the semiconductor layer contains an impurity element for imparting n-type or p-type conductivity.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by sidewall spacers.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.

Abstract: A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.

Abstract: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Abstract: The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.

Abstract: A capacitor having a dielectric layer including a composite oxide, the composite oxide including a transition metal and including a lanthanide group element, a memory device including the same and a method of manufacturing the capacitor are provided. The transition metal may be titanium and the composite oxide may be nitrided. The method may include providing a precursor of a transition metal, providing a precursor of a lanthanide group element, and forming a composite oxide on the lower electrode by oxidizing both the precursor of the transition metal and the precursor of the lanthanide group element, the composite oxide containing the transition metal and the lanthanide group element.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Abstract: A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cover the MIM capacitor; a second wiring formed on the second insulating film; and a guard ring buried in the second insulating film to surround the MIM capacitor.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.

Abstract: A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.

Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and he upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.

Abstract: The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.

Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.