Stacked Capacitor Patents (Class 257/303)
  • Patent number: 8207563
    Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 26, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Cem Basceri, Gurtej S. Sandhu
  • Patent number: 8207565
    Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: June 26, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Sato
  • Patent number: 8207567
    Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chi Chin, Ming-Chu King, Chen Cheng Chou
  • Patent number: 8198664
    Abstract: A semiconductor memory device including a plurality of supports extending parallel to each other in a first direction on a semiconductor substrate, and capacitor lower electrode rows including a plurality of capacitor lower electrodes arranged in a line along the first direction between two adjacent supports from among the plurality of supports, each capacitor lower electrode including outside walls, wherein each of the capacitor lower electrodes includes two support contact surfaces on the outside walls of the capacitor lower electrode, the support contact surfaces respectively contacting the two adjacent supports from among the plurality of supports.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gil-sub Kim
  • Patent number: 8198663
    Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
  • Patent number: 8188527
    Abstract: A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chyi Liu, Chi-Hsin Lo
  • Patent number: 8188528
    Abstract: A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: May 29, 2012
    Assignee: International Buiness Machines Corporation
    Inventors: Chengwen Pei, Kangguo Cheng, Herbert L. Ho, Subramanian S. Iyer, Byeong Y. Kim, Geng Wang, Huilong Zhu
  • Patent number: 8183614
    Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 22, 2012
    Assignee: Nanya Technology Corporation
    Inventor: Shin-Yu Nieh
  • Patent number: 8169013
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Publication number: 20120091520
    Abstract: A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 19, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Nobuyuki NAKAMURA
  • Publication number: 20120091519
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuo-Chi Tu
  • Patent number: 8159012
    Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
  • Patent number: 8148764
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee
  • Patent number: 8148223
    Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
  • Patent number: 8143699
    Abstract: An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Kuo-Chi Tu
  • Patent number: 8143659
    Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of the capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of trenches and the doped area for electrically insulating the trenches from the doped area. The doped area includes first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: March 27, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stefan Pompl
  • Patent number: 8138536
    Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: March 20, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Satoru Isogai, Takahiro Kumauchi
  • Patent number: 8129251
    Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Sun Seo
  • Patent number: 8129770
    Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeru Shiratake
  • Patent number: 8124978
    Abstract: A capacitor and method of manufacturing the same include an insulating interlayer, a lower electrode, a protection structure, a dielectric layer and an upper electrode. The insulating interlayer may include a conductive pattern formed on a substrate. The lower electrode may be electrically connected to the conductive pattern. The protection structure may be formed on an outer sidewall of the cylindrical lower electrode and on the insulating interlayer.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Young Kim, Rak-Hwan Kim, Young-Joo Cho, Won-sik Shin
  • Patent number: 8120006
    Abstract: Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, June-mo Koo, Tae-eung Yoon
  • Patent number: 8111113
    Abstract: A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: February 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert Charles Frye
  • Patent number: 8101985
    Abstract: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 24, 2012
    Assignee: Infineon Technologies AG
    Inventor: Matthias Hierlemann
  • Patent number: 8097910
    Abstract: The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8093642
    Abstract: A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: January 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 8093640
    Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 10, 2012
    Assignee: Atmel Corporation
    Inventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
  • Publication number: 20120001245
    Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kurt D. Beigel, Jigish D. Trivedi, Kevin G. Duesman
  • Patent number: 8084803
    Abstract: A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An oxide layer may be formed over the substrate, the oxide layer having an opening that exposes a portion of the high concentration diffusion junction region. A first polysilicon plate may be formed over a portion of the oxide layer and spaced from the opening, and a nitride layer may be formed over a portion of the first polysilicon plate. A sidewall may be formed over a side of the first polysilicon layer, over a side of the nitride layer, and over a portion of the oxide layer between the side of the polysilicon layer and the opening. A second polysilicon plate may be formed over the nitride layer, over the sidewall, and over the high concentration diffusion junction region.
    Type: Grant
    Filed: December 27, 2008
    Date of Patent: December 27, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam-Joo Kim
  • Patent number: 8076717
    Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Chandra Mouli, John K. Zahurak
  • Patent number: 8072024
    Abstract: A nonvolatile semiconductor memory device with a substrate. A plurality of dielectric films and electrode films are alternately stacked on the substrate and have a through hole penetrating in the stacking direction. A semiconductor pillar is formed inside the through hole. A charge storage layer is provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Ishikawa, Katsunori Yahashi
  • Patent number: 8067793
    Abstract: A method for manufacturing a semiconductor device with high response speed and high reliability. In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 8063404
    Abstract: A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 22, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Shing-Hwa Renn
  • Patent number: 8053824
    Abstract: Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom; and a second metal line electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers capacitively coupled. The basic structure of metal lines with interlocking metal fingers may be repeated on multiple adjacent metallization layers, with the metal lines oriented either in parallel or perpendicular.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: November 8, 2011
    Assignee: LSI Corporation
    Inventors: Greg Winn, Steve Howard
  • Patent number: 8053252
    Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
  • Patent number: 8039884
    Abstract: A semiconductor device includes: a ferroelectric capacitor including a first electrode provided above a substrate, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a hydrogen barrier film that covers a top surface and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the ferroelectric capacitor and the substrate; a contact hole that penetrates the interlayer dielectric film and the hydrogen barrier film and exposes the second electrode; a barrier metal that covers a top surface of the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier metal, wherein the inner wall surface of the contact hole at the hydrogen barrier film includes a concave curved surface facing the interior of the contact ho
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: October 18, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Takafumi Noda
  • Patent number: 8035141
    Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
  • Patent number: 8030697
    Abstract: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Hee Cho, Seung-Bae Park
  • Patent number: 8022457
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8018009
    Abstract: A movable substrate is placed over a bottom substrate where both substrates contain Coulomb islands. The Coulomb islands can be adjusted in charge and are used to develop a force between two opposing Coulomb islands. Information from sensors is applied to a control unit to control the movement of the movable substrate. Coulomb islands are formed in the juxtaposed edges of a first substrate and second substrate, respectively. The islands generate edge Coulomb forces. These edge Coulomb forces can be used to detach, repel, move, attract and reattach the edges of substrates into new configurations. One possibility is to combine a plurality of individual substrates into one large planar substrate.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 13, 2011
    Assignee: MetaMEMS Corp.
    Inventor: Thaddeus John Gabara
  • Patent number: 8017985
    Abstract: Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: September 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8013377
    Abstract: Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: September 6, 2011
    Assignee: Qimonda AG
    Inventors: Peter Baars, Stefan Tegen, Klaus Muemmler
  • Patent number: 8003462
    Abstract: A first electrode film containing TiAlN and a main dielectric film containing tantalum oxide are formed over a semiconductor substrate. Anneal is performed in the state that the first electrode film and the main dielectric film are formed, to react aluminum (Al) in the first electrode film with oxygen (O) in the main dielectric film and form a subsidiary dielectric film containing aluminum oxide at an interface between the first electrode film and the main dielectric film. A second electrode film is formed facing the first electrode film via the main dielectric film and the subsidiary dielectric film.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaaki Nakabayashi
  • Patent number: 7999300
    Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: August 16, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhao Lun, James Yong Meng Lee, Lee Wee Teo, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Shailendra Mishra, Jeffrey Chee
  • Patent number: 7999298
    Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Niloy Mukherjee, Gilbert Dewey, Dinesh Somasekhar, Brian S. Doyle
  • Patent number: 7999299
    Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwa Lee, Si-Woo Lee
  • Patent number: 7999297
    Abstract: A semiconductor device having transistors formed on different layers of a stack structure includes a stacked capacitor cluster, wherein a stacked capacitor of the stacked capacitor cluster includes an insulation layer of a transistor of the semiconductor device, and at least a first conduction layer and a second conduction layer disposed above and below the insulation layer, wherein the stacked capacitor is a decoupling capacitor of the stacked capacitor cluster connected in parallel between a first line and a second line.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyang-Ja Yang
  • Patent number: 7994560
    Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Christian Caillat, Richard Ferrant
  • Patent number: 7994557
    Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: August 9, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Gyu Baek, Moon-Sook Lee
  • Patent number: 7989864
    Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Garry A. Mercaldi, Michael Nuttall, Shenline Chen, Er-Xuan Ping
  • Patent number: 7985998
    Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: July 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shian-Jyh Lin, Ming-Cheng Chang, Neng Tai Shih, Hung-Chang Liao