Stacked Capacitor Patents (Class 257/303)
  • Patent number: 7977257
    Abstract: In a semiconductor device and a method of manufacturing a semiconductor device, a lower electrode is formed on a semiconductor substrate. A first zirconium oxide layer is formed on the lower electrode by performing a first deposition process using a first zirconium source and a first oxidizing gas. A zirconium carbo-oxynitride layer is formed on the first zirconium oxide layer by performing a second deposition process using a second zirconium source, a second oxidizing gas and a nitriding gas, and an upper electrode is formed on the zirconium carbo-oxynitride layer. A zirconium oxide-based composite layer having a high dielectric constant and a thin equivalent oxide thickness can be obtained.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Min-Woo Song, Pan-Kwi Park, Jung-Min Park
  • Patent number: 7977724
    Abstract: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction where the adjacent storage electrode is arranged. A dielectric layer is formed on the storage electrode. A plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park
  • Patent number: 7968929
    Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Eric Thompson
  • Patent number: 7960772
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: June 14, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 7960227
    Abstract: After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasuhiro Hayashi, Kazutoshi Izumi
  • Patent number: 7956399
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: June 7, 2011
    Assignee: NXP B.V.
    Inventors: Wibo Daniel Van Noort, Jan Sonsky, Philippe Meunier-Beillard, Erwin Hijzen
  • Patent number: 7956398
    Abstract: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: June 7, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Min Lee
  • Patent number: 7956440
    Abstract: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwan-Young Yun
  • Patent number: 7951665
    Abstract: A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Inoue, Tomoko Inoue
  • Patent number: 7943474
    Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Keith Kwong Hon Wong, Mahender Kumar
  • Patent number: 7939875
    Abstract: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: May 10, 2011
    Assignee: Au Optronics Corp.
    Inventors: Mao-Tsun Huang, Tzufong Huang
  • Patent number: 7939872
    Abstract: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Sang-Yeol Kang, Ki-Vin Lim, Hoon-Sang Choi, Eun-Ae Chung
  • Patent number: 7935998
    Abstract: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Publication number: 20110095349
    Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
    Type: Application
    Filed: December 21, 2010
    Publication date: April 28, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
  • Patent number: 7922113
    Abstract: In a fishing reel, the combination operable for braking the reel, comprising a reel spool having an axis, two axially spaced brake discs on the spool, a brake pad between the discs, and the discs interconnected to rotate together and move relatively toward the pad, a braking lever movable by the user to effect the disc relative movement, and pad engagement by the discs, a shaft extending axially, and bodily movable to effect the discs relative movement, the shaft being non-rotatable, and means including an actuator for displacing the shaft axially in response to lever movement, thereby to cause braking engagement of the discs, with the pad.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: April 12, 2011
    Inventor: Harout Alajajyan
  • Patent number: 7919802
    Abstract: A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer, in which the capacitor opening is situated directly above the first damascene conductor. Next, an MIM capacitor having a top plate and a bottom plate is created within the capacitor opening, in which the bottom plate of the MIM capacitor is electrically connected to the first damascene conductor. Next, a third dielectric layer is deposited on the second dielectric layer and the MIM capacitor, and at least one second damascene conductor is formed within part of the third dielectric layer, in which the second damascene conductor is electrically connected to the top plate of the MIM capacitor.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: April 5, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yi Lin, Chien-Chou Hung
  • Patent number: 7915172
    Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tetsuo Yaegashi
  • Patent number: 7911315
    Abstract: A pressure sensor assembly configured for use with a catheter. In one illustrative embodiment, the pressure sensor assembly may include a multi-layer co-fired ceramic (MLCC) package. The MLCC package may include two or more ceramic layers that are co-fired together, with a cavity defined by at least some of the ceramic layers. At least one internal bond pad is provided within the cavity, and at least one external connection point is provided on the MLCC package exterior. A sensor, such as a pressure sensor, may be positioned and attached within the cavity. The sensor may be electrically connected to at least one of the internal bond pads. In some cases, a sealant may be used to encapsulate the sensor within the cavity. Once fabricated, the MLCC sensor assembly may be provided in a sensor lumen of a catheter.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 22, 2011
    Assignee: Honeywell International Inc.
    Inventor: Alistair D. Bradley
  • Publication number: 20110057240
    Abstract: A semiconductor device includes a plurality of conduction plugs disposed on an active region, a bit line connected to a conduction plug of the plurality of conduction plugs which is disposed in a central portion of the active region, and storage nodes connected with conduction plugs of the plurality of conduction plugs which are disposed at both peripherals of the active region and passing over the active region.
    Type: Application
    Filed: June 25, 2010
    Publication date: March 10, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Hyung Jin Park
  • Publication number: 20110049600
    Abstract: In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.
    Type: Application
    Filed: July 14, 2010
    Publication date: March 3, 2011
    Inventor: Yasuyuki AOKI
  • Patent number: 7898014
    Abstract: Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Patent number: 7884409
    Abstract: A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hae Kim, Myoung-Hwan Oh, Myung-Soo Yeo, Hea-Yean Park
  • Patent number: 7880213
    Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Miao Lo, Lurng-Sheng Lee, Pei-Ren Jeng, Cha-Hsin Lin, Ching-Chiun Wang
  • Patent number: 7866015
    Abstract: Disclosed are embodiments of a method of forming a capacitor with inter-digitated vertical plates such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventor: Anil K. Chinthakindi
  • Patent number: 7863665
    Abstract: A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 4, 2011
    Assignee: Raytheon Company
    Inventors: Barry J. Liles, Colin S. Whelan
  • Patent number: 7863663
    Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: January 4, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan Doebler
  • Patent number: 7859825
    Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
  • Patent number: 7859081
    Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
  • Patent number: 7847330
    Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: December 7, 2010
    Inventors: Darrell Rinerson, Christophe Chevallier, Steve Kuo-Ren Hsia
  • Patent number: 7843035
    Abstract: An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: November 30, 2010
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
  • Publication number: 20100283093
    Abstract: A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 11, 2010
    Applicant: International Business Machines Corporation
    Inventors: Chengwen Pei, Kangguo Cheng, Herbert L. Ho, Subramanian S. Iyer, Byeong Y. Kim, Geng Wang, Huilong Zhu
  • Patent number: 7825451
    Abstract: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Patent number: 7825450
    Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Walker, Karl M. Robinson
  • Patent number: 7820506
    Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 26, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Noel Rocklein, Chris M. Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
  • Patent number: 7821047
    Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Ozaki
  • Patent number: 7816762
    Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Eric Thompson
  • Patent number: 7812387
    Abstract: A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 7808030
    Abstract: The electronic component includes a base material, a capacitor unit, and a wiring portion. The capacitor unit has a stacked structure including a first electrode portion provided on the base material, a second electrode portion including a first surface opposing the first electrode portion and a second surface opposite to the first surface, and a dielectric portion interposed between the electrode portions. The wiring portion includes a via portion having a surface on the base material side, and joined to the second surface of the second electrode portion via the surface on the base material side. The surface of the via portion on the base material side includes an extending portion extending outward of the periphery of the second surface of the second electrode portion.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: October 5, 2010
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Mizuno, Xiaoyu Mi, Tsuyoshi Matsumoto, Hisao Okuda, Satoshi Ueda
  • Patent number: 7799582
    Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
  • Patent number: 7795662
    Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideyuki Arai, Takashi Nakabayashi
  • Patent number: 7795660
    Abstract: A capacitor structure includes: a number of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and a dielectric surrounding the conductive regions.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: September 14, 2010
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Helmut Strack
  • Patent number: 7795661
    Abstract: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Jack A. Mandelman
  • Patent number: 7795657
    Abstract: A semiconductor memory device includes a memory cell portion, the memory cell portion including a ferroelectric capacitor and a memory cell transistor, the ferroelectric capacitor including a first electrode film on a semiconductor substrate, a second electrode film over the first electrode film, and a ferroelectric film between the first and second electrode films, and the memory cell transistor including a source and a drain between the first and second electrode films, wherein either the source or the drain connects to the first electrode film, and the other of the source or the drain connects to the second electrode film.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Hidaka
  • Patent number: 7791124
    Abstract: A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Geng Wang
  • Patent number: 7786520
    Abstract: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: August 31, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-young Lee, Il-young Yoon, Boung-ju Lee
  • Patent number: 7781820
    Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: August 24, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shigeru Sugioka
  • Patent number: 7768054
    Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 3, 2010
    Assignee: Infineon Technologies, AG
    Inventors: Thomas Benetik, Erwin Ruderer
  • Patent number: 7768051
    Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Todd R. Abbott
  • Publication number: 20100187587
    Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.
    Type: Application
    Filed: January 28, 2009
    Publication date: July 29, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Zhao LUN, James Yong Meng LEE, Lee Wee TEO, Shyue Seng TAN, Chung Woh LAI, Johnny WIDODO, Shailendra MISHRA, Jeffrey CHEE
  • Patent number: 7763923
    Abstract: A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 27, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Der-Chyang Yeh, Chie-Iuan Lin, Chuan-Ying Lee, Yi-Ting Chao, Ming-Hsien Chen