Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

Abstract: A linear capacitor design providing shielding on all sides of the linear capacitor. In one aspect the capacitor provides a signal side metal layer substantially enclosed by a dielectric material which is, in turn, substantially enclosed by an upper and lower metal shield layer. in another aspect, the upper and lower shield metal layers may be coupled by a plurality of vias. In another aspect, a plurality of alternating intermediate layers provide signal side metal and shield metal separated by dielectric material such that each signal side layer is substantially enclosed by one or more shield metal layers. In another aspect, multiple intermediate signal side metal layers are conductively coupled to one another by a plurality of vias and multiple shield metal layers are conductively coupled to one another by a plurality of vias.

Abstract: A ferroelectric capacitor including a bottom electrode which has a projecting portion, a top electrode, a ferroelectric layer and a dielectric layer formed between the bottom electrode and the top electrode. The dielectric layer is formed on a peripheral area of the bottom electrode. The ferroelectric layer is formed on the dielectric layer and on the projecting portion of the bottom electrode. As a result, a damaged layer which is formed during an etching process occurs at the ineffective area of the ferroelectric capacitor.

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: A semiconductor device includes a MOS transistor, interlayer dielectric film, first and second high-dielectric-constant films, and first and second conductive films. The MOS transistor is formed on a semiconductor substrate. The interlayer dielectric film is formed on the semiconductor substrate so as to cover the MOS transistor. The first high-dielectric-constant film is formed on the interlayer dielectric film and has an opening portion that reaches the interlayer dielectric film. The first conductive film contains a metal element and is formed to be partially embedded in the opening portion. The second high-dielectric-constant film is formed on the first conductive film. The second conductive film is formed on the second high-dielectric-constant film.

Abstract: A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.

Abstract: The present invention relates to a capacitor of a semiconductor memory cell and a method of manufacturing the same wherein a capacitor includes a first insulation layer having a buried contact hole, formed on a semiconductor substrate, and a buried contact plug filling a portion of the buried contact hole. A diffusion barrier spacer is formed on an inner surface of the buried contact hole above the buried contact plug. A second insulation layer is formed, having a through hole larger than the buried contact hole, for exposing the diffusion barrier spacer and a top surface of the contact plug. A barrier layer is formed on the through hole and a lower electrode is formed on the barrier layer. A dielectric layer is formed on the lower electrode and an upper surface of the second insulation layer and an upper electrode is formed on the dielectric layer.

Abstract: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.

Abstract: The present invention disclosed a silicon barrier capacitor device structure. By applying CVD or PVD technologies to deposit poly-silicon layers as the dielectric of capacitor on the doping region of the wafer, then implant a high-density (1016˜1021/cm3) impurity of the group III or group V elements and oxygen ion or nitrogen ion to the poly-silicon layer. After implantation, deposit a low resistance and high melting point conductor on the poly-silicon layer for the electrode. to form a capacitor structure, or repeat all of the deposition poly-silicon and both of the low resistance and high melting point conductor on the poly-silicon layer more than once. All of the odd electrodes are connected together. The even electrodes and the substrate are connected together, too. At last, apply high temperature furnace annealing to the devices. The grain boundary of the silicon was oxidized by oxygen and nitrogen to form an isolation film to be the insulation film.

Abstract: A method used during the formation of a semiconductor device comprises forming a first portion of a digit line contact plug before forming storage capacitors. Subsequent to forming storage capacitors, a second portion of the digit line plug is formed to contact the first portion, then the digit line runner is formed to contact the second plug portion. A structure resulting from the process is also described.

Abstract: A FeRAM device in which a bottom electrode of a ferroelectric capacitor is connected to a source/drain region of a transistor and a top electrode is connected to a plate line. The FeRAM device comprises a semiconductor substrate; a gate electrode formed on the semiconductor substrate; an impurity region formed on each side of the gate electrode of the semiconductor substrate; a bottom electrode connected to the impurity region; an oxygen diffusion barrier layer formed on the bottom electrode; a ferroelectric layer formed on the oxygen diffusion barrier layer and the bottom electrode; and a top electrode formed on the ferroelectric layer.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

Abstract: A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein 1) a first metal layer of an anodizable metal is deposited on a substrate; 2) the exposed surface of the anodizable metal layer is anodized to produce an oxide layer, 3) a second metal layer of electrically conductive metal is provided on the oxide layer, and 4) the first metal layer is etched to form an electrically resistive conductive path electrically connected to the region f the first metal layer beneath the second metal layer. A thin-film RC circuit element is also provided having a first layer of an anodizable metal formed on an electrically insulating substrate so as to provide two capacitor plates connected by a resistive strip, an oxide layer formed on the capacitor plates, and upper capacitor plates positioned on the oxide layer in register with the lower capacitor plates.

Abstract: A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.

Abstract: A capacitor includes an array of first conductive units and an array of second conductive units. Each of the first conductive units includes a hollow first conductive post that has lateral sides. The first conductive posts of the first conductive units are interconnected to form a grid that defines a plurality of lattices. Each of the second conductive units includes a second conductive post that is disposed in a respective one of the lattices and that has lateral sides that are surrounded by the lateral sides of the first conductive post of a respective one of the first conductive units. The first conductive post of each of the first conductive units and the second conductive post of the respective one of the second conductive units cooperatively define a charge space. A dielectric material fills the charge space.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second metal wiring layer are sequentially connected. And within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C. When manufacturing the semiconductor device, the second layer-insulating layer is formed in such a way as to cover the metal wiring layer on the first layer-insulating layer. Removal is performed of at least respective parts, corresponding to a memory cell portion, of the first and the second layer-insulating layers. Thereafter, the capacitive element C is formed in regions corresponding to the removed portions of the first and the second layer-insulating layer.

Abstract: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semiconductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.

Abstract: A image detector comprises a light source for radiating light in accordance with a predetermined signal; a window for transmitting the light from the light source; a thin film phototransistor for generating an optical current in accordance with the intensity of external light; a storage capacitor for storing charge information transmitted from the thin film phototransistor; a thin film switching transistor for outputting the information stored in the storage capacitor in accordance with an external control signal; an insulating layer for covering the window, the thin film phototransistor, the storage capacitor, and the thin film switching transistor; a protecting layer formed on the insulating layer; and a conductive object detection pattern formed on the protecting layer to apply an electrical power supply signal to the light source when a conductive living object contacts the conductive objecting detecting pattern.

Abstract: A semiconductor device is obtained that can prevent occurrence of a shape defect of a capacitor electrode in the semiconductor device or operation failure of the semiconductor device. A semiconductor device with the capacitor includes a second interlayer insulation film, an SC poly plug, a barrier metal and an SN electrode. The second interlayer insulation film has a through hole. The SC poly plug is formed within the through hole of the second interlayer insulation film. The barrier metal is formed on the SC poly plug. The SN electrode is formed on the barrier metal. The SN electrode is electrically connected to the SC poly plug with the barrier metal interposed therebetween. The barrier metal is a multilayer film including three layers of a tantalum nitride (TaN) film, a titanium nitride (TiN) film and a titanium (Ti) film.

Abstract: A metal-over-metal (MOM) device and the method for manufacturing same is provided. The device has at least one device cell on a first layer comprising a frame piece and a center piece surrounded by the frame piece. The center piece has a cross-shape center portion defining four quadrants of space between the frame and center pieces. The center piece has one or more center fingers each extending from at least one of the four ends thereof within a quadrant. The frame piece also has one or more frame fingers extending therefrom, each being in at least one quadrant and not being overlapped with the center finger in the same quadrant.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: A storage capacitor structure of a planar display is disclosed. The storage capacitor includes a substrate, a bottom electrode, an insulator, and a top electrode. The bottom electrode or top electrode has an uneven surface toward the insulator interposed between the two electrodes in order to increase the capacitance of the storage capacitor structure. A method for fabricating such storage capacitor structure is also disclosed. It includes steps of providing a substrate; and forming a bottom electrode, an insulator, and a top electrode in sequence. The bottom electrode or the top electrode has the uneven surface by an etching step.

Abstract: The present invention relates to a capacitor of a semiconductor memory cell and a method of manufacturing the same wherein a capacitor includes a first insulation layer having a buried contact hole, formed on a semiconductor substrate, and a buried contact plug filling a portion of the buried contact hole. A diffusion barrier spacer is formed on an inner surface of the buried contact hole above the buried contact plug. A second insulation layer is formed, having a through hole larger than the buried contact hole, for exposing the diffusion barrier spacer and a top surface of the contact plug. A barrier layer is formed on the through hole and a lower electrode is formed on the barrier layer. A dielectric layer is formed on the lower electrode and an upper surface of the second insulation layer and an upper electrode is formed on the dielectric layer.

Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.

Abstract: In an electrode for an electric double layer capacitor of the present invention, the peak value of particle size distribution of graphite particles added to a conductive adhesive is in a range of 2.6 to 3.2 ?m, not less than 100,000 dimples having a largest outer diameter in a range of 4 to 10 ?m and a depth in a range of 4 to 15 ?m are formed on the surface of the collector sheet per 1 cm2, and the occupied area of the dimples to the entire surface area of the collector sheet is not more than 50%. By determining the saponification value of polyvinylalcohol which is used as a binder component of the conductive adhesive in a range of 90.0 to 98.5, adhesiveness of the collector sheet and the electrode forming sheet is improved. Furthermore, by substituting H atoms contained in the polyvinylalcohol with Si atoms, adhesiveness of the collector sheet and the electrode forming sheet can be further improved.

Abstract: Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at least one freestanding storage node electrode, to thereby reduce or prevent the storage node electrode from falling or bending towards an adjacent storage node electrode.

Abstract: A power divider having metal capacitors is disclosed to detect and divide a frequency signal. The divide includes a first capacitor including first and second electrodes formed at a first portion of a substrate, a second capacitor including first and second electrodes formed at a second portion of the substrate, a first metal line connected to the second electrode of the first capacitor, a second metal line connected to the second electrode of the second capacitor, a poly resistor connected to a contact area of the first capacitor and to a contact area of the second capacitor, and a third metal line connected to the first and second metal lines to divide a signal flown through the first and second metal lines.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A semiconductor device without any peel off from the insulation film and without any fracture that becomes the cause of a short circuit is obtained even if a metal such as Ru is employed for the storage node. On the semiconductor substrate are provided an underlying interlayer insulation film located over both a capacitor region and a peripheral region, an interlayer insulation film located above the underlying interlayer insulation film, and a tubular metal film having a bottom end portion in contact with the underlying interlayer insulation film, and piercing the interlayer insulation film with the opening side located at the upper side in the capacitor region and the peripheral region. The opening side of the tubular metal film is formed only of a portion extending along the sidewall of a throughhole in the interlayer insulation film.

Abstract: An interdigital capacitor includes a semiconductor substrate, and a pair of comb-like electrodes formed on the semiconductor substrate. At least one of the pair of comb-like electrodes includes a cutting target portion.

Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

Abstract: A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: Methods are provided for forming a transistor for use in an active matrix liquid crystal display (AMLCD). In one aspect a method is provided for processing a substrate including providing a glass substrate, depositing a conductive seed layer on a surface of the glass substrate, depositing a resist material on the conductive seed layer, patterning the resist layer to expose portions of the conductive seed layer, and depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique.

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Abstract: A semiconductor device having an analog capacitor and a method of fabricating the same are disclosed. The semiconductor device includes a bottom plate electrode disposed at a predetermined region of a semiconductor substrate, and an upper plate electrode having a region overlapped with the bottom plate electrode thereon. The upper plate electrode and the bottom plate electrode are formed of a metal compound. A capacitor dielectric layer is interposed between the bottom plate electrode and the upper plate electrode. A bottom electrode plug and an upper electrode plug are connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer.

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: On a semiconductor substrate, a transistor and a capacitor electrically connected to the transistor are formed, the capacitor having two electrodes made of metal and a capacitor dielectric layer between the two electrodes made of oxide dielectric material. A temporary protective film is formed over the capacitor, the temporary protective film covering the capacitor. The semiconductor substrate with the temporary protective film is subjected to a heat treatment in a reducing atmosphere. The temporary protective film is removed. The semiconductor substrate with the temporary protective film removed is subjected to a heat treatment in an inert gas atmosphere or in a vacuum state. A protective film is formed over the capacitor, the protective film covering the capacitor. With these processes, leak current of the capacitor can be reduced.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Abstract: A semiconductor device includes an IC chip, a frame on which the IC chip is mounted, a conductive plate disposed beneath and spaced from the frame, a first external terminal and a second external terminal that electrically connect the IC chip, the frame, and the conductive plate, and a molding compound covering and encapsulating the IC chip, the frame, and the conductive plate.