Abstract: A flexible scheme for forming a multi-layer capacitor structure is provided. The multi-layer capacitor structure includes a first electrode and a second electrode extending through at least one metallization layer, wherein the first electrode and the second electrode are separated by dielectric materials. In each of the metallization layers, the first electrode comprises a first bus and first fingers connected to the first bus, wherein the first bus comprises a first leg in a first direction, and wherein the first fingers are parallel to each other and are in a second direction. The first direction and the second direction form an acute angle. In each of the metallization layers, the second electrode comprises a second bus and second fingers connected to the second bus, wherein the second fingers are parallel to the first fingers in a same metallization layer.

Abstract: An interdigitized capacitor comprising first and second electrodes. The first electrode comprises two combs symmetrical to a first mirror plane. The fingers of the combs extend toward the first mirror plane. The second electrode comprises two combs and a linear plate. The combs are symmetrical to a second mirror plane and the fingers thereof extend toward the second mirror plane. The linear plate is located at the second mirror plane and connected to one finger of the combs of the second electrode. The first and second mirror planes are orthogonal. The fingers of the combs of the first and second electrodes are interdigitized.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract: A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Abstract: A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or hysteretic-resistor memory cells. Each tree structure corresponds to a bit line, has a trunk portion and at least one branch portion. The trunk portion of each tree structure extends from a corresponding bit line, and each tree structure corresponds to a plurality of layers. Each branch portion corresponds to at least one layer and extends from the trunk portion of a tree structure. Plate lines correspond to at least one layer and overlap the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions.

Abstract: A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.

Abstract: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.

Abstract: The apparatus for working and observing samples comprises a sample plate on which a sample is to be placed; a first ion beam lens barrel capable of irradiating a first ion beam over a whole predetermined irradiation range at one time; a mask that can be arranged between the sample plate and the first ion beam lens barrel, and shields part of the first ion beam; mask-moving means capable of moving the mask; a charged particle beam lens barrel capable of scanning a focused beam of charged particles in the range irradiated with the first ion beam; and detection means capable of detecting a secondarily generated substance.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.

Abstract: In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.

Abstract: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.

Abstract: A semiconductor device with a capacitor includes a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer including more than one polycrystalline tantalum oxide layer and more than one separation layer, wherein the polycrystalline tantalum oxide layers and the separation layers are alternately stacked, while one of the polycrystalline tantalum oxide layers is a lowermost layer among the stacked layers.

Abstract: A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer, and a second conductive layer formed on the first dielectric layer. The second conductive layer is coupled to the polysilicon layer.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.

Abstract: A semiconductor device having a capacitor including a first electrode, a second electrode and an insulator. The semiconductor device includes first layers and second layers laminated alternately. The first layers each includes lines of the first electrode and lines of the second electrode arranged alternately and extending in a first direction. The second layers each including lines of the first electrode and lines of the second electrode arranged alternately and extending in a second direction. First via holes connect the lines of the first electrode in each of the first layers and lines of the first electrode in each of the second layers. Second via holes connect the lines of the second electrode in each of the first layers and the lines of the second electrode in each of the second layers.

Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.

Abstract: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

Abstract: A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer includes a plurality of grid units arranged in a matrix, where in odd rows of the matrix, a first conductive grid is located in each odd column, and a first circular hole is located in each even column. Additionally, a first conductive island is located within each first circular hole. The pattern of the second conductive grids, the second circular holes, and the second conductive island of the second conductive layer is mismatched with that of the first conductive layer. The plug layer has a plurality of plugs disposed in between each first conductive island and each second conductive grid, and in between each first conductive grid and each second conductive island.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: The present invention relates to a device with integrated capacitance structure has at least one first and an adjacent second rewiring plane, each of which comprises at least one first partial structure and a second partial structure, which is different from the first partial structure, the second partial structure in each case substantially surrounding the first partial structure, and the first partial structure of the first rewiring plane being electrically connected to the second partial structure of the second rewiring plane and the second partial structure of the first rewiring plane being electrically connected to the first partial structure of the second rewiring plane and forming different poles of the capacitance structure.

Abstract: A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.

Abstract: Semiconductor devices are provided with double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, container capacitors for a semiconductor device have a cup-shaped bottom electrode with an interior surface including HSG polysilicon and an exterior surface including smooth polysilicon. A barrier layer may be formed within the container that defines the container capacitor.

Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: An electronic component and method of production thereof is presented. The electronic component includes a first insulation layer, an upper metal layer on the first insulation layer, an electrically conductive structure integrated into the first insulation layer and formed as a capacitor with a first metal strip sequence, and a second metal strip sequence. Each of the first and second sequences are arranged congruently one above another and are connected to one another by via connections. The second sequence is arranged on both sides of the first sequence at identical lateral distances. The metal strips of the first and second sequences are arranged at the same level and are connected to different electrical potentials. The electrically conductive structure mechanically stabilizes the insulation layer under the action of mechanical force such as bonding of the upper metal layer or mounting of the electronic component.

Abstract: A ferroelectric memory device includes a first bit line, a second bit line provided adjacent to the first bit line, a first memory cell block including a first terminal, a second terminal, and a plurality of memory cells connected in series between the first and second terminals and arranged in a first direction along the first bit line connected to the first terminal by a first block select transistor, a second memory cell block including a plurality of memory cells, and a plurality of first contacts arranged between the first and second memory cell blocks, each first contact connecting the upper electrode and drain or source electrode of one memory cell.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second electrode, and a second dielectric film provided between the second electrode and the third electrode, an insulating film covering the capacitor structure and having a first hole reaching the first electrode, a second hole reaching the second electrode, and a third hole reaching the third electrode, a first conductive connection electrically connecting the first electrode and the third electrode and having portions buried in the first and third holes, and a second conductive connection formed-separately from the first conductive connection and having a portion buried in the second hole.

Abstract: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.