With High Dielectric Constant Insulator (e.g., Ta 2 O 5 ) Patents (Class 257/310)
  • SEMICONDUCTOR DEVICE
    Publication number: 20130049091
    Abstract: A semiconductor device comprises an MIS field effect transistor including a channel region made of p-conductive silicon, a gate insulating film including a first insulating film having dielectric constant higher than dielectric constant of silicon dioxide, and a gate electrode. The gate electrode includes a first metal film formed on the gate insulating film and having a work function greater than a work function of intrinsic semiconductor silicon, and a p-conductive silicon film formed on the first metal film and in contact with the first metal film.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 28, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kanta SAINO
  • Semiconductor device and manufacturing method therefor
    Patent number: 8384143
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Semiconductor device and manufacturing method thereof
    Patent number: 8367428
    Abstract: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 5, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Nonvolatile memory device and method for fabricating the same
    Patent number: 8368134
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 5, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8361854
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy
    Patent number: 8349694
    Abstract: When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Martin Gerhardt
  • Semiconductor device and method for manufacturing the same
    Patent number: 8343830
    Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same
    Patent number: 8344439
    Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Young-sun Kim, Se-hoon Oh
  • Laminated thin-film device, manufacturing method thereof, and circuit
    Patent number: 8344386
    Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Integrated semiconductor structure for SRAM and fabrication methods thereof
    Patent number: 8330227
    Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
  • METHOD OF DEPOSITING GATE DIELECTRIC, METHOD OF PREPARING MIS CAPACITOR, AND MIS CAPACITOR
    Publication number: 20120273861
    Abstract: The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared.
    Type: Application
    Filed: June 8, 2011
    Publication date: November 1, 2012
    Applicant: SHANGHAN INSTITUTE OF MICROSYSTEM AND IMFORMATION TECHNOLOGY,CHINESE ACADEM
    Inventors: Xinhong Cheng, Dawei Xu, Zhongjian Wang, Chao Xia, Dawei He, Zhaorui Song, Yuehui Yu
  • Erasable non-volatile memory device using hole trapping in high-K dielectrics
    Patent number: 8294196
    Abstract: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Integrated circuit with replacement metal gates and dual dielectrics
    Patent number: 8288296
    Abstract: A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Kangguo Cheng, Dechao Guo, Pranita Kulkarni
  • Zirconium-doped tantalum oxide films
    Patent number: 8288809
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Non-volatile memory devices having data storage layer
    Patent number: 8283711
    Abstract: Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-gu Jin, Yoon-dong Park, Won-joo Kim, Seung-hoon Lee, Suk-pil Kim
  • Semiconductor memory device and method of manufacturing the same
    Patent number: 8273652
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contact plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: September 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Min Kim
  • High-k metal gate device
    Patent number: 8258546
    Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
  • Semiconductor device
    Patent number: 8253180
    Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
  • Capacitor, method of producing the same, semiconductor device, and liquid crystal display device
    Patent number: 8237242
    Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: August 7, 2012
    Assignee: Sony Corporation
    Inventors: Kiwamu Adachi, Satoshi Horiuchi
  • Semiconductor device and its manufacturing method
    Patent number: 8222683
    Abstract: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: July 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshimasa Horii
  • Semiconductor device and method of fabricating the same
    Patent number: 8217440
    Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaihsa Toshiba
    Inventor: Yoshinori Tsuchiya
  • Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
    Patent number: 8212299
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1?x)O2(0<x<1), (Zry, Ti1?y)O2(0<y<1), (Hfz, Ti1?z)O2(0<z<1), (Zrk,Til, Hfm)O2(0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Capacitor and method for fabricating the same
    Patent number: 8212301
    Abstract: A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer. The third dielectric layer can be thicker than the first dielectric layer.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: July 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Semiconductor devices including dual gate structures
    Patent number: 8207582
    Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Method for manufacturing a resistive switching memory device and devices obtained thereof
    Patent number: 8206995
    Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 26, 2012
    Assignee: IMEC
    Inventors: Judit Gloria Lisoni Reyes, Ludovic Goux, Dirk Wouters
  • Dielectric, capacitor using dielectric, semiconductor device using dielectric, and manufacturing method of dielectric
    Patent number: 8203176
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Multi-layer gate dielectric
    Patent number: 8193593
    Abstract: A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventor: Gang Bai
  • Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT
    Patent number: 8183630
    Abstract: A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Commissariat A L'Energie Atomique
    Inventors: Perrine Batude, Laurent Clavelier, Marie-Anne Jaud, Olivier Thomas, Maud Vinet
  • Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same
    Patent number: 8178404
    Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: May 15, 2012
    Assignee: NXP B.V.
    Inventors: Michael Olewine, Kevin Saiz
  • Interfacial barrier for work function modification of high performance CMOS devices
    Patent number: 8178939
    Abstract: A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.
    Type: Grant
    Filed: June 21, 2009
    Date of Patent: May 15, 2012
    Assignee: Sematech, Inc.
    Inventors: Wei-Yip Loh, Prashant Majhi, Brian Coss
  • Semiconductor device and manufacturing method therefor
    Patent number: 8169015
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 1, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0
    Patent number: 8169013
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Capacitor of a semiconductor device
    Patent number: 8159016
    Abstract: A capacitor of a semiconductor device, and a method of manufacturing the capacitor of the semiconductor device, include a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein the dielectric layer includes tantalum (Ta) oxide and an oxide of a Group 5 element, such as niobium (Nb) or vanadium (V).
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Park, Jung-hyun Lee
  • Titanium aluminum oxide films
    Patent number: 8154066
    Abstract: A dielectric layer containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a titanium aluminum oxide film.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Resistive random access memory
    Patent number: 8148765
    Abstract: A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure. The resistance of the oxidation structure can be changed by an electric field.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jun Shim, Han-Sin Lee, In-Gyu Baek, Jinshi Zhao, Eun-Kyung Yim
  • Methods of fabricating high-k metal gate devices
    Patent number: 8148249
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu-Chao Lin
  • Method for manufacturing oxide film having high dielectric constant, capacitor having dielectric film formed using the method, and method for manufacturing the same
    Patent number: 8143660
    Abstract: Provided are a method for manufacturing a high k-dielectric oxide film, a capacitor having a dielectric film formed using the method, and a method for manufacturing the capacitor. A high k-dielectric oxide film is manufactured by (a) loading a semiconductor substrate in an ALD apparatus, (b) depositing a reaction material having a predetermined composition rate of a first element and a second element on the semiconductor substrate, and (c) forming a first high k-dielectric oxide film having the two elements on the semiconductor substrate by oxidizing the reaction material such that the first element and the second element are simultaneously oxidized. In this method, the size of an apparatus is reduced, productivity is enhanced, and manufacturing costs are lowered. Further, the high k-dielectric oxide film exhibits high dielectric constant and low leakage current and trap density.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Burn-seok Seo, Yo-sep Min, Young-jin Cho
  • Memory cells, memory cell constructions, and memory cell programming methods
    Patent number: 8134194
    Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode including metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Ferro-electric device and modulatable injection barrier
    Patent number: 8120084
    Abstract: Described is a modulatable injection barrier and a semiconductor element comprising same. More particularly, the invention relates to a two-terminal, non-volatile programmable resistor. Such a resistor can be applied in non-volatile memory devices, and as an active switch e.g. in displays. The device comprises, in between electrode layers, a storage layer comprising a blend of a ferro-electric material and a semiconductor material. Preferably both materials in the blend are polymers.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: February 21, 2012
    Assignee: Rijksuniversiteit Groningen
    Inventors: Paulus Wilhelmus Maria Blom, Bert de Boer, Kamal Asadi
  • Ferroelectric capacitor with underlying conductive film
    Patent number: 8120087
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Semiconductor device and method for manufacturing the same
    Patent number: 8115261
    Abstract: It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81?x?0.99, 0.04?y?0.25, 0?z?1) on a semiconductor substrate, the ranges of composition ratios x, y, and z being values measured by XPS; and transforming the amorphous film into an insulating film containing (HfzZr1-z)xSi1-xO2 as tetragonal crystals, by performing annealing at 750° C. or higher on the amorphous film in an atmosphere containing oxygen.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: February 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Yasushi Nakasaki
  • MIM capacitor high-k dielectric for increased capacitance density
    Patent number: 8110861
    Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.
    Type: Grant
    Filed: April 3, 2010
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hadi H Abdul-Ridha, David J. Howard
  • Semiconductor device and manufacturing method thereof
    Patent number: 8110411
    Abstract: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: February 7, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Stud capacitor device and fabrication method
    Patent number: 8106438
    Abstract: The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Guy Blalock, Scott Meikle
  • Selective high-k dielectric film deposition for semiconductor device
    Patent number: 8106440
    Abstract: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Marko Radosavljevic, Mantu K. Hudait, Matthew V Metz
  • Charge trapping devices with field distribution layer over tunneling barrier
    Patent number: 8101989
    Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: January 24, 2012
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Method of forming capacitors
    Patent number: 8088659
    Abstract: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jiong-Ping Lu, Ming-Jang Hwang
  • Damascene metal-insulator-metal (MIM) device
    Patent number: 8089113
    Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 3, 2012
    Assignee: Spansion LLC
    Inventors: Suzette K. Pangrle, Steven Avanzino, Sameer Haddad, Michael VanBuskirk, Manuj Rathor, James Xie, Kevin Song, Christie Marrian, Bryan Choo, Fei Wang, Jeffrey A. Shields
  • Capacitor with zirconium oxide and method for fabricating the same
    Patent number: 8084804
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: December 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-jeung Lee
  • Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices
    Patent number: RE43673
    Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen