Plural Additional Contacted Control Electrodes Patents (Class 257/319)
  • Patent number: 10522560
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source line formed over a substrate. The semiconductor device may include a channel pattern including a connection part disposed over the source line, and pillar parts protruding from the connection part in a first direction. The semiconductor device may include a well structure protruding from the connection part in the first direction and spaced apart from the source line. The semiconductor device may include a source contact structure protruding from the source line in the first direction and passing through the connection part. The semiconductor device may include a gate stack disposed between the source contact structure and the well structure and enclosing the pillar parts over the connection part.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10504914
    Abstract: An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: December 10, 2019
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10418377
    Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: September 17, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Pieter Blomme
  • Patent number: 10410915
    Abstract: A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contact
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 10403637
    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10290651
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 10283515
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. A gate length in a first direction of a floating gate positioned between one of the electrode layers and the semiconductor layer is longer than a layer thickness in the first direction of the one of the electrode layers. A ratio of the layer thickness of the one of the electrode layers to the gate length has a positive correlation with an outer diameter of a first portion of the semiconductor layer surrounded by the floating gate in a second direction from the semiconductor layer toward the one of the electrode layers.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Yasuda
  • Patent number: 10229923
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Patent number: 10224337
    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
  • Patent number: 10050055
    Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Shimura
  • Patent number: 9966353
    Abstract: An elongated trench (35) is formed so as to connect the Ag layer (32) and the exposed part of the circuit layer stretching out around the Ag layer (32). The trench (35) a narrow and elongated recessed part penetrating the glass layer (31) and the aluminum oxide film (12A) from the Ag layer (32) to reach the surface (12a) of the circuit layer (2). The extended part (36), which is a part of the Ag layer (32) flatted along with the inner surface (35a) of the trench (35), is formed in the trench (35). The Ag layer (32) and the circuit layer (12) are electrically connected directly by Ag with a low electric resistance value by the extended part (36) in the portion where the trench (35) is formed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 8, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shuji Nishimoto, Yoshiyuki Nagatomo
  • Patent number: 9966384
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 9960178
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kawai, Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 9947683
    Abstract: According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars are provided within the structural body extending along the first direction. A first distance between the first pillar and the first interconnection is greater than a second distance between the third pillar and the third interconnection. The first distance is greater than a third distance between the fourth pillar and the fourth interconnection. A fourth distance between the second pillar and the second interconnection is greater than the second distance. The fourth distance is greater than the third distance.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiro Shimojo
  • Patent number: 9941293
    Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Jayavel Pachamuthu, Yingda Dong
  • Patent number: 9935121
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Konagai, Yoshihiro Akutsu, Masaru Kito
  • Patent number: 9923556
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 20, 2018
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 9893076
    Abstract: A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer connection bit line and a substrate which includes one or more elevated source regions disposed on at least one side of each row of NAND flash strings so that each NAND flash string includes a lower select transistor with a first channel portion that runs perpendicular to the surface of the substrate through a vertical channel string body, a second channel portion that runs parallel to the surface of the substrate, and a third channel portion that runs perpendicular to the surface of the substrate through the elevated source region.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 13, 2018
    Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9876027
    Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 23, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Hiroyuki Ogawa
  • Patent number: 9853038
    Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. The support openings are laterally expanded by laterally recessing the insulating layers with respect to the sacrificial material layers. The laterally expanded support openings are filled with a combination of a dielectric material and a sacrificial fill material to form support pillar structures. After forming memory films and channels in the memory openings, the sacrificial material layers are replaced with electrically conductive layers while the support pillar structures provide structural support to the insulating layers. The sacrificial fill material is replaced with contact via structures to form integrated support and contact structures.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 26, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Zhixin Cui
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Patent number: 9831257
    Abstract: A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by insulating strips. Data storage structures including floating gates are disposed along the conductive strips in the stacks. Vertical channel films are disposed on sidewalls of the stacks. Memory cells in the plurality of memory cells have channels in the vertical channel films, and control gates in the conductive strips. A tunnel oxide layer is disposed between the vertical channel films and the floating gates. The floating gates can be coplanar with conductive strips in the plurality of stacks, or be disposed between the conductive strips in the plurality of stacks.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 9812211
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Patent number: 9786613
    Abstract: Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Michael A. Stuber
  • Patent number: 9761527
    Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Patent number: 9754953
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 9748265
    Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 29, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Changhyun Lee
  • Patent number: 9704801
    Abstract: A semiconductor memory device includes first and second stacked bodies and a conductive body. The first and second stacked bodies are disposed side by side on the conductive layer. The conductive body is provided between the first and second stacked bodies. The first and second stacked bodies each includes a plurality of electrode layers stacked on the conductive layer, a first insulating layer between adjacent electrode layers, a second insulating layer including a first portion and a second portion, and a semiconductor layer extending through the plurality of electrode layers. The first portion is provided between the first insulating layer and one of the adjacent electrode layers. The second portion is separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body. The second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Masaru Kito, Toshiya Nakamori
  • Patent number: 9698022
    Abstract: Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventor: Randy J. Koval
  • Patent number: 9685454
    Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 20, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani
  • Patent number: 9666279
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: June 26, 2016
    Date of Patent: May 30, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9613981
    Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 4, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 9595531
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Gordon A Haller, Fatma A Simsek-Ege
  • Patent number: 9583539
    Abstract: A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Seje Takaki
  • Patent number: 9583423
    Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 9553100
    Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 24, 2017
    Assignee: SANDISK TECHOLOGIES LLC
    Inventors: Hiroyuki Kamiya, Kensuke Yamaguchi
  • Patent number: 9548312
    Abstract: A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Alexander Ebermann, Martin Schulze
  • Patent number: 9508732
    Abstract: In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hun Lee, Ki-Yong Kim, Sung-Wook Park, Gyu-Yeol Lee
  • Patent number: 9472665
    Abstract: A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Patent number: 9449983
    Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Hiroyuki Ogawa
  • Patent number: 9443862
    Abstract: A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Dai Iwata, Yusuke Yoshida, Kazutaka Yoshizawa
  • Patent number: 9431344
    Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 30, 2016
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Patent number: 9425209
    Abstract: An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory cells having horizontal lines and being intersected by vertical lines coupled to corresponding memory cells. Levels include contact pads communicating with horizontal lines for a given block. The global lines include connectors. Connectors coupled to given global lines are coupled to landing areas on corresponding contact pads of the blocks. The blocks include first and second blocks disposed so that a first set of the contact pads associated with the first block are next to a second set of contact pads associated with the second block. The landing areas of the contact pads of the first and second blocks are mirror image surfaces of one another. The horizontal lines can be bit lines and the vertical lines can be word lines.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 23, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Cheng Yang, Lo-Yuen Lin, Yu-Wei Jiang
  • Patent number: 9385227
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 5, 2016
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 9343322
    Abstract: A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT) so that the stacks have non-simple spatial periods on a line through the alternating active strips and insulating strips. A plurality of conductive lines are arranged orthogonally over, and have surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the active strips in the stacks and the conductive lines. Memory elements are disposed in the interface regions, which establish a 3D array of memory cells accessible via the plurality of active strips and the plurality of conductive lines. The insulating strips in the stacks can include a first group of strips having a first EOT and a second group of strips having a second EOT that is greater than the first EOT.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 9331093
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 3, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Peter Rabkin, Jayavel Pachamuthu
  • Patent number: 9305938
    Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson
  • Patent number: 9305933
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jaegoo Lee
  • Patent number: 9257570
    Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a plurality of first electrodes provided on the first insulating film, a second insulating film provided on a side surface of the first electrodes and on an upper surface of the first electrodes, and a second electrode insulated from the first electrodes by the second insulating film. The second electrode includes an interconnect portion provided on the second insulating film, and a downward-extending portion extending into a space between the first electrodes from the interconnect portion. A lower end portion of the downward-extending portion is not covered with the second insulating film.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Sato, Hiroaki Naito, Satoshi Nagashima
  • Patent number: 9236117
    Abstract: A semiconductor memory device includes a pipe channel layer formed on a semiconductor substrate, a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer, first conductive layers stacked while surrounding the first channel layer, second conductive layers stacked while surrounding the second channel layer, and third conductive layers stacked while surrounding the third channel layer, wherein the first to third conductive layers are separately controlled.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventor: Wan Cheul Shin