Plural Additional Contacted Control Electrodes Patents (Class 257/319)
  • Patent number: 11488962
    Abstract: The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11469110
    Abstract: Cyclic etch methods comprise the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula CxHyFz where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front; and iii) repeating the steps of i) and ii) until the SiN layer on the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 11, 2022
    Assignee: American Air Liquide, Inc.
    Inventors: Xiangyu Guo, James Royer, Venkateswara R. Pallem, Nathan Stafford
  • Patent number: 11398486
    Abstract: Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Patent number: 11373698
    Abstract: A semiconductor device includes a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Tae-Yong Lee
  • Patent number: 11315941
    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
  • Patent number: 11289506
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 29, 2022
    Assignee: Kioxia Corporation
    Inventor: Mitsuhiro Omura
  • Patent number: 11205659
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The slit structure extends vertically through the memory stack. An upper end of the slit structure is above an upper end of the channel structure.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Hongbin Zhu, Juan Tang, Wei Xu
  • Patent number: 11183571
    Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yong-Sheng Huang, Ming-Chyi Liu, Chih-Ren Hsieh
  • Patent number: 11018148
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Patent number: 10971510
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a plurality of wiring layers stacked via a plurality of insulating layers above the substrate, the wiring layers having an opening extending in a direction perpendicular to the substrate, each of the wiring layers including a first face recessed in a first direction, a second face recessed in a second direction, third face recessed in a third direction, and a fourth face recessed in a fourth direction; a block insulating film provided to be in contact with each of the first to fourth faces; a charge storage film provided on a side face of the block insulating film; a tunnel insulating film provided on a side face of the charge storage film; and a semiconductor film provided on a side face of the tunnel insulating film.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tetsu Morooka
  • Patent number: 10886294
    Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole in a structure is formed. The structure includes a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers can be formed on a sidewall of the initial channel hole to form a channel hole. The channel hole with a channel-forming structure can be formed to form a semiconductor channel. The channel-forming structure can include a memory layer extending along a vertical direction. The plurality of second layers can then be replaced with a plurality of gate electrodes.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 5, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Li Hong Xiao
  • Patent number: 10854534
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 10815193
    Abstract: The invention relates to an improved process for making available the coproduct hydrogen chloride obtained in the preparation of an isocyanate by phosgenation of the corresponding amine for a desired subsequent use (i.e.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 27, 2020
    Assignee: Covestro Deutschland AG
    Inventors: Jan Busch, J├╝rgen Arras, Christian Steffens
  • Patent number: 10777578
    Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: NUSTORAGE TECHNOLOGY CO., LTD.
    Inventor: Fu-Chou Liu
  • Patent number: 10700085
    Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Dong-Sik Lee, Joon-Sung Lim
  • Patent number: 10522560
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source line formed over a substrate. The semiconductor device may include a channel pattern including a connection part disposed over the source line, and pillar parts protruding from the connection part in a first direction. The semiconductor device may include a well structure protruding from the connection part in the first direction and spaced apart from the source line. The semiconductor device may include a source contact structure protruding from the source line in the first direction and passing through the connection part. The semiconductor device may include a gate stack disposed between the source contact structure and the well structure and enclosing the pillar parts over the connection part.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10504914
    Abstract: An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: December 10, 2019
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10418377
    Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: September 17, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Pieter Blomme
  • Patent number: 10410915
    Abstract: A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contact
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 10403637
    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10290651
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 10283515
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. A gate length in a first direction of a floating gate positioned between one of the electrode layers and the semiconductor layer is longer than a layer thickness in the first direction of the one of the electrode layers. A ratio of the layer thickness of the one of the electrode layers to the gate length has a positive correlation with an outer diameter of a first portion of the semiconductor layer surrounded by the floating gate in a second direction from the semiconductor layer toward the one of the electrode layers.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Yasuda
  • Patent number: 10229923
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Patent number: 10224337
    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
  • Patent number: 10050055
    Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Shimura
  • Patent number: 9966353
    Abstract: An elongated trench (35) is formed so as to connect the Ag layer (32) and the exposed part of the circuit layer stretching out around the Ag layer (32). The trench (35) a narrow and elongated recessed part penetrating the glass layer (31) and the aluminum oxide film (12A) from the Ag layer (32) to reach the surface (12a) of the circuit layer (2). The extended part (36), which is a part of the Ag layer (32) flatted along with the inner surface (35a) of the trench (35), is formed in the trench (35). The Ag layer (32) and the circuit layer (12) are electrically connected directly by Ag with a low electric resistance value by the extended part (36) in the portion where the trench (35) is formed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 8, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shuji Nishimoto, Yoshiyuki Nagatomo
  • Patent number: 9966384
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 9960178
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 1, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kawai, Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 9947683
    Abstract: According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars are provided within the structural body extending along the first direction. A first distance between the first pillar and the first interconnection is greater than a second distance between the third pillar and the third interconnection. The first distance is greater than a third distance between the fourth pillar and the fourth interconnection. A fourth distance between the second pillar and the second interconnection is greater than the second distance. The fourth distance is greater than the third distance.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiro Shimojo
  • Patent number: 9941293
    Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Jayavel Pachamuthu, Yingda Dong
  • Patent number: 9935121
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Konagai, Yoshihiro Akutsu, Masaru Kito
  • Patent number: 9923556
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 20, 2018
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 9893076
    Abstract: A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer connection bit line and a substrate which includes one or more elevated source regions disposed on at least one side of each row of NAND flash strings so that each NAND flash string includes a lower select transistor with a first channel portion that runs perpendicular to the surface of the substrate through a vertical channel string body, a second channel portion that runs parallel to the surface of the substrate, and a third channel portion that runs perpendicular to the surface of the substrate through the elevated source region.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 13, 2018
    Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9876027
    Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 23, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Hiroyuki Ogawa
  • Patent number: 9853038
    Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. The support openings are laterally expanded by laterally recessing the insulating layers with respect to the sacrificial material layers. The laterally expanded support openings are filled with a combination of a dielectric material and a sacrificial fill material to form support pillar structures. After forming memory films and channels in the memory openings, the sacrificial material layers are replaced with electrically conductive layers while the support pillar structures provide structural support to the insulating layers. The sacrificial fill material is replaced with contact via structures to form integrated support and contact structures.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 26, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Zhixin Cui
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Patent number: 9831257
    Abstract: A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by insulating strips. Data storage structures including floating gates are disposed along the conductive strips in the stacks. Vertical channel films are disposed on sidewalls of the stacks. Memory cells in the plurality of memory cells have channels in the vertical channel films, and control gates in the conductive strips. A tunnel oxide layer is disposed between the vertical channel films and the floating gates. The floating gates can be coplanar with conductive strips in the plurality of stacks, or be disposed between the conductive strips in the plurality of stacks.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 9812211
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Patent number: 9786613
    Abstract: Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Michael A. Stuber
  • Patent number: 9761527
    Abstract: A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Patent number: 9754953
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 9748265
    Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 29, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Changhyun Lee
  • Patent number: 9704801
    Abstract: A semiconductor memory device includes first and second stacked bodies and a conductive body. The first and second stacked bodies are disposed side by side on the conductive layer. The conductive body is provided between the first and second stacked bodies. The first and second stacked bodies each includes a plurality of electrode layers stacked on the conductive layer, a first insulating layer between adjacent electrode layers, a second insulating layer including a first portion and a second portion, and a semiconductor layer extending through the plurality of electrode layers. The first portion is provided between the first insulating layer and one of the adjacent electrode layers. The second portion is separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body. The second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Masaru Kito, Toshiya Nakamori
  • Patent number: 9698022
    Abstract: Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventor: Randy J. Koval
  • Patent number: 9685454
    Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 20, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani
  • Patent number: 9666279
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: June 26, 2016
    Date of Patent: May 30, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9613981
    Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 4, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 9595531
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Gordon A Haller, Fatma A Simsek-Ege
  • Patent number: 9583423
    Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 9583539
    Abstract: A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Seje Takaki