Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

Abstract: A three-dimensional semiconductor memory device including a substrate including a first connection region, a second connection region, and a cell array region disposed between the first and second connection regions. The memory device further includes an electrode structure including a plurality of electrodes vertically stacked on the substrate, wherein each of the electrodes has a pad exposed on the first connection region, and a dummy electrode structure disposed adjacent to the electrode structure and including a plurality of dummy electrodes vertically stacked on the substrate. Each dummy electrode has a dummy pad exposed on the second connection region. The electrode structure includes a first stair structure and a second stair structure which each includes the pads of the electrodes exposed on the first connection region. The first stair structure extends along a first direction, and the second stair structure extends along a second direction that crosses the first direction.

Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor substrate via a first insulation film. A memory gate electrode is formed over the semiconductor substrate via a second insulation film having a charge accumulation part. The second insulation film is formed across between the semiconductor substrate and the memory gate electrode, and between the control gate electrode and the memory gate electrode. Between the control gate electrode and the memory gate electrode, a third insulation film is formed between the second insulation film and the memory gate electrode. The third insulation film is not formed under the memory gate electrode. A part of the memory gate electrode is present under the lower end face of the third insulation film.

Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.

Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

Abstract: A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The first stacked structure includes a plurality of alternately stacked metal layers and oxide layers. The second stacked structure is disposed adjacent to the first stacked structure and includes a plurality of alternately stacked semiconductor layers and oxide layers. The metal layers of the first stacked structure are connected to the semiconductor layers of the second stacked structure.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

Abstract: According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.

Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a core region of a substrate and a plurality of second fin structures in a peripheral region of the substrate, forming a first dummy gate structure including a first dummy gate oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second gate oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate electrode layer, performing an ion implantation process to tune the threshold voltages of the first fin structures, and removing each first dummy gate oxide layer. The method also includes removing each second dummy gate electrode layer, and forming a gate dielectric layer and a metal layer on each first fin structure and each second fin structure.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings.

Abstract: A semiconductor device according to the present embodiment includes a stacked body having an end which is step-shaped and a contact in each of the steps of the end. Each of the steps includes alternating a plurality of conductive layers and a plurality of insulating layers. The contact includes a plurality of conductive films contacting each of the conductive layers, and a plurality of insulating films contacting each of the insulating layers, the insulating films being provided between the conductive films.

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

Abstract: According to one embodiment, a memory device includes a first interconnect, a second interconnect, a first layer, a second layer. The first interconnect includes a first region and a second region. The first region extends in a first direction and includes a first metallic element. The second region extends in the first direction and includes the first metallic element and nitrogen. The second interconnect extends in a second direction crossing the first direction. A portion of the second region is positioned between the second interconnect and a portion of the first region. The first layer is provided between the second interconnect and the portion of the second region. The second layer is provided between the first layer and the second interconnect. The second layer includes at least one of silicon or a second oxide. The silicon is monocrystalline, polycrystalline, or amorphous.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a semiconductor member extending in the first direction, and a charge storage film provided between the stacked body and the semiconductor member. The stacked body includes first insulating films and electrode films stacked alternately along the first direction. A recess is made in a surface of the stacked body facing the semiconductor member every one of the electrode films.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The insulating portion is provided in the stacked body and extends in a stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction. The insulating portion includes a first insulating film containing silicon oxide, a second insulating film containing silicon oxide, and a third insulating film located between the first insulating film and the second insulating film and containing silicon nitride.

Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern.

Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

Abstract: Provided is an electronic device including a semiconductor memory, The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers and a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interpose d between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical, direction; a second stacked structure comprising, a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and th

Abstract: Methods of making a carbon nanotube material and uses thereof are described. The methods can include obtaining a carbon-containing polymeric matrix shell having a single discrete void space defined by the carbon-containing polymeric matrix shell or having an encapsulated core and subjecting the carbon-containing polymeric matrix shell to a graphitization process to form a shell having a carbon nanotube network from the matrix. The resulting carbon nanotube material includes a shell having a network of carbon nanotubes and either (i) a single discrete void space defined by the network of carbon nanotubes or (ii) the encapsulated core surrounded by the network of carbon nanotubes.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a front side surface of a semiconductor substrate, memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, drain regions contacting a respective vertical semiconductor channel, bit lines electrically connected to the respective drain regions, driver circuitry for the memory stack structures located on a backside of the semiconductor substrate, and electrically conductive paths vertically extending through the semiconductor substrate and electrically connecting nodes of the driver circuitry to respective word lines or bit lines.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.