Abstract: A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.

Abstract: Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.

Abstract: Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion that has a first main electrode and a gate pad electrode on a first main surface of the element active portion, includes first parallel pn layers in a drift layer below the first main electrode, and includes second parallel pn layers below the gate pad electrode. The vertical semiconductor device includes a first conductivity type isolation region between the second parallel pn layers below the gate pad electrode and a p-type well region disposed in a surface layer of the drift layer, and by the repetition pitch of the second parallel pn layers being shorter than the repetition pitch of the first parallel pn layers, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand.

Abstract: [Problem] To provide a semiconductor device in which it is possible to lessen the local concentration of an electric field on a termination structure. [Solution] The semiconductor device (1) comprises: an n-type SiC substrate (2) having an active region (3); a p-type termination structure (4) formed along the outer periphery of the active region (3), and a source electrode (14) that is formed on the SiC substrate (2) with an interlayer film (12) therebetween, and that selectively penetrates the interlayer film (12) and is connected to the termination structure (4). The termination structure (4) forms a second side (42) that has a relatively high dielectric breakdown strength, and a first side (41) that has a relatively low dielectric breakdown strength compared to the second side (42). The shape of the second side (42) and the shape of the first side (41) are asymmetrical.

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Abstract: A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.

Abstract: A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.

Abstract: A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface.

Abstract: A semiconductor device includes at least two device cells integrated in a semiconductor body. Each device cell includes a drift region, a source region, a drain region arranged between the source region and the drift region, a diode region, a pn junction between the diode region and the drift region, and a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom. The body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench. Each device cell further includes a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric. The diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A semiconductor device includes a semiconductor substrate with doped regions of a first type and doped regions of a second type. A first metallization layer connects to the doped regions of the first type through conductive paths, such that current is able to flow within the metallization layer along a plurality of linear axes. A second metallization layer connects to the doped regions of the second type through conductive paths, such that that current is able to flow within the metallization layer along a plurality of linear axes. Contacts on an exterior surface of the semiconductor device can be arranged concentrically.

Abstract: An energy-scavenging interface receives an input signal from a transducer and supplies an output signal to a load. A switch is connected between the transducer and a reference node, and a diode is connected between the transducer and the load. A control circuit closes the switch for a time interval to permit energy storage in the transducer. A scale copy of a peak value of stored electric current is obtained. The switch is opened when the time interval elapses and the stored energy exceeds a threshold. The stored energy is then released to supply the load through the diode. The switch remains open as long as the value of current in the output signal exceeds the value of the scaled copy of the peak value.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract: A radio frequency (RF) switching circuit may include: a first switching circuit unit connected between a first signal port for signal transmission and reception and a common connection node connected to an antenna port and operated according to a first gate signal; a second switching circuit unit connected between a second signal port for signal transmission and reception and the common connection node and operated according to a second gate signal; a negative voltage generating unit generating a negative voltage using a voltage of an RF signal from the common connection node; and a gate signal generating unit generating the first and second gate signals using the negative voltage from the negative voltage generating unit and an operating voltage.

Abstract: The present invention provides a guarding ring structure of a semiconductor high voltage device and the manufacturing method thereof. The guarding ring structure comprises a first N type monocrystalline silicon substrate (3), a second N type monocrystalline silicon substrate (8), a discontinuous oxide layer (2), a metal field plate (1), a device region (9), multiple P+ type diffusion rings (5) and an equipotential ring (4). The second N type monocrystalline silicon substrate (8) is a single N type crystalline layer epitaxially formed on the first N type monocrystalline silicon substrate (3) and has lower doping concentration than the first N type monocrystalline silicon substrate (3). N type diffusion rings (6) are embedded in the inner side of the P+ type diffusion rings (5) and are fully depleted at zero bias voltage. The guarding ring structure can achieve the same withstand voltage with less area and design time.

Abstract: A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first type, a drift region of the second conductivity type, and a first electrode. The first and second emitter regions are arranged between the drift region and first electrode and each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source and body regions. A parasitic region of the first conductivity type is disposed outside the cell region and includes at least one section with charge carrier lifetime reduction means.

Abstract: A radio frequency switching circuit may include a first switching circuit unit including first to nth (n is a natural number greater than at least 2) transistors M1 to Mn connected in series between a first signal port for transmission and reception of signals and a common connection node connected to an antenna port and operated according to a first gate signal; a second switching circuit unit connected in series between the common connection node and a second signal port for transmission and reception of signals and operated according to a second gate signal; and a first impedance adjuster forming an alternating current (AC) ground path between a ground and a gate of the first transistor of the first switching circuit unit when the first switching circuit unit is in an off-state.

Abstract: A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate with second conductivity type compensation regions. The drift portions contact the drain metallization and have a first maximum doping concentration. The compensation regions are in Ohmic contact with the source metallization. The peripheral area includes a first edge termination region and a second semiconductor region in Ohmic contact with the drift portions having a second maximum doping of the first conductivity type which lower than the first maximum doping concentration by a factor of ten. The first edge termination region of the second conductivity type adjoins the second semiconductor region and is in Ohmic contact with the source metallization.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Abstract: A semiconductor device with multiple transistor devices includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device being an LDMOS transistor formed in the semiconductor layer between the first trench and the second trench; and a second transistor device formed in the semiconductor layer on the other side of the second trench. The first transistor device is electrically isolated from the second transistor device by the second trench.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.

Abstract: A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.

Abstract: In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L1 (>0) of the ineffective region in the y-direction, a length D1 of the communication portion in the z-direction, and a length D2 of the bottom portion in the z-direction satisfy L1?2(D1+D2). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.

Abstract: A semiconductor device includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The source region comprises a first region of a first conductivity type, and a second region of a second conductivity type, the second conductivity type opposite to the first conductivity type. The first region is arranged between the second region and the gate structure. The second region comprises at least one projection protruding into the first region and toward the gate structure.

Abstract: A package structure integrating a start-up component, a controller, and a power switch for a power converter, wherein the power converter has a coil having a first end and a second end, and the first end is coupled to a rectifier, the package structure including: a first die pad for carrying a chip of the controller; a second die pad for carrying a chip of the start-up component and a chip of the power switch, wherein the chip of the start-up component has a bottom surface providing a first drain contact; and the chip of the power switch has a bottom surface providing a second drain contact; and a plurality of external connection leads, of which one is connected with the second die pad via a wire and is used to couple with the second end of the coil.

Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.

Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

Abstract: Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate.

Abstract: An field effect transistor has a plurality of cells provided on a first straight line. Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode and a drain terminal electrode. The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode, and a finger source electrode. The gate terminal electrode connects the finger gate electrodes of two adjoining cells in common. The drain terminal electrode connects the finger drain electrodes of two adjoining cells in common. The finger gate electrode of one cell of two adjoining cells and the finger gate electrode of another cell of the two adjoining cells cross perpendicularly. The gate terminal electrode and the drain terminal electrode are provided alternately in a region where the finger gate electrodes of the two adjoining cells cross.

Abstract: In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

Abstract: A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures.

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type opposite the first conductivity type adjacent the body region, and a trench extending into the substrate adjacent the source and body regions. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the gate metallization, and extends along a length of the trench underneath at least part of the source metallization.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; agate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

Abstract: A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

Abstract: A semiconductor device is provided which includes a semiconductor body having a base region and a main horizontal surface, and a first electrode arranged on the main horizontal surface. The semiconductor body further includes a plurality of vertical trenches having gate electrodes in a vertical cross-section. A body region forms a first pn-junction with the base region and extends between two of the vertical trenches. A source region is in ohmic contact with the first electrode and arranged between the two vertical trenches. An anti-latch-up region is arranged between the two vertical trenches and in ohmic contact with the first electrode. The anti-latch-up region has a maximum doping concentration which is higher than a maximum doping concentration of the body region. An anode region forms a rectifying pn-junction with the base region only and adjoins a third one of the vertical trenches, and has ohmic contact with the first electrode.

Abstract: According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

Abstract: The present disclosure includes novel techniques to provide wafer level fan-outs in electronic circuit packages housing one or more circuit devices, at least one of which has input and/or output nodes disposed on opposite facings.

Abstract: A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.