Plural Sections Connected In Parallel (e.g., Power Mosfet) Patents (Class 257/341)
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Patent number: 9024381Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.Type: GrantFiled: March 29, 2012Date of Patent: May 5, 2015Assignee: MagnaChip Semiconductor, Ltd.Inventors: Moon-soo Cho, Kwang-yeon Jun, Hyuk Woo, Chang-sik Lim
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Patent number: 9024383Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.Type: GrantFiled: May 1, 2013Date of Patent: May 5, 2015Assignee: Infineon Technologies Austria AGInventors: Stefan Gamerith, Armin Willmeroth, Franz Hirler
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Patent number: 9012984Abstract: A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator.Type: GrantFiled: March 13, 2013Date of Patent: April 21, 2015Assignee: Cree, Inc.Inventors: Lin Cheng, Anant Agarwal, John Palmour
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Patent number: 9006809Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.Type: GrantFiled: May 19, 2014Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Fei Xie, Wen Cheng Tien, Ya Ping Chen, Li Bin Man, Kuo Jung Chen, Yu Liu, Tian Yi Zhang, Sisi Xie
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Patent number: 9006822Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: GrantFiled: October 24, 2012Date of Patent: April 14, 2015Assignee: NXP B.V.Inventors: Steven Thomas Peake, Phil Rutter
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Patent number: 9006820Abstract: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.Type: GrantFiled: December 19, 2012Date of Patent: April 14, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Hideaki Tsuchiko
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Patent number: 9000576Abstract: The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound.Type: GrantFiled: August 21, 2012Date of Patent: April 7, 2015Assignee: Cyntec Co., Ltd.Inventors: Han-Hsiang Lee, Yi-Cheng Lin, Da-Jung Chen
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Patent number: 8994105Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.Type: GrantFiled: May 6, 2013Date of Patent: March 31, 2015Assignee: Azure Silicon LLCInventor: Jacek Korec
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Patent number: 8987821Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: October 24, 2013Date of Patent: March 24, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Hideaki Tsuchiko
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Patent number: 8987818Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.Type: GrantFiled: December 6, 2011Date of Patent: March 24, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Joel Montgomery McGregor, Vishnu Khemka
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Patent number: 8987819Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.Type: GrantFiled: June 27, 2014Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa
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Patent number: 8981384Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.Type: GrantFiled: July 14, 2011Date of Patent: March 17, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takeyoshi Masuda
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Patent number: 8981477Abstract: A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2015Assignee: Dongbu Hitek Co., Ltd.Inventor: Nam Chil Moon
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Patent number: 8981475Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.Type: GrantFiled: June 18, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Santosh Sharma, Yun Shi, Anthony K. Stamper
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Patent number: 8975156Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.Type: GrantFiled: December 21, 2004Date of Patent: March 10, 2015Assignee: Commissariat a l'Energie AtomiqueInventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
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Patent number: 8975694Abstract: A semiconductor device includes a semiconductor substrate with doped regions of a first type and doped regions of a second type. A first metallization layer connects to the doped regions of the first type through conductive paths, such that current is able to flow within the metallization layer along a plurality of linear axes. A second metallization layer connects to the doped regions of the second type through conductive paths, such that that current is able to flow within the metallization layer along a plurality of linear axes. Contacts on an exterior surface of the semiconductor device can be arranged concentrically.Type: GrantFiled: March 7, 2013Date of Patent: March 10, 2015Assignee: VLT, Inc.Inventors: Patrizio Vinciarelli, Sergey Luzanov
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Patent number: 8969960Abstract: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.Type: GrantFiled: June 7, 2012Date of Patent: March 3, 2015Assignee: Mitsubishi Electric CorporationInventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Masayuki Imaizumi, Kazuyasu Nishikawa
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Patent number: 8969958Abstract: A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate positioned over a channel region and a first portion of a transition region and a polysilicon field plate positioned over a second portion of the transition region and a shallow trench isolation region. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more body extension regions, each having the same doping type as the body substrate, extend at least underneath the edge of the field plate adjacent to the gap. The body extension regions force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.Type: GrantFiled: April 30, 2012Date of Patent: March 3, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Bernhard Heinrich Grote
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Patent number: 8969959Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer.Type: GrantFiled: March 12, 2013Date of Patent: March 3, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Chang Su Jang
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Patent number: 8963242Abstract: A power semiconductor device includes first to fifth electrodes, first to sixth semiconductor layers, and several first pillar layers. The first semiconductor layer is formed on the first electrode. The second semiconductor layer is formed on the first semiconductor layer. Several first pillar layers are arranged parallel with the second semiconductor layer. The third and fourth semiconductor layers are formed on the second semiconductor layer. The fourth electrode is formed on the first pillar layer adjacent to the third semiconductor layer. The fifth electrode is formed on the first pillar layer adjacent to the fourth semiconductor layer. The concentration of dopant of the first pillar layer positioning between the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode is lower than the concentration of dopant of the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode.Type: GrantFiled: March 6, 2013Date of Patent: February 24, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Wataru Saito
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Patent number: 8963240Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.Type: GrantFiled: April 26, 2013Date of Patent: February 24, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Sik K. Lui
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Patent number: 8963241Abstract: A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.Type: GrantFiled: April 30, 2012Date of Patent: February 24, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Bernhard Heinrich Grote
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Patent number: 8957475Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: Dongbu HiTek Co., Ltd.Inventor: Nam Chil Moon
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Patent number: 8957502Abstract: A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n? surface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the n? surface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.Type: GrantFiled: December 12, 2012Date of Patent: February 17, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Dawei Cao, Yasuhiko Onishi
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Patent number: 8952430Abstract: The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.Type: GrantFiled: June 2, 2011Date of Patent: February 10, 2015Assignees: Denso Corporation, Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa
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Patent number: 8937351Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.Type: GrantFiled: March 4, 2013Date of Patent: January 20, 2015Assignee: Microchip Technology IncorporatedInventors: Gregory Dix, Harold Kline, Dan Grimm, Roger Melcher, Jacob L. Williams
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Patent number: 8936985Abstract: A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.Type: GrantFiled: March 12, 2012Date of Patent: January 20, 2015Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20150008519Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.Type: ApplicationFiled: September 22, 2014Publication date: January 8, 2015Applicant: STMicroelectronics S.r.l.Inventors: Simone Dario Mariana, Andrea Paleari, Stephane Wen Yung Bach, Paolo Gattari
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Patent number: 8928077Abstract: In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.Type: GrantFiled: September 19, 2008Date of Patent: January 6, 2015Assignee: Fairchild Semiconductor CorporationInventors: JaeGil Lee, Chongman Yun, Hocheol Jang, Christopher L. Rexer, Praveen Muraleedharan Shenoy, Dwayne S. Reichl, Joseph A. Yedinak
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Patent number: 8928078Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.Type: GrantFiled: December 25, 2012Date of Patent: January 6, 2015Assignee: Richtek Technology Corporation, R.O.C.Inventors: Tzu-Cheng Kao, Jian-Hsing Lee, Jin-Lian Su, Huan-Ping Chu, Hung-Der Su
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Patent number: 8928079Abstract: A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.Type: GrantFiled: September 11, 2012Date of Patent: January 6, 2015Assignee: Alpha and Omega Semiconductor LimitedInventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
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Patent number: 8928071Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.Type: GrantFiled: March 16, 2013Date of Patent: January 6, 2015Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
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Patent number: 8921937Abstract: The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.Type: GrantFiled: August 24, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
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Patent number: 8921936Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively.Type: GrantFiled: December 29, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Sung-Nien Tang, Sheng-Hsiong Yang
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Patent number: 8916913Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.Type: GrantFiled: July 13, 2012Date of Patent: December 23, 2014Assignee: Monolithic Power Systems, Inc.Inventors: Ji-Hyoung Yoo, Lei Zhang
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Patent number: 8912596Abstract: A transistor used for a semiconductor device for high power application needs to have a channel region for obtaining higher drain current. As an example of such a transistor, a vertical (trench type) transistor has been considered; however, the vertical transistor cannot have a high on/off ratio of drain current and thus cannot have favorable transistor characteristics. Over a substrate having conductivity, an oxide semiconductor layer having a surface having a dotted pattern of a plurality of island-shaped regions with a tapered shape in a cross section is sandwiched between a first electrode formed between the substrate and the oxide semiconductor layer and a second electrode formed over the oxide semiconductor layer, and a conductive layer functioning as a gate electrode is formed on the side surface of the island-shaped region in the oxide semiconductor layer with an insulating layer provided therebetween.Type: GrantFiled: July 6, 2012Date of Patent: December 16, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8907420Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: GrantFiled: May 27, 2010Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 8907421Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.Type: GrantFiled: September 10, 2012Date of Patent: December 9, 2014Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.Inventor: Shengan Xiao
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Patent number: 8901652Abstract: An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:āan epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;āan active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.Type: GrantFiled: August 25, 2010Date of Patent: December 2, 2014Assignee: STMicroelectronics S.R.L.Inventors: Mario Giuseppe Saggio, Alfio Guarnera, Simone Rascunaā²
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Patent number: 8901661Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.Type: GrantFiled: June 6, 2013Date of Patent: December 2, 2014Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Franz Hirler, Joachim Weyers
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Patent number: 8901671Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.Type: GrantFiled: February 10, 2011Date of Patent: December 2, 2014Assignee: Forschungsverbund Berlin E.V.Inventors: Oliver Hilt, Hans-Joachim Wuerfl
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Patent number: 8901614Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.Type: GrantFiled: May 19, 2009Date of Patent: December 2, 2014Assignee: X-Fab Semiconductor Foundries AGInventors: Michael Stoisiek, Michael Gross
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Patent number: 8900949Abstract: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.Type: GrantFiled: May 22, 2013Date of Patent: December 2, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Hamza Yilmaz
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Patent number: 8896061Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: GrantFiled: September 14, 2012Date of Patent: November 25, 2014Assignee: Macronix International Co., Ltd.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8895370Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.Type: GrantFiled: September 30, 2013Date of Patent: November 25, 2014Assignee: STMicroelectronics S.R.L.Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magriā²
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Patent number: 8890243Abstract: In the interior of a semiconductor substrate having a main surface, a first p? epitaxial region is formed, a second p? epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p? epitaxial region and the second p? epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p? epitaxial region is formed between the n+ buried region and the second p? epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.Type: GrantFiled: November 27, 2012Date of Patent: November 18, 2014Assignee: Renesas Electronics CorporationInventor: Shinichiro Yanagi
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Patent number: 8890144Abstract: A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.Type: GrantFiled: March 8, 2012Date of Patent: November 18, 2014Assignee: United Microelectronics Corp.Inventors: Pao-An Chang, Ching-Ming Lee, Te-Yuan Wu, Chih-Chung Wang, Wen-Fang Lee, Wei-Lun Hsu
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Patent number: 8884369Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.Type: GrantFiled: June 1, 2012Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
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Patent number: 8884361Abstract: A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode.Type: GrantFiled: January 13, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura
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Patent number: RE45449Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.Type: GrantFiled: April 30, 2013Date of Patent: April 7, 2015Assignee: Infineon Technologies AGInventors: Markus Zundel, Franz Hirler, Armin Willmeroth