Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: In a manufacturing method of an active matrix type liquid crystal display device, a semiconductor device having good TFT characteristics is realized. LDD regions of a driver circuit NTFT and LDD regions of a pixel section NTFT are given different impurity concentration. An impurity is doped at differing concentrations using a mask. Thus a liquid crystal display device provided with a driver circuit having high speed operation and a pixel section with high reliability can be obtained.

Abstract: A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

Abstract: A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

Abstract: A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

Abstract: A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).

Abstract: An ultra-thin gate oxide layer of hafnium oxide (HfO2) and a method of formation are disclosed. The ultra-thin gate oxide layer of hafnium oxide (HfO2) is formed by a two-step process. A thin hafnium (Hf) film is first formed by thermal evaporation at a low substrate temperature, after which the thin hafnium film is radically oxidized using a krypton/oxygen (Kr/O2) high-density plasma to form the ultra-thin gate oxide layer of hafnium oxide (HfO2). The ultra-thin gate oxide layer of hafnium oxide (HfO2) formed by the method of the present invention is thermally stable in contact with silicon and is resistive to impurity diffusion at the HfO2/silicon interface. The formation of the ultra-thin gate oxide layer of hafnium oxide (HfO2) eliminates the need for a diffusion barrier layer, allows thickness uniformity of the field oxide on the isolation regions and, more importantly, preserves the atomically smooth surface of the silicon substrate.

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced.

Abstract: A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method provides a semiconductor structure having a thin silicide region formed atop source/drain regions and a thicker silicide region formed atop gate regions. The method includes: first forming a structure which includes self-aligned silicide regions atop the source/drain diffusion regions and the gate region. A non-reactive film and a planarizing film are then applied to the structure containing the self-aligned silicide regions and thereafter a thicker silicide region, as compared to the self-aligned silicide region located atop the source/drain regions, is formed on the gate region.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

Abstract: A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes a first edge, a second edge and a base. The method and system further include providing a source and/or a drain for the at least one gate. The source and/or a drain are in proximity to the first edge or the first and second edges of the at least one gate. The at least one gate, the source and/or drain or both the at least one gate and the source and/or drain are configured such that source and/or drain do not substantially overlap the at least one gate at the base of the at least one gate.

Abstract: In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and the yield is increased by reducing the number of process steps.

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract: A power semiconductor device formed of a substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed on a surface of the substrate, a plurality of lightly doped spaced base regions of a second conductivity type formed to a first predetermined depth in the epitaxial layer with common conduction regions between the base regions, a plurality of highly doped source regions of the first conductivity type formed in the lightly doped base regions, invertible channel regions disposed between the source regions and the common conduction regions, deep implanted junctions of the second conductivity type formed in the epitaxial layer under the base regions extending between the first predetermined depth and a second predetermined depth, gate electrodes insulated from the invertible channels by an insulation layer formed over the invertible channels, and thick insulation spacers disposed over at least a portion of the common conduction regions.

Abstract: A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).

Abstract: A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantation, which forms a low-concentration source region, Source contact region, drain region, and drain contact region. Side spacers are formed on both side walls of the gate-use poly-Si layer, after which the laminate of the gate-use poly-Si layer, the side spacers, and the gate insulation film is used along with the field insulation film as a mask to perform ion implantation via the silicon nitride layer, which forms a high-concentration source region and drain region. After a silicide conversion treatment, the unreacted metal is removed, which forms a silicide layer.

Abstract: A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K dielectric spacers can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs). The T-shaped conductor forms dynamic source/drain extensions.

Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.

Abstract: Thin film transistors for a display device each include a semiconductor layer made of polysilicon having a channel region, drain and source regions at both sides of the channel region and doped with impurity of high concentration, and an LDD region arranged either between the drain region and the channel region or between the source region and the channel region and doped with impurity of low concentration. An insulation film is formed over an upper surface of the semiconductor layer and has a film thickness which decreases in a step-like manner as it extends to the channel region, the LDD region, the drain and the source regions; and a gate electrode is formed over the channel region through the insulation film. Such a constitution can enhance the numerical aperture and can suppress the magnitude of stepped portions in a periphery of the thin film transistor.

Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: The present invention relates to a semiconductor device and a semiconductor integrated circuit. The semiconductor device comprises a semiconductor layer comprising a channel region, a source and a drain regions and at least one lower impurity concentration region interposed between the channel region and the source or the drain region. The source and the drain regions comprise metal silicide region. The lower impurity concentration region is not covered with the metal silicide region. The operational speed of the circuit can be improved, and the leak current of the transistor can be reduced.

Abstract: It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode (3) at a subsequent step. In the meantime, the upper surface of the gate electrode (3) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall (4) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode (3) and to form a contact on the gate electrode (3).

Abstract: To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.

Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

Abstract: The invention relates to a semiconductor component with enhanced avalanche resistance. At the nominal current of this semiconductor component, in the event of an avalanche the voltage applied between two electrodes is 6% or more above the static reverse voltage at the same temperature.

Abstract: A self-luminescence display device, in which dispersion in display among a plurality of pixels, caused by dispersion in characteristics among drive thin-film transistors, is decreased and uniform display free of unevenness can be obtained. The device includes a plurality of pixels having current drive type luminescent elements, and parallel-connected n (n≧2) thin-film transistors to feed a drive current to the respective current drive type luminescent elements. The transistors are arranged in different pixels, respectively, for example, in a first region of pixels adjacent to one another along a first direction. A second region of dummy pixels can be provided on at least one side of said first region along said first direction.

Abstract: The invention disclosed a power MOSFET with reduced snap-back and being capable increasing avalanche-breakdown current endurance, which has sequentially a drain with N+ silicon substrate, an N− epitaxial layer formed on said N+ silicon substrate, a source contact region formed of N+ doped well and P+ doped well implanted after etching in a P− well formed on said N− epitaxial layer, and a gate electrode with deposition of polysilicon above a channel between said N− epitaxial layer and N+ source contact region, said device is characterized in that: Said source contact region is formed by etching into said P− well first and implanting P+ dopant to the interface between said N− epitaxial layer and P− well, and the source contact region of said N+ well and that of said P+ well are not at the same level, by which it is possible to increase the avalanche-breakdown current endurance of the power MOSFET device.

Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Abstract: A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.

Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

Abstract: The present invention discloses a semiconductor device, and a method of fabricating the same, where the semiconductor device has a gate electrode, a source-drain diffused layer of a first conductivity type, and a sidewall insulating film formed on the side face of the gate electrode, wherein the source-drain diffused layer has a lightly doped region formed below the sidewall insulating film, and a heavily doped region with impurity concentration higher than that of the lightly doped region, and the lightly doped region includes at least two kinds of impurities of the first conductivity type.

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56).

Abstract: There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low.

Abstract: A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.

Abstract: An aspect of the present invention includes: a gate insulating layer formed on an n-type silicon semiconductor region; a gate electrode formed on the gate insulating layer; a channel region formed immediately below the gate electrode in the semiconductor region; p-type source/drain regions formed at both sides of the channel region in the semiconductor region; p-type diffusion layer regions formed between the channel region and the source/drain regions in the semiconductor region and having a lower impurity concentration than the source/drain regions; first impurity regions formed near surface portions of the diffusion layer regions; and second impurity regions formed in part of the p-type diffusion layer regions and near surface portions of the source/drain regions, the second impurity regions being deeper than the first impurity regions, the first and second impurity regions containing one element selected from germanium, silicon, gallium, and indium as impurity.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: By appropriately selecting the structure of top gate type or staggered type TFTs disposed in the respective circuits of a semiconductor device depending on the function of the circuits, the operating characteristics and the reliability of the semiconductor device is improved. An LDD region (107) the whole of which overlaps a gate electrode is provided in a first n-channel type TFT of a controlling circuit. LDD regions (111) and (112) at least part of which overlaps a gate electrode are provided in a second n-channel type TFT of the control circuit. LDD regions (117) to (120) which do not overlap a gate electrode through offset regions are provided in an n-channel type TFT of a pixel matrix circuit. By making different the concentration of LDD regions of the control circuit and the concentration of the pixel matrix circuit, optimized circuit operation is obtained.