Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas have a predetermined impurity concentration and a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas have a same conductivity type as the first impurity areas and an impurity concentration lower than the concentration of the first impurity area.

Abstract: A magnetic memory device includes a memory cell portion, a peripheral circuit portion positioned in the vicinity of the memory cell portion, a plurality of first magnetoresistive effect elements which are arranged in the memory cell portion and function as memory elements, and a plurality of second magnetoresistive effect elements which are arranged in at least a part of the peripheral circuit portion and function as dummies, wherein a sum total of occupying areas of the second magnetoresistive effect elements is 5% to 80% of the peripheral circuit portion.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Abstract: By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments.

Abstract: A transistor comprising a gate, a channel beneath the gate and separated from the gate by an insulator, a source adjacent to the channel on a first side of the gate, a drain adjacent to the channel on a second side of the gate, doped extension regions into the channel from the source and the drain that underlap the gate, and insulating spacers adjacent to sidewalls of the gate that overlap the extension regions. The insulating spacers may be used to align the doped extension regions, offset the extension regions from the gate, and reduce Miller capacitance and standby leakage current.

Abstract: A gate electrode 14 is formed through a gate oxide film 13 over a channel region 12 in an element region 11, and sidewall dielectric films 16 are provided on side sections of the gate electrode 14. Source/drain regions 17 include low concentration impurity regions 171 and high concentration impurity regions 172. The impurity regions 172 are provided, by an over-etching method when forming the sidewalls 16, at a disposition level LV2 in the element region 11, which is lower than a disposition level LV1 where the impurity regions 171 are disposed. Assisting impurity regions 173 are provided in regions where the levels change between level LV1 and LV2. As a result, the continuity of impurity regions between the impurity regions 172 and the impurity regions 171 that are low concentration extension regions is secured, the their electrical connection is stabilized.

Abstract: A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: Embodiments of the present invention provide a striped or closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a sidewall spacer is then formed at the lateral sides of the gate electrode on the semiconductor substrate. Epitaxial growth is conducted at a lower growth rate to form, at both lateral sides of the sidewall spacer on the semiconductor substrate, first semiconductor layers made of first single-crystal silicon films superior in crystallinity. Then, epitaxial growth is conducted at a higher growth rate to form, on the first semiconductor layers, second semiconductor layers made of single-crystal films or polycrystalline films, which are inferior in crystallinity, or amorphous films. The upper areas of the first semiconductor layers and the whole areas of the second semiconductor layers are doped with impurity, thus forming impurity diffusion layers respectively serving as a source and a drain.

Abstract: An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: An electrical switching device includes a semiconductor having a channel therein which is proximate to at least on channel tap in an extension region and also to a gate. A conductor (e.g., a metal) is disposed proximate to the extension region but is electrically isolated from both the extension region and the gate (e.g., through the use of one or more insulators). The conductor has a workfunction outside of the bandgap of a semiconductor in the extension region and therefore includes a layer of charge in the extension region. The magnitude and polarity of this layer of charge is controlled through selection of the metal, the semiconductor, and the insulator.

Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

Abstract: A buried insulating film is formed in an LDD region between a source region and a drain region, and a non-doped silicon film is formed in the SOI layer above the buried insulating film. The SOI layer lying under the buried insulating film has a body concentration of 1018 cm?3.

Abstract: A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.

Abstract: The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.

Abstract: A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.

Abstract: A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A field effect transistor includes a drain region (12) having a first portion (18) and a second portion (20), with the second portion being more lightly doped than the first portion. A channel region (14) is adjacent to the second portion and a drain electrode (24) overlies the drain region. A gate electrode (16) overlies the channel region. A shield structure (30) overlies the drain region and has a first section (32) at a first distance (33) from a semiconductor substrate (10) and a second section (34) at a second distance (35) from the semiconductor substrate, the second distance being greater than the first distance. In a particular embodiment the FET includes a shield structure wherein the first and second sections are physically separate. The location of these shield sections may be varied within the FET, and the potential of each section may be independently controlled.

Abstract: Provided is a semiconductor device having a source region formed of a semiconductor, a drain region formed of a semiconductor of the same conductive type as that of the source region, a channel region formed of a semiconductor between the source region and the drain region, a gate insulating film provided on the channel region, and a gate electrode provided on the gate insulating film and formed with a P-N junction including a P-type semiconductor region and an N-type semiconductor region. At this time, the P-type semiconductor region and the N-type semiconductor region of the P-N junction of the gate electrode are electrically insulated.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region 45b having a lightly doped drain region 42b and a heavily doped drain region 44b, a first silicide layer 40c formed on the source region, a second silicide layer 40d formed on the drain region, a first conductor plug 54 connected to the first silcide layer and a second conductor plug 54 connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region.

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

Abstract: A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

Abstract: Gate electrodes (3) are formed on a semiconductor substrate (1), each with a gate insulating film (2) interposed therebetween. A pair of offset spacers (4) are respectively formed on opposite side faces of each of the gate insulating film (2) and the gate electrodes (3). Diffusion layers (5) are formed in the semiconductor substrate (1) on opposite sides of a portion of the semiconductor substrate (1) immediately under each of the gate electrodes (3), by ion implantation.

Abstract: To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.

Abstract: In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround the heavily doped region. The heavily doped region and vertical lightly doped region have a second conductivity type and are disposed in the semiconductor substrate on both sides of the gate electrode. The vertical lightly doped region has a lower impurity concentration and a larger depth than the heavily doped regions. A horizontal lightly doped region, which has a lower impurity concentration than the vertical lightly doped region, is further disposed in an upper side of the vertical lightly doped region.

Abstract: A metal-oxide-semiconductor (MOS) transistor with improved resistance to HF attack during a pre-SEG clean process is disclosed. The MOS transistor encompasses a semiconductor substrate having a main surface and a gate electrode with two sidewalls. The gate electrode is patterned on the main surface of the semiconductor substrate. Source/drain (S/D) doping regions are formed on opposite sides of the gate electrode in the main surface of the semiconductor substrate. A gate oxide layer is disposed underneath the gate electrode. A surface-nitridized silicon oxide liner covers the two sidewalls of the gate electrode. The surface nitridized silicon oxide liner further overlies lightly doped drain (LDD) regions in close proximity to the gate electrode. A silicon nitride spacer is disposed on the surface-nitridized silicon oxide liner. An elevated selective epitaxial growth (SEG) film is grown on the S/D regions and top of the gate electrode. A silicide layer formed from the elevated SEG film.

Abstract: A microwave transistor structure comprising: (1) a substrate having a top surface; (2) a silicon semiconductor material of a first conductivity type; (3) a conductive gate; (4) a channel region of a second conductivity type; (5) a drain region of the second conductivity type; (6) a body of the first conductivity type; (7) a source region of the second conductivity type; (8) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the channel region, wherein the shield plate is adjacent and parallel to the drain region, and to the conductive gate region; and (9) a conductive plug region formed in the body region of the silicon semiconductor material, wherein the conductive plug region connects a lateral surface of the body region to the top surface of the substrate.

Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively; an n-type intermediate region provided between two adjacent ones of the channel regions; and two pairs of lightly doped regions. The lightly doped regions in one of the two pairs have mutually different carrier concentrations and are located between one of the heavily doped regions and one of the channel regions that is closer to the heavily doped region than any other channel region is. The lightly doped regions in the other pair also have mutually different carrier concentrations and are located between the other heavily doped region and another one of the channel regions that is closer to the heavily doped region than any other channel region is.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Abstract: A method of forming a shallow junction in a semiconductor substrate is disclosed. The method of one embodiment comprises preamorphizing a first region of a semiconductor substrate to a first depth and implanting recrystallization inhibitors into a second region of the semiconductor substrate. The second region is a part of the first region and has a second depth. Next, a dopant is implanted into a third region of the semiconductor substrate with the third region being a part of the second region and a first annealing is performed to selectively recrystallize the first region that has no recrystallization inhibitors. Next, a second annealing is performed to recrystallize the second region and diffuse the dopant within the second region.

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

Abstract: Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.

Abstract: The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: There is provided an electronic device having high reliability and high color reproducibility. A pixel structure is made such that a switching FET (201) and an electric current controlling FET (202) are formed on a single crystal semiconductor substrate (11), and an EL element (203) is electrically connected to the electric current controlling FET (202). The fluctuation in characteristics of the electric current controlling FET (202) is very low among pixels, and an image with high color reproducibility can be obtained. By taking hot carrier measures in the electric current controlling FET (202), the electronic device having high reliability can be obtained.

Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: A semiconductor device is a P-channel type MOS field effect transistor that comprises; a semiconductor substrate, a gate oxide film positioned on the semiconductor substrate, a gate electrode positioned on the gate oxide film; and two P+ source and drain diffusion areas, each of which has a P− offset area, that are formed in an n-well region of the semiconductor substrate. At least one of the gate electrode, the gate oxide film and the offset areas contains fluorine.