Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A semiconductor device comprises a base semiconductor substrate (201) having an edge area (120) which surrounds an element forming area (110), a buried oxide film (202) provided over the base semiconductor substrate (201) in the element forming area (110), an element forming semiconductor substrate (203) provided over the buried oxide film (202).

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract: There is disclosed a method of fabricating a semiconductor device having excellent characteristics. The device comprises a substrate having an insulating surface. A hydrogen-rich region is formed inside the substrate by ion doping. Thermal processing is performed at 300 to 450° C. to thermally diffuse hydrogen ions. Thus, dangling bonds and defect levels in an active layer are compensated. Since the hydrogenation from inside the semiconductor device is enabled in this way, hydrogen termination can be performed at a high efficiency.

Abstract: A semiconductor device structure including a substrate including at least one silicon-on-insulator substrate region and at least one non-silicon-on-insulator region. The at least one silicon-on-insulator region and at least one non-silicon-on-insulator region are formed in a pattern in the substrate. At least one trench is arranged in the vicinity of at least at a portion of a boundary between a silicon-on-insulator substrate region and the non-silicon-on-insulator substrate region. The at least one trench is arranged in at least one of the silicon-on-insulator region and the non-silicon-on-insulator region.

Abstract: A device for protecting a structure of SOI type including several insulated cells, each cell being formed of a portion of a semiconductor substrate of a first conductivity type having its bottom and its lateral walls delimited by an insulating area. A protective cell includes a first semiconductor region of the second conductivity type connected to a reference potential and several second regions of the second conductivity type separated from one another and from the first region. The substrate portion of each of the cells other than the protective cell is connected to one of the second regions.

Abstract: The microreactor is completely integrated and is formed by a semiconductor body having a surface and housing at least one buried channel accessible from the surface of the semiconductor body through two trenches. A heating element extends above the surface over the channel and a resist region extends above the heating element and defines an inlet reservoir and an outlet reservoir. The reservoirs are connected to the trenches and have, in cross-section, a larger area than the trenches. The outlet reservoir has a larger area than the inlet reservoir. A sensing electrode extends above the surface and inside the outlet reservoir.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between the element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: A silicon on insulator (SOI) semiconductor device is provided having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The device combines the inverted region with channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on insulator layers. Additionally, the invention encompasses semicondutor devices and assemblies utilizing silicon-on-insulator layers.

Abstract: An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is “gettered” into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.

Abstract: A trench 312a passing through an impurity area 301a of a circuit element formed at a semiconductor layer 306 of an SOI substrate 314 and extending to a conductive layer 311 formed at a semiconductor substrate 304 is provided. Inside the trench 312a, a conductor 310a for electrically connecting the impurity area 301a of the circuit element and the conductive layer 311 is formed. By adopting this structure, it becomes possible to promptly transmit a surge voltage applied through an external connector terminal 101 to the semiconductor substrate 304 to prevent breakdown at the buried insulator layer. Thus, the buried insulator layer in a semiconductor integrated circuit device having an SOI structure is protected by providing a protective element under the impurity area of the integrated circuit element to assure a high degree of reliability while enabling high-speed drive and higher integration.

Abstract: A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n− region, a n+ region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n− region is formed in the substrate, and the n+ region is formed within the n− region. The isolation region is formed in the substrate next to the edge of the n− region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n− region, a portion of the isolation region and a portion of the n+ region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n− region to the field implant region so that edge junction leakage is reduced.

Abstract: A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal.

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: A method of manufacturing a polycrystalline silicon film having a particular field effect mobility is disclosed. A first polycrystalline silicon film is formed on a transparent insulation substrate. The surface of the silicon film is oxidized, and an amorphous silicon film is formed on the first polycrystalline silicon film and oxide layer. The amorphous silicon film is subjected to a solid phase growth process to be converted to a second polycrystalline silicon film. The field effect mobility of the second polycrystalline silicon film can be adjusted to a desired value by controlling the relative thicknesses of the first and second polycrystalline silicon films.

Abstract: A SOI.MOSFET includes: a substrate; a buried oxide film formed on the substrate; a top semiconductor layer formed on the buried oxide film; a gate electrode formed on the top semiconductor layer with a gate oxide film interposed therebetween; source/drain regions of a second conductivity type formed in the top semiconductor layer and on both sides of the gate electrode; and an embedded region of the second conductivity type which is disposed in the top semiconductor layer and between the source/drain regions and is separated from the source/drain regions and from a top semiconductor/gate oxide interface.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the Vcc and Vss. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for highperformance, low-voltage, and low-power VLSI circuits on SOI wafers.

Abstract: In producing a semiconductor device by annealing with laser light irradiation, while a linear laser light is scanned in a direction perpendicular to a line, the annealing is performed for a semiconductor material. In this state, since an anneal effect in a beam lateral direction corresponding to a line direction is 2 times or more different than that in the scanning direction, a plurality of semiconductor elements are formed along a line direction in which the linear laser light is irradiated. Also, a line direction connecting the source and drain region of a thin film transistor is aligned to the line direction of the linear laser light.

Abstract: A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A semiconductor device includes a substrate and a first layer of a first conductive material on the substrate, the first layer having a first etching rate. A second layer of a second conductive material has a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate. A third layer includes a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate. An insulating layer has a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate. A transparent conductive layer is on the third layer through the first and second holes.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.

Abstract: A method and apparatus for performing multiple implantations in a semiconductor wafer is used to set variable implantation waveforms. An implanter is used, which allows for setting of variable waveforms, corresponding to energy, beam current, and angle, used for implantation. At least one of a ramping voltage, a ramping beam current source, and a programmable motor mechanically connected to a wafer table is used to obtain the variable waveforms. Using the implanter and method of the invention, detailed doping profiles are created using only a single implant. Such detailed doping profiles are used to create high gradient retrograde wells, and transistors with punch-through suppression implants and channel implants with controlled dopant gradients.

Abstract: An FET structure for utilization with a silicon-on-insulator semiconductor device structure. The structure includes a silicon-on-insulator substrate structure. Source and drain diffusion regions are provided on the silicon-on-insulator substrate. An FET body region is interconnected with the source and drain diffusion regions. A gate oxide region is arranged over at least a portion of the body region and the source and drain diffusion regions. A gate region is arranged over at least a portion of the gate oxide region. A diode is interconnected with and provides a conductive pathway between the gate region and the FET body region. The diode is electrically isolated from the FET source and drain regions and inversion channel by a high threshold FET region.

Abstract: An SOI substrate (10) has a buried oxide film (31) formed on a silicon substrate (2) and an SOI layer (4) formed on the buried oxide film. The buried oxide film substantially uniformly contains fluorine over the whole area thereof, and is reduced in relative dielectric constant as compared with a silicon oxide film, having a relative dielectric constant of about 3.9, containing no fluorine. The fluorine concentration of the buried oxide film (31) is set to be at any level in the range of 1×1019 to 1×1022 cm−3 substantially over the whole area. Thus provided is a MOS transistor suppressing influence by a DIBL effect and preventing occurrence of current leakage on an edge portion of a channel region resulting from influence by an electric field from an adjacent semiconductor element.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms.

Abstract: A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Abstract: Active matrix TFT elements array in which the number of production steps is not increased and the high production yield can be achieved. A semiconductor film is formed by patterning in an elongated island shape between pixel electrodes disposed neighboring to each other in the direction of drain lines to provide a protrusion to prevent shorting across the pixel electrodes even if photoresist film residuals are produced.

Abstract: A method and structure for a silicon on insulator (SOI) device with a body contact are provided. The body contact is formed by epitaxial growth from a substrate to the body region of the device. The body contact is self-aligned with the gate of the device and is buried within an isolation region outside of the active area of the device. Thus, the body contact does not increase parasitic capacitance in the device, not does the body contact affect device density. No additional metal wiring or contact holes are required.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: In a region on the left hand of FIG. 1 with respect to the gate electrode (107), a first source region (103a), a body-potential drawing region (105) and a second source region (103b) are formed in this order along the vertical direction of this figure. The first and second source regions (103a, 103b) are of n+ type, and the body-potential drawing region (105) is of p+ type. In a thin-film transistor (100), the body-potential drawing region (105) can draw and fix a body potential.

Abstract: In order to obtain a thin-film transistor having high characteristics using a metal element for accelerating the crystallization of silicon, a nickel element is selectively added to the surface of an amorphous silicon film (103) in regions (101) and (102) and regions (108) to (110), and a heat treatment is carried out to grow crystals (horizontal growth) in directions parallel to the substrate as indicated by arrows (104) to (107). At this point, the regions (108) to (110) having a width of 5 &mgr;m or less serve as stopper regions so that horizontal growth starting from the regions (101) and (102) stops there. In this way, the horizontal growth regions can be formed with high controllability. Then a circuit such as a shift register can be constructed with a region having the same crystal growth form.

Abstract: The invention provides a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and SOI layer provided in succession on a silicon substrate.

Abstract: A method for creating a SOI CMOS type device compatible with bulk CMOS using a bulk CMOS physical layout data base. The method uses the P-well and N-well masks used in fabrication of bulk CMOS devices. The N-well and P-well regions are fabricated by implanting the appropriate dopants above and below the buried oxide layer to create the basic SOI CMOS structure. Particular modifications to the basic SOI CMOS structure include providing a mask for establishing ohmic contact with the wells below the buried oxide layer. The modification uses a separate mask which is generated from the existing bulk CMOS mask database.

Abstract: A TFT structure includes a variably doped contact layer system in order to reduce leakage current characteristics and increase mobility of the TFT. Such TFTs may be utilized in, for example, X-ray imagers or liquid crystal displays. In certain embodiments, the contact layer system is lightly doped adjacent a semiconductor or channel layer, and is more heavily doped adjacent the source/drain electrodes. The variation in doping density of the contact layer system may be performed in a step-like manner, gradually, continuously, or in any other suitable manner. In certain embodiments, the contact layer system may include a single layer which is deposited over an intrinsic semiconductor layer, with the amount of dopant gas being used during the deposition process being adjusted through the deposition of the single layer so as to cause the doping density to vary (increase or decrease) throughout the thickness of the system/layer.

Abstract: A thin-film transistor comprises a semiconductor unit 60 constituted of a channel formation portion 61 and a source region 63 and a drain region 62 sandwiching the channel formation portion 61 therebetween, a transparent pixel electrode 54 made of indium tin oxide, a drain electrode 57 and a source electrode 58 each made of Cr, Mo, Ta or W, and a gate electrode 68 formed on the channel formation portion via a gate insulating layer 58, wherein the drain region and the source region are, respectively, connected with the electrodes through silicide layers 64, 65 formed by diffusion of the any above-mentioned element. A method for making the transistor and a liquid crystal display device comprising the transistor are also disclosed.

Abstract: Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g.

Abstract: A SOI MOS field effect transistor includes: a superficial top semiconductor layer of a first conductivity type formed on a SOI substrate; source and drain regions of a second conductivity type arranged apart from each other on the top semiconductor layer; a P-type first channel region, an N+-type floating region, and a P-type second channel region formed in this order in a self-aligned manner and disposed between the N+-type source region and the N+-type drain region for an N-type MOSFET, or an N-type first channel region, a P+-type floating region, and an N-type second channel region formed in this order in a self-aligned manner and disposed between the P+-type source region and the P+-type drain region for a P-type MOSFET; and two gate electrodes for controlling the first and second channel regions, wherein a doping concentration of the second channel region adjacent to the drain region is lower than a doping concentration of the first channel region adjacent to the source regi

Abstract: Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impurity regions allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Abstract: A high voltage metal oxide semiconductor device. The high voltage device comprises a high voltage NMOS, a high voltage PMOS, or a high voltage CMOS. A field oxide layer is used to isolate the gate from the source region, while a diffusion region is formed under the field oxide layer. A channel region around the source drain extends across a first doped well and a second doped well having different dopant concentration. The channel region further comprises two grading regions with different dopant concentrations around the drain region.

Abstract: In a process for producing a thin-film device, a conducting layer composed of an anodically oxidizable metal is formed on a substrate and is etched to form gate bus lines and gate electrode having upper surfaces parallel to the substrate and inclined side surfaces. The gate bus lines and the gate electrodes are anodically oxidized, so that they include inner conducting portions and outer insulating oxide films covering the inner conducting portions. The outer insulating films prevent the bus lines from short circuiting, and the inclined side surfaces of the bus lines makes it possible to fabricate a dense wiring arrangement.