Abstract: An integrated thin film transistor on insulator circuit made up of a number of thin film transistors formed with small feature size and densely packed so as to allow interconnection as a complex circuit. An insulating substrate, preferably flexible, serves as the support layer for the integrated circuit. Control gate metallization is carried on the insulating substrate, a dielectric layer is deposited over the control gate, and an amorphous silicon layer with doped source and drain regions deposited on the dielectric layer. Trenches are formed to remove the amorphous silicon material between transistors to allow highly dense circuit packing. An upper interconnect level which forms connections to the source and drain and gate regions of the thin film transistors, also interconnects the transistors to form more complex circuit structures. Due to the dense packing of the transistors allowed by the trench isolation, the interconnecting foils can be relatively short, increasing the speed of the circuit.

Abstract: The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source and drain diffusion layers of n+-type are formed on first opposite sides of a channel region in the p-type silicon substrate. A gate made of polycrystalline silicon is formed over the channel region through a gate oxide film. Leak guard diffusion layers of p-type are formed on second opposite sides of the channel region in the p-type silicon substrate. The p-type leak guard diffusion layer has a junction surface to the isolation oxide film. The junction surface of the p-type leak guard diffusion layer and the isolation oxide film exists up to a level which is deeper than a depth of the n+-type source and drain diffusion layers.

Abstract: A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between the element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: A polycrystalline silicon active layer is provided on a transparent insulating substrate. Phosphorus is ion-implanted into the active layer, to form a pair of n-type source/drain regions with a base region interposed therebetween. In this ion-implantation, a density gradient of phosphorus is formed in the thicknesses direction of the active layer. Boron is ion-implanted into each of the source/drain regions, to be adjacent to the base region. In this ion-implantation, a density gradient of boron is formed, and the position providing a maximum density of boron is set to be deeper than the position which provides a maximum density of phosphorus. By the ion-implantation of boron, an n-type LDD portion having a high resistance and a p-type portion are formed on the upper and lower sides, respectively, adjacent to the base region within each of the source/drain regions.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector-base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: In an LDD polysilicon thin-film transistor, the active layer is formed in a single body and the upper surface thereof is oxidized. A gate insulating layer has a bird's beak type structure and the source and drain region are simultaneously formed in high and low concentrations by performing one ion implantation process, so that the manufacturing process is simplified and the quality of the active layer is improved. Also, the ion concentration level tapers off toward the channel, so that the V.sub.gs -I.sub.ds characteristic is improved.

Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Abstract: A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

Abstract: It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6').

Abstract: An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.

Abstract: A semiconductor memory and device comprising a plurality of N-channel and P-channel transistor regions, a first and a second field shield region, and an oxide isolation region. The first field shield region is disposed so as to isolate the N-channel transistor regions from one another, and the second field shield region is provided to isolate the P-channel transistor regions from one another. The oxide isolation region is furnished to isolate the N-channel transistor regions from the P-channel transistor regions. The isolation effected by the field shield regions and the isolation provided by the oxide isolation region combine to suppress latch-up, fix the potential in the body regions of the MOS transistors making up the memory or device, and minimize the layout area of the memory or device.

Abstract: A thin film transistor comprising a gate electrode offset from source and drain, which comprises a substrate having thereon a gate electrode fabricated on an active region provided on the substrate, wherein, an anodic oxide of the material constituting the gate electrode is provided on the side and the upper face of said gate electrode, and the anodic oxide on the side of the gate electrode is formed thicker than the anodic oxide formed on the upper face.

Abstract: Generation of parasitic transistor in active layer edge is prevented, in an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: An SOI DRAM includes a direct body contact between the SOI layer and the silicon substrate, and field-shield isolation positioned on the surface of the SOI structure which extends over the direct body contact. Deep trench storage capacitors are positioned adjacent the direct body contact.

Abstract: In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner in the source and drain regions than in the channel forming region a structure is realized wherein, at the boundary between the source region and the channel forming region and the boundary between the drain region and the channel forming region, portions where electric field concentrations occur are displaced from the portion where a channel is formed. By reducing the OFF current (the leak current) without also reducing the ON current, a high mutual conductance is realized.

Abstract: A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolithography step is used to expose the source region. Implantation is then performed using one of two types of material. A first type creates electron traps of predetermined energy in the vicinity of the source-body junction. A second type creates defects in the crystalline structure of the semiconductor material. Both implantation types create recombination centers in the material. This allows the discharge through the source-body junction of charges built up in the body region.

Abstract: An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.

Abstract: A semiconductor device comprises a transparent insulating substrate, a first insulating layer, a semiconductor layer, a second insulating layer, and an island-like semiconductor layer in order from the side of the substrate. When the laser light is irradiated from the upper side of the semiconductor device the laser light irradiated to the portions having no island-like semiconductor layer thereon is absorbed by the semiconductor layer after being transmitted through the second insulating layer and the heat generates in the semiconductor layer. Heat diffusion occurs thereafter. At the same time, the energy of laser light by laser radiation from the upper side of the semiconductor device is absorbed in the island-like semiconductor layer. The energy is accumulated as the heat in the island-like semiconductor layer and the second insulating layer to suppress the heat diffusion into the substrate.

Abstract: A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.

Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.

Abstract: On a semiconductor substrate (1), there are provided field oxide films (2,3,4), a gate oxide film (5), thin oxide films (6, 6) with film thickness almost equal to that of the gate oxide film (5), and a gate electrode (7). An oxide film (8) of the same thickness as the gate oxide film (5) is also provided so as to separate the field oxide films (3) and (4), to overlap a portion of the gate electrode (7). A high-concentration impurity layer (11, 12) is formed under each of the thin oxide films (6, 8). Source-drain areas (9, 10) are provided with end portions separated from the high-concentration impurity layer (12) and the field oxide films (3, 4).

Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.

Abstract: A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.

Abstract: A device isolation area structure in a semiconductor device is composed of two layers of a first device isolation film formed by selectively oxidizing a surface of a silicon substrate, and a second device isolation region formed in a single crystal silicon film covering the first device isolation film. A guard band region may be formed within the semiconductor substrate and immediately below the first device isolation film so as to be in contact with the first device isolation film. The device isolation area structure is suitable to high integration of the semiconductor device and provides less possibilities of occurrence of crystal defects.

Abstract: A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following inequality:T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1where K.sub.1 .tbd..epsilon..sub.BOX.sup.-1 (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd..phi..sub.FN +.phi..sub.FP, .epsilon..sub.BOX is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .phi..sub.FN and .phi..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.

Abstract: An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.

Abstract: In a thin film transistor formed by a gate electrode formed on a transparent insulating substrate, a semiconductor active layer opposing the gate electrode, a drain electrode, and a source electrode connected to a transparent pixel electrode, an optical shield layer is located so as to approximately surround the semiconductor active layer.

Abstract: Leakage current due to light incident upon the semiconductor layer which forms the channel of a TFT is eliminated. An insulating layer is formed between one of source and drain electrodes and the semiconductor layer over a distance which is longer than a hole-electron recombination distance, from all the edges of at least one of the source and drain electrodes of the TFT so that it overlaps the semiconductor layer.

Abstract: A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation:T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1where K.sub.1 .tbd..epsilon..sub.BOX (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd.2.PHI..sub.FN +2.PHI..sub.FP -1.03, .epsilon..sub.BOX.sup.-1 is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .PHI..sub.FN and .PHI..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.

Abstract: In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate.

Abstract: A resistor is connected to the source/drain of a transistor and used as a load element of a memory cell. A trench is formed which extends from a top of the wafer through an isolation region of the wafer to a silicon base of the wafer. The silicon base of the wafer is located below the isolation region of the wafer. A resistive layer of material is formed in the trench. The resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically connected to the silicon base of the wafer. The resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material in the trench. In the preferred embodiment, the resistive layer of material is deposited polysilicon.

Abstract: A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high ultraviolet reflectance number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting silicon into only that portion of the silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the silicon layer, to form the N-conductivity well region. The structure is then annealed at a relatively low temperature for several minutes, which is sufficient to activate the phosphorus and to cause local recrystallization of the N-well region of the silicon layer, without essentially causing a redistribution of the phosphorus.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried p-layer (16) and a buried n-well region (26) are formed in order to position p-n junctions beneath n-channel and p-channel devices respectively formed in the outer silicon layer (14) outwardly from the p-layer (16) and (n)-well (26).

Abstract: A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at an end portion of the extended body region, so as to provide a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In addition, in order to inhibit radiation-induced leakage along a backside interface of the extended body region abutting an underlying dielectric substrate, a portion of the extended body region between the channel stop region and the body/channel region has an impurity concentration profile that is increased at the interface of the extended body region with the underlying dielectric substrate.

Abstract: An SOI-type insulated-gate FET is formed such that an electrical resistance across a pn-junction of the source region is less than that across a pn-junction of the drain region. This is accomplished by providing the FET with a metal dopant, such as aluminum or tungsten; by excessively doping the source region; by providing an amorphous source region; or by providing a layer formed of a material having a different thermal expansion coefficient from the thermal expansion coefficient of the material forming the source region, upon the source region. In the thus fabricated transistor, there is generated a carrier generation center or a precipitation of the impurities at a pn-junction formed between the source region and the semiconductor substrate. Thus, a current path is formed across the pn-junction of the source region in both the forward and reverse directions of a diode of the pn-junction, so as to substantially eliminate the potential difference between the source region and the semiconductor substrate.

Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10 .sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.

Abstract: An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.

Abstract: A semiconductor over insulator transistor is provided preferably of a lightly doped drain ("LDD") profile. LDD transistor (74) includes a semiconductor mesa (76) formed over an insulating layer (94) which overlies a semiconductor substrate (96). Semiconductor mesa (76) includes a source region (78) and a drain region (80) at opposite ends thereof. A body node (82) is disposed between source and drain regions (78,80). A low resistance contact region (98) lies along substantially the entire width of body region (82) and contacts a vertical contact which permits electrical contact from the top surface of semiconductor mesa (76) to low resistance contact region (98). Low resistance contact region (98) may be extended to fully underlie source region (78) such that the vertical contact may be moved away from body node (82).