Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract: A thin film transistor and its fabrication method are disclosed wherein the thin film transistor includes a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a membrane layer formed on a portion of the active layer and defining an offset region in the active layer, a gate insulation layer formed on portions of the membrane layer and the active layer, a gate electrode formed on a portion of the gate insulation layer, and a source region and a drain region formed in the active layer.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral MOS device on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and over at least a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A thin film transistor array substrate of a liquid crystal display is provided which includes a substrate, a shorting bar on the substrate, and a plurality of gate lines connected to the shorting bar, each gate line having an electrically non-connection region and a connection region connecting the non-connection region to the shorting bar, wherein said connection region has a thickness such that the gate lines and the shorting bar are electrically separated from each other when the connection regions are anodized.

Abstract: A semiconductor-on-insulator (SOI) device is fabricated by forming spaced apart trenches in a first face of a semiconductor substrate. An insulating layer is formed on the first face of the semiconductor substrate, including on the trenches. A second substrate is bonded to the insulating layer, opposite the semiconductor substrate. The semiconductor substrate is thinned at a second face thereof which is opposite the first face, until a semiconductor film remains on the insulating layer, having alternating thin and thick film semiconductor regions on the insulating layer. Source/drains are formed in the thin film semiconductor regions. Insulated gates are formed on the thick film semiconductor regions, such that a respective insulated gate is located between adjacent source/drains. SOI devices which can suppress floating body effects and yet provide dense integration may thereby be formed.

Abstract: A low cost means is described to semi-isolate the substrate regions of an integrated circuit occupied by a plurality of circuit types with separate power supply connections but with interconnecting signals. The separate power supply connections are made to minimize noise generated by one circuit from coupling into another circuit. One example of integrated circuits with a noise coupling issue are the so called "mixed signal" circuits in which the switching transient noise of digital circuits can interfere with the performance of on board analog circuits. Because of a common substrate, noise injected into the substrate by one circuit can affect the performance of another. This invention reduces the effect of substrate noise by providing an isolation zone around a given circuit type of an integrated circuit by removing the field implant in this zone and placing a deep implant of the same polarity type as substrate in the N channel transistor regions.

Abstract: A gate insulating film 103 is oxidized by a thermal oxidation method using a gate electrode 104 as a mask. At this time, the thickness of the gate insulating film 103 becomes thicker so that the portions indicated by 106 and 107 are obtained. The thickness of an active layer becomes thin at an end 112 of a channel, so that the distance from the gate electrode becomes long by the thickness. Then the strength of an electric field between a source and drain is relaxed by this portion. In this way, a thin film transistor having improved withstand voltage characteristics and leak current characteristics is obtained.

Abstract: A high frequency MOSFET device includes a Silicon-On-Insulator substrate. The MOSFET device has a source electrode connected to the substrate by a conductive region penetrating the insulator layer for dissipating heat from the drive section of an MOSFET to the substrate. The conductive region may be in a grid pattern or lattice configuration, surrounding the drive section of each MOSFET on the SOI substrate, opposite the source electrode of the MOSFET.

Abstract: SOI FETs include an electrically insulating substrate, a semiconductor region on the electrically insulating substrate, a field effect transistor having source, drain and channel regions in the semiconductor region and a metal silicide region between the electrically insulating substrate and the semiconductor region. The metal silicide region (e.g., TiSi.sub.2) forms non-rectifying junctions with the source and channel regions of the field effect transistor so that holes accumulated in the channel region (upon impact ionization) can be readily transported to the source region (and contact thereto) via the metal silicide layer and recombination of the holes with electrons in the source region can be carried out with high efficiency. The metal silicide region ohmically contacts the source and channel regions, but does not form a junction with the drain region of said field effect transistor.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: An active silicon-on-insulator region isolation structure is provided that includes an active bulk substrate region (24), an active silicon-on-insulator region (22), and a transition region positioned between the active bulk substrate region (24) and the active silicon-on-insulator region (22). The active silicon-on-insulator region (22) includes a silicon-on-insulator film (16) positioned above a buried insulator layer (18). The transition region includes a sloping portion of the buried insulator layer (18) and a tapered edge portion of the silicon-on-insulator film (16).

Abstract: An active matrix substrate of a Pixel on Passivation structure includes TFTs and pixel electrodes on an interlayer insulating film over bus lines. The interlayer insulating film is formed of an organic insulating film, and the contact layer of the TFT has a double layer structure of a fine crystal silicon (n.sup.+) layer and an amorphous silicon (n.sup.+) layer the crystal silicon (n.sup.+) layer being placed on the side closer to the source electrode and the drain electrode, and the amorphous silicon (n.sup.+) layer being placed on the opposite side. This improves both the ON characteristics and the OFF characteristics of the TFT are improved, and the stable operative region of the active matrix substrate and the margin to accommodate to variations in threshold value due to aging are expanded, without substantial additional production costs and a decrease in productivity.

Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

Abstract: A miniaturized light valve with a surface area on the order of several centimeters may be successfully formed using a composite substrate and an opposing substrate which has thereon an electrode and which is bonded to the composite substrate at a predetermined gap therefrom. An electro-optical material, such as a liquid crystal compound, is confined within the gap. The composite substrate includes a single crystal layer of a semiconductor material provided on a lower level insulation layer. The single crystal layer is formed with a source region, a drain region, and a channel region of a MOS transistor, and a gate insulation film is provided on the single crystal layer in alignment with the channel region. Further, a gate electrode is provided on the gate insulation film. The composite substrate further includes a pixel electrode on the upper major surface of an insulation layer deposited over the MOS transistor and in contact with the drain region. The single crystal semiconductor thin film is limited to 0.

Abstract: A thin-film transistor (TFT) which has a crystalline silicon active layer of excellent reliability and characteristics, and a method of fabricating such a TFT inexpensively are provided. In a TFT which has at least two low density impurity regions and a source/drain adjacent to a channel-forming region, catalyst elements which cause amorphous silicon to crystallize are included in the source/drain, and the density of said catalyst elements in the interface between the channel-forming region and the low-density impurity regions is less than that in the source/drain.

Abstract: A semiconductor device is provided by forming an insulating film on a supporting substrate and a semiconductor layer on the insulating film, forming an MOS semiconductor component having a source, a drain and a gate on the semiconductor layer, forming at least one of the source region of the semiconductor layer provided with the source and the drain region thereof provided with the drain to have greater thickness than a channel region of the semiconductor layer provided with a gate oxide film and a gate on the gate oxide film, and forming at least one of the source and the drain to be separated from the insulating film by the semiconductor layer of opposite conductivity type therefrom. A bulk layer of the same conductivity type as the semiconductor layer is provided in a thick region of the semiconductor layer. An MNOS or MONOS semiconductor non-volatile memory cell can be formed by replacing the gate oxide film with a memory gate insulating film consisting of a silicon oxide film and a silicon nitride film.

Abstract: A MOS type field effect transistor including a portion of silicon layer (114) forming an active region (114a) placed between a grid oxide layer (120) and a buried oxide layer (112), and laterally delimited by lateral oxide insulation blocks (116). The portion of the silicon layer (114) has concave edges (122, 124) facing the lateral oxide insulation blocks (116). The transistor is applicable to the manufacture of integrated circuits with low electricity consumption.

Abstract: An aluminum gate for a thin film transistor is fabricating by implanting ions into the exposed surface of the aluminum gate. The ions are preferably selected from the group consisting of nitrogen, carbon, oxygen and boron ions. A composite layer of aluminum and the implanted ions thereby formed at the exposed surface of the aluminum layer. Gates for thin film transistors, including an aluminum layer and a composite layer of aluminum and another element at the surface thereof can suppress hillocks in the aluminum gate which may be caused by compressive stresses during subsequent fabrication steps. The composite layer can have a low resistance and can allow a direct contact with an indium tin oxide conductive layer.

Abstract: A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.

Abstract: Silicon is formed at selected locations on a silicon-on-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the wafer, is formed on an overall surface of the substrate.

Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.

Abstract: The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes.

Abstract: The present invention provides a contact hole structure in a field effect transistor having a semiconductor layer extending over an insulation region, a control electrode provided on an insulation film on the semiconductor layer, and an inter-layer insulator covering the semiconductor layer and the control electrode. The semiconductor layer further comprises a drain region of a first conductivity type extending on the insulation region, an intermediate region of a second conductivity type extending on the insulation region and also being in contact with the drain region so that the intermediate region is positioned under the control electrode, and a laminated region in contact with the intermediate region so that the laminated region is separated by the intermediate region from the drain region. The laminated region comprises a base layer of the second conductivity type on the insulation region and a source region of the first conductivity type laminated on the base layer.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: A semiconductor device (120) is formed in a silicon-on-insulator (SOI) substrate (135). The semiconductor device (120) has a channel region (126) that is controlled by a gate structure (129). The channel region (126) has a doping profile that is essentially uniform where the channel region (126) is under the gate structure (129). This eliminates the parasitic channel region that is common with conventional field effect transistors (FETs) that are formed in SOI substrates. Consequently, the semiconductor device (120) of the present invention does not suffer from the "kink" problem that is common to conventional FET devices.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: Protection circuits for preventing an internal circuit on a semiconductor substrate from destroying due to an excess voltage are formed on the output end and input end of an internal circuit. The protection circuit on the input end has a gate electrode comprised of a band-like conductive film. This gate electrode is grounded and has a shape zigzagging in a waveform with crests and troughs alternately appearing in a planar view. A drain diffusion layer connected to an output end of the internal circuit is formed in one of two diffusion regions of the surface of the semiconductor substrate that are defined by the gate electrode, and a source diffusion layer grounded is formed in the other region. The source diffusion layer and the drain diffusion layer are formed integral with each other, so that the protection circuit on the input end is substantially constituted of one buffer transistor.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

Abstract: The side surfaces of an active layer from which a thin-film transistor is constructed are annealed by laser light irradiation. Defects which occur during patterning concentrate at the side surfaces of the active layer, and due to the movement of carriers which results from these defects, an OFF current is generated. Thus, by improving the crystallinity of the side surfaces of the active layer and thereby reducing the number of defects it is possible to reduce the OFF current.

Abstract: A thin-film transistor of a type constructed of the semiconductor region on top of an insulating substrate and the gate electrode on the gate insulating layer on top of the channel of the semiconductor region. The thin-film transistor contains an impurity region of opposite semiconductor type of a source region and a drain region, at least where the side wall of the semiconductor region borders the gate electrode via the insulating layer. The impurity region is doped with a higher impurity concentration than the other semiconductor regions. The above arrangement dramatically lowers current leak in the thin-film transistor, and offers a substantially improved manufacturing yield of thin-film transistor.

Abstract: In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into the active layer. A thin film comprising SiO.sub.x N.sub.y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO.sub.x N.sub.y. Also, a thin film comprising SiO.sub.x N.sub.y is formed under the active layer. The active layer includes a metal element at a concentration of 1.times.10.sup.15 to 1.times.10.sup.19 cm.sup.-3 and hydrogen at a concentration of 2.times.10.sup.19 to 5.times.10.sup.21 cm.sup.-3.

Abstract: An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or semi-amorphous semiconductor material; and a region provided under said channel region, said region comprising an amorphous material containing the same material as that of the channel region as the principal component, or said region comprising a material having a band gap larger than said channel region. A process for fabricating the device is also disclosed.

Abstract: In a monolithic active matrix circuit that uses offset-gate TFTs in which the gate electrode is offset from the source and drain regions or TFTs whose gate insulating film is formed by vapor deposition, not only an active matrix circuit but also a drive circuit therefor is formed by using P-channel TFTs.

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate.

Abstract: A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a semiconductor element having a pn-junction is included in the semiconductor substrate. The semiconductor integrated circuit device having the SOI structure is formed with a semiconductor layer, or SOI layer, on a p-type semiconductor substrate through a buried insulating film and further with semiconductor circuit elements serving as functional elements at the SOI layer thus formed. As a protection transistor to protect the semiconductor circuit elements, a MOSFET may be formed in which n-type diffusion layers are formed in the semiconductor substrate. The n-type diffusion layers of the MOSFET are to be surrounded by p-type diffusion layers more highly doped than the semiconductor substrate.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: A semiconductor device includes a flat, square n-type diffusion layer, a p-type channel stopper region, and an electrode. The n-type diffusion layer is formed to be isolated in a check element region of a p-type semiconductor substrate or a p-type well covered with a field oxide film and having circuit element regions and the check element region sandwiched therebetween. The p-type channel stopper region is formed to contact at least one side of the n-type diffusion layer. The electrode is extracted from the n-type diffusion layer through a contact hole. The n-type diffusion layer, the p-type channel stopper region, and the electrode constitute the check element for checking a state of the p-type channel stopper region by measuring a junction breakdown voltage of the n-type diffusion layer.

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Abstract: An H-transistor, fabricated in a silicon-on-insulator ("SOI") substrate, includes opposing source and drain terminals or regions flanking a centrally-located body node or well. Above the body node or well is formed the H-shaped gate terminal of the transistor. One or more shunt body contacts or ties bisect the source terminal and connect the source terminal of the transistor to the underlying body node. In this way, the body node or well is no longer electrically "floating", but, instead, is connected to the fixed ground potential of the source terminal of the transistor.

Abstract: A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.

Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

Abstract: A semiconductor device includes an insulating support. A strip of semiconductor material has two ends in contact with the insulating support and a midsection extending between the ends. A dielectric layer encircles the midsection, and a conductive layer encircles the dielectric layer. The conductive layer has a substantially constant width such that a gate electrode formed within the conductive layer is fully self-aligned with drain and source regions formed within the ends.

Abstract: A semiconductor memory and device comprising a plurality of N-channel and P-channel transistor regions, a first and a second field shield region, and an oxide isolation region. The first field shield region is disposed so as to isolate the N-channel transistor regions from one another, and the second field shield region is provided to isolate the P-channel transistor regions from one another. The oxide isolation region is furnished to isolate the N-channel transistor regions from the P-channel transistor regions. The isolation effected by the field shield regions and the isolation provided by the oxide isolation region combine to suppress latch-up, fix the potential in the body regions of the MOS transistors making up the memory or device, and minimize the layout area of the memory or device.

Abstract: An SOI substrate comprises a buried silicon oxide layer formed directly under an active silicon layer, and a layer containing phosphorus therein formed under the buried silicon oxide layer. The layer containing phosphorus therein acts as the getter layer, so that an effective gettering of heavy metals can be obtained in a wide temperature range from a low temperature region to a high temperature region. In addition, since the silicon oxide layer exists between the active layer and the getter layer, the diffusion of the phosphorus into the active layer is effectively prevented, and therefore, the phosphorus scarely diffuses to the active layer, so that the device manufactured is subjected to almost no adverse influence of the diffusion of the phosphorus.

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike.

Abstract: A thin film transistor for incorporation into an active-matrix liquid crystal display includes an active layer provided on a substrate. An electrode insulating layer is formed on the active layer, and a gate electrode including first and second gate layers is provided on the electrode insulating layer. The second gate layer overlies the first gate layer and has a width greater than the first gate layer. LDD regions, self-aligned with the second gate layer are provided in the active layer adjacent source and drain regions. The active layer further including a channel region located under the first gate layer and offset regions located under portions of the second gate layer extending beyond the first gate layer at opposite sides of the channel region.

Abstract: A semiconductor device having the SOI structure is provided, which enables to reduce the size of components compared with the conventional semiconductor devices. The device contains a first insulator film formed on a semiconductor substrate, and semiconductor islands formed on the first insulator film. Each of the islands has an electronic component. The device further contains semiconductor sidewalls formed to surround the respective islands. The sidewalls are contacted with outer sides of the corresponding islands. Electrodes are formed outside the islands to be contacted with the corresponding sidewalls. A second insulator film is formed on the exposed first insulator film from the islands to laterally isolate the respective islands and the corresponding sidewalls from each other. The electronic components are electrically connected to the respective electrodes through the corresponding sidewalls.

Abstract: A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied.