Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.

Abstract: There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: To fabricate a crystalline semiconductor film with controlled locations and sizes of the crystal grains, and to utilize the crystalline semiconductor film in the channel-forming region of a TFT in order to realize a high-speed operable TFT. A translucent insulating thermal conductive layer 2 is provided in close contact with the main surface of a substrate 1, and an insular or striped first insulating layer 3 is formed in selected regions on the thermal conductive layer. A second insulating layer 4 and semiconductor film 5 are laminated thereover. The semiconductor film 5 is first formed with an amorphous semiconductor film, and then crystallized by laser annealing. The first insulating layer 3 has the function of controlling the rate of heat flow to the thermal conductive layer 2, and the temperature distribution difference on the substrate 1 is utilized to form a single-crystal semiconductor film on the first insulating layer 3.

Abstract: A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.

Abstract: An improved silicon on sapphire structure and/or device has one or more buffer layers. In a first preferred embodiment, the buffer layer is layer of silicon oxide material that prevents the stress induced defects in the silicon layer. In an alternative embodiment, the buffer layer comprises two layers. A first silicon oxide layer attached to the silicon to insure a perfect interface between the silicon. A second silicon oxide layer then is attached to the sapphire layer. The first and second silicon oxide layers are then attached, e.g., by a wafer bonding technique. This structure has no conductive paths beneath the oxide insulator(s) and therefore enables improved performance in radio frequency applications.

Abstract: A source and a drain of a field-effect transistor are formed so as to fulfill a specified physical relationship to upper and lower gates thereof and thereby parasitic capacitance that hampers its high-speed operation is minimized. The filed-effect transistor includes a second support substrate, a lower gate that is embedded in an insulator formed on the second support substrate, an insulating layer formed on the lower gate, a semiconductor layer formed on the insulating layer, an insulating layer formed on the semiconductor layer, an upper gate formed on the insulating layer, as well as a source electrode, a drain electrode, an upper gate electrode, and a lower gate electrode all of which are isolated from one another by the insulating layer.

Abstract: Disclosed are an SOI device having no edge leakage current and a method of fabricating the same. The SOI device comprises: an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; an oxide layer formed to be in contact with the buried oxide layer at the semiconductor layer portion corresponding to a field region so that an active region is defined; a gate electrode pattern having a gate oxide layer, the gate oxide layer only formed on the active region; a source region and a drain region formed inside the active region of the semiconductor layer of both sides of the gate electrode pattern; and a gate electrode line formed on the gate electrode pattern and on the field region so as to interconnect the gate electrode patterns of the respective active regions arranged in a line.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: A transistor on an SOI wafer has a subsurface recombination area at least partially within its body. The recombination area includes one or more damaged recombination regions. The damaged recombination region(s) may be formed by a damaging implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. Alignment of the damaged recombination region(s) is improved by forming the source and drain of the transistor prior to removal of the dummy gate, using the dummy gate as a doping mask.

Abstract: In order to provide a semiconductor substrate that can be an SOI substrate suitable for production of high-frequency transistor, the semiconductor substrate is produced by a method of producing the semiconductor substrate having a step of bonding a first base having a semiconductor layer region to a second base and a step of removing the first base while leaving the semiconductor layer region on the second base, wherein a magnitude relation between the concentration of a p-type impurity and the concentration of an n-type impurity in the bonding atmosphere is established according to the composition of the second base.

Abstract: To present a SOI type MOS element excellent in yield, performance and characteristic, easy in manufacture, and low in cost, and a method of manufacturing the same. A SOI type MOS transistor structure comprising polysilicon electrodes 128 for gate, source and drain composed by burying into trench holes 120a, 120b, 120c respectively formed in a semiconductor substrate 110, a gate oxide film 122 formed in the entire inside of the trench hole 120a, N-diffusion layer 124 and N+ diffusion layer 126 formed in the entire inside of the trench holes 120b and 120c, and a thick SiO2 film 114 in a trench hole 113 formed in the semiconductor substrate 110 so as to surround the transistor.

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract: An SOI wafer has a set of gettering sites formed in the device layer, optionally extending through the buried insulator; the gettering sites being formed within the source/drain regions of transistors.

Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

Abstract: Provided are a semiconductor device capable of satisfactorily solving a floating-body problem and a hot carrier problem which often arise in an SOI device and of causing a widely distributed partial isolating film to generate a crystal defect for peripheral structures with difficulty and a method of manufacturing the semiconductor device. A dummy region DM1 having no function as an element is formed at almost regular intervals in a partial isolating film 5b provided between MOS transistors TR1. Consequently, the occupation rate of the dummy region DM1 having a lower resistance value than that of a silicon layer 3b provided under the partial isolating film 5b is increased so that the floating-body problem and the hot carrier problem can be solved.

Abstract: A lightly doped region (3) of N-type or P-type isolated from one component region and another is formed out of a surface silicon layer of an SOI substrate (1), a gate electrode (21) is provided above the lightly doped region (3) with a gate oxidation film (15) therebetween, a drain region (5) and a source region (7) made by making the lightly doped region (3) on the front face side different in conduction type from the lightly doped region (3) are provided respectively on both sides of the gate electrode (21), and a leakage stopping layer (13) which is the same in conduction type as the lightly doped region (3) and higher in impurity concentration than the lightly doped region (3) is provided between the source region (7) and a buried oxidation film (19).

Abstract: A protection circuit structure for use with silicon-on-insulator integrated circuits is provided so as to improve electrostatic discharge protection capability. The protection circuit structure includes a P/N junction defining a protection diode. The protection diode is formed underneath an electrically conductive input pad associated with a conventional SOI semiconductor device.

Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 Å to 4 &mgr;m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7×1019 atoms.cm−3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7×1019 atoms.cm−3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5×1018 atoms.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.

Abstract: A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

Abstract: A semiconductor device comprises an embedded insulation layer 101 formed on a semiconductor substrate 100, plural power semiconductor elements 2, 3 formed on a semiconductor substrate 100 on the embedded insulation layer, a trench 4 formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator 5 insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements 2, 3 such as transistors can be used, being connected each other in series.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. An interface between the insulator layer and the semiconductor layer bleeds off extra carriers. Active regions are defined in the semiconductor layer by isolation trenches and the insulator layer.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. A plurality of transistor active regions and at least one body contact active region are formed on an SOI substrate. A semiconductor residue layer, which is thinner than the transistor active regions and the body contact active region, is disposed between the transistor active regions and the body contact active region. The transistor active regions, the body contact active region and the semiconductor residue layer are disposed on a buried insulating layer of the SOI substrate. The semiconductor residue layer is covered with a partial trench isolation layer. A bar-shaped full trench isolation layer is interposed between the adjacent transistor active regions. The full trench isolation layer is in contact with sidewalls of the transistor active regions adjacent thereto and is in contact with the buried insulating layer between the adjacent transistor active regions.

Abstract: A semiconductor device of a SOI (silicon on insulator) structure includes a P-type silicon support substrate, a first insulating layer formed on the semiconductor support substrate, and an SOI layer formed on the first insulating layer. A first hole is formed to penetrate through the semiconductor layer and the first insulating layer, and a P-type polysilicon layer is filled in the first hole so that the P-type polysilicon layer is electrically connected to the semiconductor support substrate. A second insulating layer is formed on the SOI layer. A second hole is formed to penetrate through the second insulating layer in alignment with the first hole, and an aluminum electrode is formed on the second insulating layer to fill the second hole, so that the aluminum electrode is electrically connected through the P-type polysilicon layer to the silicon support substrate. Thus, the potential of the silicon support substrate can be fixed through the aluminum electrode formed on the SOI layer side.

Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a polysilicon layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: For forming a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a gate dielectric and a gate electrode are formed on the semiconductor material, and spacers are formed on sidewalls of the gate electrode and the gate dielectric. The spacers cover portions of the semiconductor material. A dopant is implanted into exposed regions of the semiconductor material to form a drain doped region and a source doped region. A portion of the drain doped region and a portion of the source doped region extend under the spacers. A drain contact silicide is formed with an exposed portion of the drain doped region, and a source contact silicide is formed with an exposed portion of the source doped region. The spacers are removed to expose the portions of the semiconductor material including a portion of the drain doped region and a portion of the source doped region.

Abstract: An SOI layer is thickened. A channel region formed in the SOI layer has an impurity concentration profile having a single peak. The peak position is set to the depth of the interface between the SOI layer and a buried insulating layer, or set to a position deeper than that. Provision is made for improving radiation resistance and setting threshold voltage to a desirable voltage.

Abstract: An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device layer 20 is formed on the outer surface of buried insulator layer 18. An inductive well 22 can be formed to provide a platform for the formation of inductive devices 34 within an inductive region 26.

Abstract: A thin film semiconductor device comprising an insulating substrate, a plurality of thin film transistors integrated on the insulating substrate, each thin film transistor including a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, and the semiconductor thin film being formed with a channel region confronting the gate electrode, and a source region and a drain region which are located at both sides of the channel region, and a conductor film which is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region. A display device having a pair of insulating substrates, electrooptical material held in the gap between the insulating substrates, a counter electrode formed in one of the insulating substrates, and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate.

Abstract: A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

Abstract: In a semiconductor device which has capacitors respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating surface, whereby high-speed, high-precision processing of signals having a large number of bits supplied from the multiple input terminals is realized by a small circuit scale.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: A method has been provided to form a sheet of large grain crystallized silicon, in an early stage of transistor production, before the areas of the source and drain are defined. The method takes advantage of high annealing temperatures and transition metals to speed the lateral growth of silicide. By using higher temperatures, the number of amorphous enclaves is minimized and the transition metal nucleation site can be made small. A small transition metal nucleation site, in turn, can be more easily located near the center of a transistor, or where it is convenient. After annealing, the areas close to the silicide nucleation site are transformed into polycrystalline with a high electron mobility, desirable for the formation of source/drain and channel regions. Silicide products, away from the transistor active areas, are etched away when the area of the source and drain are defined. A product by process using the method of the above-described invention is also provided.

Abstract: A thin film semiconductor device comprising an insulating substrate, a plurality of thin film transistors integrated on the insulating substrate, each thin film transistor including a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, and the semiconductor thin film being formed with a channel region confronting the gate electrode, and a source region and a drain region which are located at both sides of the channel region, and a conductor film which is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region. A display device having a pair of insulating substrates, electrooptical material held in the gap between the insulating substrates, a counter electrode formed in one of the insulating substrates, and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: An FET device comprises a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.